1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 
28 #include "amdgpu.h"
29 #include "amdgpu_ucode.h"
30 
31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32 {
33 	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 	DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 		  le32_to_cpu(hdr->ucode_array_offset_bytes));
43 	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44 }
45 
46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47 {
48 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50 
51 	DRM_DEBUG("MC\n");
52 	amdgpu_ucode_print_common_hdr(hdr);
53 
54 	if (version_major == 1) {
55 		const struct mc_firmware_header_v1_0 *mc_hdr =
56 			container_of(hdr, struct mc_firmware_header_v1_0, header);
57 
58 		DRM_DEBUG("io_debug_size_bytes: %u\n",
59 			  le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 		DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 			  le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 	} else {
63 		DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 	}
65 }
66 
67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68 {
69 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71 	const struct smc_firmware_header_v1_0 *v1_0_hdr;
72 	const struct smc_firmware_header_v2_0 *v2_0_hdr;
73 	const struct smc_firmware_header_v2_1 *v2_1_hdr;
74 
75 	DRM_DEBUG("SMC\n");
76 	amdgpu_ucode_print_common_hdr(hdr);
77 
78 	if (version_major == 1) {
79 		v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
80 		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
81 	} else if (version_major == 2) {
82 		switch (version_minor) {
83 		case 0:
84 			v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
85 			DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
86 			DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
87 			break;
88 		case 1:
89 			v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
90 			DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
91 			DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
92 			break;
93 		default:
94 			break;
95 		}
96 
97 	} else {
98 		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
99 	}
100 }
101 
102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
103 {
104 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
105 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
106 
107 	DRM_DEBUG("GFX\n");
108 	amdgpu_ucode_print_common_hdr(hdr);
109 
110 	if (version_major == 1) {
111 		const struct gfx_firmware_header_v1_0 *gfx_hdr =
112 			container_of(hdr, struct gfx_firmware_header_v1_0, header);
113 
114 		DRM_DEBUG("ucode_feature_version: %u\n",
115 			  le32_to_cpu(gfx_hdr->ucode_feature_version));
116 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
117 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
118 	} else {
119 		DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
120 	}
121 }
122 
123 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
124 {
125 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
126 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
127 
128 	DRM_DEBUG("RLC\n");
129 	amdgpu_ucode_print_common_hdr(hdr);
130 
131 	if (version_major == 1) {
132 		const struct rlc_firmware_header_v1_0 *rlc_hdr =
133 			container_of(hdr, struct rlc_firmware_header_v1_0, header);
134 
135 		DRM_DEBUG("ucode_feature_version: %u\n",
136 			  le32_to_cpu(rlc_hdr->ucode_feature_version));
137 		DRM_DEBUG("save_and_restore_offset: %u\n",
138 			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
139 		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
140 			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
141 		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
142 			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
143 		DRM_DEBUG("master_pkt_description_offset: %u\n",
144 			  le32_to_cpu(rlc_hdr->master_pkt_description_offset));
145 	} else if (version_major == 2) {
146 		const struct rlc_firmware_header_v2_0 *rlc_hdr =
147 			container_of(hdr, struct rlc_firmware_header_v2_0, header);
148 
149 		DRM_DEBUG("ucode_feature_version: %u\n",
150 			  le32_to_cpu(rlc_hdr->ucode_feature_version));
151 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
152 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
153 		DRM_DEBUG("save_and_restore_offset: %u\n",
154 			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
155 		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
156 			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
157 		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
158 			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
159 		DRM_DEBUG("reg_restore_list_size: %u\n",
160 			  le32_to_cpu(rlc_hdr->reg_restore_list_size));
161 		DRM_DEBUG("reg_list_format_start: %u\n",
162 			  le32_to_cpu(rlc_hdr->reg_list_format_start));
163 		DRM_DEBUG("reg_list_format_separate_start: %u\n",
164 			  le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
165 		DRM_DEBUG("starting_offsets_start: %u\n",
166 			  le32_to_cpu(rlc_hdr->starting_offsets_start));
167 		DRM_DEBUG("reg_list_format_size_bytes: %u\n",
168 			  le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
169 		DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
170 			  le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
171 		DRM_DEBUG("reg_list_size_bytes: %u\n",
172 			  le32_to_cpu(rlc_hdr->reg_list_size_bytes));
173 		DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
174 			  le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
175 		DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
176 			  le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
177 		DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
178 			  le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
179 		DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
180 			  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
181 		DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
182 			  le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
183 		if (version_minor == 1) {
184 			const struct rlc_firmware_header_v2_1 *v2_1 =
185 				container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
186 			DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
187 				  le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
188 			DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
189 				  le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
190 			DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
191 				  le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
192 			DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
193 				  le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
194 			DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
195 				  le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
196 			DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
197 				  le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
198 			DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
199 				  le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
200 			DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
201 				  le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
202 			DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
203 				  le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
204 			DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
205 				  le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
206 			DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
207 				  le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
208 			DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
209 				  le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
210 			DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
211 				  le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
212 		}
213 	} else {
214 		DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
215 	}
216 }
217 
218 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
219 {
220 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
221 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
222 
223 	DRM_DEBUG("SDMA\n");
224 	amdgpu_ucode_print_common_hdr(hdr);
225 
226 	if (version_major == 1) {
227 		const struct sdma_firmware_header_v1_0 *sdma_hdr =
228 			container_of(hdr, struct sdma_firmware_header_v1_0, header);
229 
230 		DRM_DEBUG("ucode_feature_version: %u\n",
231 			  le32_to_cpu(sdma_hdr->ucode_feature_version));
232 		DRM_DEBUG("ucode_change_version: %u\n",
233 			  le32_to_cpu(sdma_hdr->ucode_change_version));
234 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
235 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
236 		if (version_minor >= 1) {
237 			const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
238 				container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
239 			DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
240 		}
241 	} else {
242 		DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
243 			  version_major, version_minor);
244 	}
245 }
246 
247 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
248 {
249 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
250 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
251 
252 	DRM_DEBUG("PSP\n");
253 	amdgpu_ucode_print_common_hdr(hdr);
254 
255 	if (version_major == 1) {
256 		const struct psp_firmware_header_v1_0 *psp_hdr =
257 			container_of(hdr, struct psp_firmware_header_v1_0, header);
258 
259 		DRM_DEBUG("ucode_feature_version: %u\n",
260 			  le32_to_cpu(psp_hdr->ucode_feature_version));
261 		DRM_DEBUG("sos_offset_bytes: %u\n",
262 			  le32_to_cpu(psp_hdr->sos_offset_bytes));
263 		DRM_DEBUG("sos_size_bytes: %u\n",
264 			  le32_to_cpu(psp_hdr->sos_size_bytes));
265 		if (version_minor == 1) {
266 			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
267 				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
268 			DRM_DEBUG("toc_header_version: %u\n",
269 				  le32_to_cpu(psp_hdr_v1_1->toc_header_version));
270 			DRM_DEBUG("toc_offset_bytes: %u\n",
271 				  le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
272 			DRM_DEBUG("toc_size_bytes: %u\n",
273 				  le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
274 			DRM_DEBUG("kdb_header_version: %u\n",
275 				  le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
276 			DRM_DEBUG("kdb_offset_bytes: %u\n",
277 				  le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
278 			DRM_DEBUG("kdb_size_bytes: %u\n",
279 				  le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
280 		}
281 		if (version_minor == 2) {
282 			const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
283 				container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
284 			DRM_DEBUG("kdb_header_version: %u\n",
285 				  le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
286 			DRM_DEBUG("kdb_offset_bytes: %u\n",
287 				  le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
288 			DRM_DEBUG("kdb_size_bytes: %u\n",
289 				  le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
290 		}
291 		if (version_minor == 3) {
292 			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
293 				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
294 			const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
295 				container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
296 			DRM_DEBUG("toc_header_version: %u\n",
297 				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version));
298 			DRM_DEBUG("toc_offset_bytes: %u\n",
299 				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes));
300 			DRM_DEBUG("toc_size_bytes: %u\n",
301 				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes));
302 			DRM_DEBUG("kdb_header_version: %u\n",
303 				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version));
304 			DRM_DEBUG("kdb_offset_bytes: %u\n",
305 				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes));
306 			DRM_DEBUG("kdb_size_bytes: %u\n",
307 				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes));
308 			DRM_DEBUG("spl_header_version: %u\n",
309 				  le32_to_cpu(psp_hdr_v1_3->spl_header_version));
310 			DRM_DEBUG("spl_offset_bytes: %u\n",
311 				  le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes));
312 			DRM_DEBUG("spl_size_bytes: %u\n",
313 				  le32_to_cpu(psp_hdr_v1_3->spl_size_bytes));
314 		}
315 	} else {
316 		DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
317 			  version_major, version_minor);
318 	}
319 }
320 
321 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
322 {
323 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
324 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
325 
326 	DRM_DEBUG("GPU_INFO\n");
327 	amdgpu_ucode_print_common_hdr(hdr);
328 
329 	if (version_major == 1) {
330 		const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
331 			container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
332 
333 		DRM_DEBUG("version_major: %u\n",
334 			  le16_to_cpu(gpu_info_hdr->version_major));
335 		DRM_DEBUG("version_minor: %u\n",
336 			  le16_to_cpu(gpu_info_hdr->version_minor));
337 	} else {
338 		DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
339 	}
340 }
341 
342 int amdgpu_ucode_validate(const struct firmware *fw)
343 {
344 	const struct common_firmware_header *hdr =
345 		(const struct common_firmware_header *)fw->data;
346 
347 	if (fw->size == le32_to_cpu(hdr->size_bytes))
348 		return 0;
349 
350 	return -EINVAL;
351 }
352 
353 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
354 				uint16_t hdr_major, uint16_t hdr_minor)
355 {
356 	if ((hdr->common.header_version_major == hdr_major) &&
357 		(hdr->common.header_version_minor == hdr_minor))
358 		return false;
359 	return true;
360 }
361 
362 enum amdgpu_firmware_load_type
363 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
364 {
365 	switch (adev->asic_type) {
366 #ifdef CONFIG_DRM_AMDGPU_SI
367 	case CHIP_TAHITI:
368 	case CHIP_PITCAIRN:
369 	case CHIP_VERDE:
370 	case CHIP_OLAND:
371 	case CHIP_HAINAN:
372 		return AMDGPU_FW_LOAD_DIRECT;
373 #endif
374 #ifdef CONFIG_DRM_AMDGPU_CIK
375 	case CHIP_BONAIRE:
376 	case CHIP_KAVERI:
377 	case CHIP_KABINI:
378 	case CHIP_HAWAII:
379 	case CHIP_MULLINS:
380 		return AMDGPU_FW_LOAD_DIRECT;
381 #endif
382 	case CHIP_TOPAZ:
383 	case CHIP_TONGA:
384 	case CHIP_FIJI:
385 	case CHIP_CARRIZO:
386 	case CHIP_STONEY:
387 	case CHIP_POLARIS10:
388 	case CHIP_POLARIS11:
389 	case CHIP_POLARIS12:
390 	case CHIP_VEGAM:
391 		return AMDGPU_FW_LOAD_SMU;
392 	case CHIP_VEGA10:
393 	case CHIP_RAVEN:
394 	case CHIP_VEGA12:
395 	case CHIP_VEGA20:
396 	case CHIP_ARCTURUS:
397 	case CHIP_RENOIR:
398 	case CHIP_NAVI10:
399 	case CHIP_NAVI14:
400 	case CHIP_NAVI12:
401 	case CHIP_SIENNA_CICHLID:
402 	case CHIP_NAVY_FLOUNDER:
403 	case CHIP_VANGOGH:
404 	case CHIP_DIMGREY_CAVEFISH:
405 		if (!load_type)
406 			return AMDGPU_FW_LOAD_DIRECT;
407 		else
408 			return AMDGPU_FW_LOAD_PSP;
409 	default:
410 		DRM_ERROR("Unknown firmware load type\n");
411 	}
412 
413 	return AMDGPU_FW_LOAD_DIRECT;
414 }
415 
416 #define FW_VERSION_ATTR(name, mode, field)				\
417 static ssize_t show_##name(struct device *dev,				\
418 			  struct device_attribute *attr,		\
419 			  char *buf)					\
420 {									\
421 	struct drm_device *ddev = dev_get_drvdata(dev);			\
422 	struct amdgpu_device *adev = drm_to_adev(ddev);			\
423 									\
424 	return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field);	\
425 }									\
426 static DEVICE_ATTR(name, mode, show_##name, NULL)
427 
428 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
429 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
430 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
431 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
432 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
433 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
434 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
435 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
436 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
437 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
438 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
439 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
440 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version);
441 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version);
442 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version);
443 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version);
444 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
445 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
446 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
447 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
448 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
449 
450 static struct attribute *fw_attrs[] = {
451 	&dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
452 	&dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
453 	&dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
454 	&dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
455 	&dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
456 	&dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
457 	&dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
458 	&dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
459 	&dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
460 	&dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
461 	&dev_attr_dmcu_fw_version.attr, NULL
462 };
463 
464 static const struct attribute_group fw_attr_group = {
465 	.name = "fw_version",
466 	.attrs = fw_attrs
467 };
468 
469 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
470 {
471 	return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
472 }
473 
474 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
475 {
476 	sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
477 }
478 
479 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
480 				       struct amdgpu_firmware_info *ucode,
481 				       uint64_t mc_addr, void *kptr)
482 {
483 	const struct common_firmware_header *header = NULL;
484 	const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
485 	const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
486 	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
487 	const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
488 
489 	if (NULL == ucode->fw)
490 		return 0;
491 
492 	ucode->mc_addr = mc_addr;
493 	ucode->kaddr = kptr;
494 
495 	if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
496 		return 0;
497 
498 	header = (const struct common_firmware_header *)ucode->fw->data;
499 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
500 	dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
501 	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
502 	mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
503 
504 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
505 	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
506 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
507 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
508 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
509 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&
510 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&
511 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
512 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
513 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
514 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&
515 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&
516 		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
517 		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
518 		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
519 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
520 
521 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
522 					      le32_to_cpu(header->ucode_array_offset_bytes)),
523 		       ucode->ucode_size);
524 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
525 		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
526 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
527 			le32_to_cpu(cp_hdr->jt_size) * 4;
528 
529 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
530 					      le32_to_cpu(header->ucode_array_offset_bytes)),
531 		       ucode->ucode_size);
532 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
533 		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
534 		ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
535 
536 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
537 					      le32_to_cpu(header->ucode_array_offset_bytes) +
538 					      le32_to_cpu(cp_hdr->jt_offset) * 4),
539 		       ucode->ucode_size);
540 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
541 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
542 				le32_to_cpu(dmcu_hdr->intv_size_bytes);
543 
544 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
545 					      le32_to_cpu(header->ucode_array_offset_bytes)),
546 		       ucode->ucode_size);
547 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
548 		ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
549 
550 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
551 					      le32_to_cpu(header->ucode_array_offset_bytes) +
552 					      le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
553 		       ucode->ucode_size);
554 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
555 		ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
556 		memcpy(ucode->kaddr,
557 		       (void *)((uint8_t *)ucode->fw->data +
558 				le32_to_cpu(header->ucode_array_offset_bytes)),
559 		       ucode->ucode_size);
560 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
561 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
562 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
563 		       ucode->ucode_size);
564 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
565 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
566 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
567 		       ucode->ucode_size);
568 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
569 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
570 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
571 		       ucode->ucode_size);
572 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {
573 		ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
574 		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,
575 		       ucode->ucode_size);
576 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {
577 		ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
578 		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,
579 		       ucode->ucode_size);
580 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
581 		ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
582 		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
583 			      le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),
584 		       ucode->ucode_size);
585 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {
586 		ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
587 		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
588 			      le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),
589 		       ucode->ucode_size);
590 	}
591 
592 	return 0;
593 }
594 
595 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
596 				uint64_t mc_addr, void *kptr)
597 {
598 	const struct gfx_firmware_header_v1_0 *header = NULL;
599 	const struct common_firmware_header *comm_hdr = NULL;
600 	uint8_t *src_addr = NULL;
601 	uint8_t *dst_addr = NULL;
602 
603 	if (NULL == ucode->fw)
604 		return 0;
605 
606 	comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
607 	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
608 	dst_addr = ucode->kaddr +
609 			   ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
610 			   PAGE_SIZE);
611 	src_addr = (uint8_t *)ucode->fw->data +
612 			   le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
613 			   (le32_to_cpu(header->jt_offset) * 4);
614 	memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
615 
616 	return 0;
617 }
618 
619 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
620 {
621 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
622 		amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
623 			amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
624 			&adev->firmware.fw_buf,
625 			&adev->firmware.fw_buf_mc,
626 			&adev->firmware.fw_buf_ptr);
627 		if (!adev->firmware.fw_buf) {
628 			dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
629 			return -ENOMEM;
630 		} else if (amdgpu_sriov_vf(adev)) {
631 			memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
632 		}
633 	}
634 	return 0;
635 }
636 
637 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
638 {
639 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
640 		amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
641 		&adev->firmware.fw_buf_mc,
642 		&adev->firmware.fw_buf_ptr);
643 }
644 
645 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
646 {
647 	uint64_t fw_offset = 0;
648 	int i;
649 	struct amdgpu_firmware_info *ucode = NULL;
650 
651  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
652 	if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
653 		return 0;
654 	/*
655 	 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
656 	 * ucode info here
657 	 */
658 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
659 		if (amdgpu_sriov_vf(adev))
660 			adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
661 		else
662 			adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
663 	} else {
664 		adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
665 	}
666 
667 	for (i = 0; i < adev->firmware.max_ucodes; i++) {
668 		ucode = &adev->firmware.ucode[i];
669 		if (ucode->fw) {
670 			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
671 						    adev->firmware.fw_buf_ptr + fw_offset);
672 			if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
673 			    adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
674 				const struct gfx_firmware_header_v1_0 *cp_hdr;
675 				cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
676 				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
677 						    adev->firmware.fw_buf_ptr + fw_offset);
678 				fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
679 			}
680 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
681 		}
682 	}
683 	return 0;
684 }
685