1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 32 { 33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 42 le32_to_cpu(hdr->ucode_array_offset_bytes)); 43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 44 } 45 46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 47 { 48 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 50 51 DRM_DEBUG("MC\n"); 52 amdgpu_ucode_print_common_hdr(hdr); 53 54 if (version_major == 1) { 55 const struct mc_firmware_header_v1_0 *mc_hdr = 56 container_of(hdr, struct mc_firmware_header_v1_0, header); 57 58 DRM_DEBUG("io_debug_size_bytes: %u\n", 59 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 62 } else { 63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 64 } 65 } 66 67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 68 { 69 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 71 72 DRM_DEBUG("SMC\n"); 73 amdgpu_ucode_print_common_hdr(hdr); 74 75 if (version_major == 1) { 76 const struct smc_firmware_header_v1_0 *smc_hdr = 77 container_of(hdr, struct smc_firmware_header_v1_0, header); 78 79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); 80 } else if (version_major == 2) { 81 const struct smc_firmware_header_v1_0 *v1_hdr = 82 container_of(hdr, struct smc_firmware_header_v1_0, header); 83 const struct smc_firmware_header_v2_0 *v2_hdr = 84 container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0); 85 86 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes)); 87 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes)); 88 } else { 89 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 90 } 91 } 92 93 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 94 { 95 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 96 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 97 98 DRM_DEBUG("GFX\n"); 99 amdgpu_ucode_print_common_hdr(hdr); 100 101 if (version_major == 1) { 102 const struct gfx_firmware_header_v1_0 *gfx_hdr = 103 container_of(hdr, struct gfx_firmware_header_v1_0, header); 104 105 DRM_DEBUG("ucode_feature_version: %u\n", 106 le32_to_cpu(gfx_hdr->ucode_feature_version)); 107 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 108 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 109 } else { 110 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 111 } 112 } 113 114 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 115 { 116 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 117 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 118 119 DRM_DEBUG("RLC\n"); 120 amdgpu_ucode_print_common_hdr(hdr); 121 122 if (version_major == 1) { 123 const struct rlc_firmware_header_v1_0 *rlc_hdr = 124 container_of(hdr, struct rlc_firmware_header_v1_0, header); 125 126 DRM_DEBUG("ucode_feature_version: %u\n", 127 le32_to_cpu(rlc_hdr->ucode_feature_version)); 128 DRM_DEBUG("save_and_restore_offset: %u\n", 129 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 130 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 131 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 132 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 133 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 134 DRM_DEBUG("master_pkt_description_offset: %u\n", 135 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 136 } else if (version_major == 2) { 137 const struct rlc_firmware_header_v2_0 *rlc_hdr = 138 container_of(hdr, struct rlc_firmware_header_v2_0, header); 139 140 DRM_DEBUG("ucode_feature_version: %u\n", 141 le32_to_cpu(rlc_hdr->ucode_feature_version)); 142 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 143 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 144 DRM_DEBUG("save_and_restore_offset: %u\n", 145 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 146 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 147 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 148 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 149 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 150 DRM_DEBUG("reg_restore_list_size: %u\n", 151 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 152 DRM_DEBUG("reg_list_format_start: %u\n", 153 le32_to_cpu(rlc_hdr->reg_list_format_start)); 154 DRM_DEBUG("reg_list_format_separate_start: %u\n", 155 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 156 DRM_DEBUG("starting_offsets_start: %u\n", 157 le32_to_cpu(rlc_hdr->starting_offsets_start)); 158 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 159 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 160 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 161 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 162 DRM_DEBUG("reg_list_size_bytes: %u\n", 163 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 164 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 165 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 166 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 167 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 168 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 169 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 170 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 171 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 172 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 173 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 174 if (version_minor == 1) { 175 const struct rlc_firmware_header_v2_1 *v2_1 = 176 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 177 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 178 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); 179 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 180 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); 181 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 182 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); 183 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 184 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); 185 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 186 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); 187 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 188 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); 189 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 190 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); 191 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 192 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); 193 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 194 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); 195 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 196 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); 197 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 198 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); 199 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 200 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); 201 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 202 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); 203 } 204 } else { 205 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 206 } 207 } 208 209 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 210 { 211 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 212 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 213 214 DRM_DEBUG("SDMA\n"); 215 amdgpu_ucode_print_common_hdr(hdr); 216 217 if (version_major == 1) { 218 const struct sdma_firmware_header_v1_0 *sdma_hdr = 219 container_of(hdr, struct sdma_firmware_header_v1_0, header); 220 221 DRM_DEBUG("ucode_feature_version: %u\n", 222 le32_to_cpu(sdma_hdr->ucode_feature_version)); 223 DRM_DEBUG("ucode_change_version: %u\n", 224 le32_to_cpu(sdma_hdr->ucode_change_version)); 225 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 226 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 227 if (version_minor >= 1) { 228 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 229 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 230 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 231 } 232 } else { 233 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 234 version_major, version_minor); 235 } 236 } 237 238 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 239 { 240 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 241 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 242 243 DRM_DEBUG("PSP\n"); 244 amdgpu_ucode_print_common_hdr(hdr); 245 246 if (version_major == 1) { 247 const struct psp_firmware_header_v1_0 *psp_hdr = 248 container_of(hdr, struct psp_firmware_header_v1_0, header); 249 250 DRM_DEBUG("ucode_feature_version: %u\n", 251 le32_to_cpu(psp_hdr->ucode_feature_version)); 252 DRM_DEBUG("sos_offset_bytes: %u\n", 253 le32_to_cpu(psp_hdr->sos_offset_bytes)); 254 DRM_DEBUG("sos_size_bytes: %u\n", 255 le32_to_cpu(psp_hdr->sos_size_bytes)); 256 if (version_minor == 1) { 257 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 258 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 259 DRM_DEBUG("toc_header_version: %u\n", 260 le32_to_cpu(psp_hdr_v1_1->toc_header_version)); 261 DRM_DEBUG("toc_offset_bytes: %u\n", 262 le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes)); 263 DRM_DEBUG("toc_size_bytes: %u\n", 264 le32_to_cpu(psp_hdr_v1_1->toc_size_bytes)); 265 DRM_DEBUG("kdb_header_version: %u\n", 266 le32_to_cpu(psp_hdr_v1_1->kdb_header_version)); 267 DRM_DEBUG("kdb_offset_bytes: %u\n", 268 le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes)); 269 DRM_DEBUG("kdb_size_bytes: %u\n", 270 le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes)); 271 } 272 if (version_minor == 2) { 273 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 274 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 275 DRM_DEBUG("kdb_header_version: %u\n", 276 le32_to_cpu(psp_hdr_v1_2->kdb_header_version)); 277 DRM_DEBUG("kdb_offset_bytes: %u\n", 278 le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes)); 279 DRM_DEBUG("kdb_size_bytes: %u\n", 280 le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes)); 281 } 282 if (version_minor == 3) { 283 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 284 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 285 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 286 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 287 DRM_DEBUG("toc_header_version: %u\n", 288 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version)); 289 DRM_DEBUG("toc_offset_bytes: %u\n", 290 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes)); 291 DRM_DEBUG("toc_size_bytes: %u\n", 292 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes)); 293 DRM_DEBUG("kdb_header_version: %u\n", 294 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version)); 295 DRM_DEBUG("kdb_offset_bytes: %u\n", 296 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes)); 297 DRM_DEBUG("kdb_size_bytes: %u\n", 298 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes)); 299 DRM_DEBUG("spl_header_version: %u\n", 300 le32_to_cpu(psp_hdr_v1_3->spl_header_version)); 301 DRM_DEBUG("spl_offset_bytes: %u\n", 302 le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes)); 303 DRM_DEBUG("spl_size_bytes: %u\n", 304 le32_to_cpu(psp_hdr_v1_3->spl_size_bytes)); 305 } 306 } else { 307 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 308 version_major, version_minor); 309 } 310 } 311 312 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 313 { 314 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 315 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 316 317 DRM_DEBUG("GPU_INFO\n"); 318 amdgpu_ucode_print_common_hdr(hdr); 319 320 if (version_major == 1) { 321 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 322 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 323 324 DRM_DEBUG("version_major: %u\n", 325 le16_to_cpu(gpu_info_hdr->version_major)); 326 DRM_DEBUG("version_minor: %u\n", 327 le16_to_cpu(gpu_info_hdr->version_minor)); 328 } else { 329 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 330 } 331 } 332 333 int amdgpu_ucode_validate(const struct firmware *fw) 334 { 335 const struct common_firmware_header *hdr = 336 (const struct common_firmware_header *)fw->data; 337 338 if (fw->size == le32_to_cpu(hdr->size_bytes)) 339 return 0; 340 341 return -EINVAL; 342 } 343 344 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 345 uint16_t hdr_major, uint16_t hdr_minor) 346 { 347 if ((hdr->common.header_version_major == hdr_major) && 348 (hdr->common.header_version_minor == hdr_minor)) 349 return false; 350 return true; 351 } 352 353 enum amdgpu_firmware_load_type 354 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 355 { 356 switch (adev->asic_type) { 357 #ifdef CONFIG_DRM_AMDGPU_SI 358 case CHIP_TAHITI: 359 case CHIP_PITCAIRN: 360 case CHIP_VERDE: 361 case CHIP_OLAND: 362 case CHIP_HAINAN: 363 return AMDGPU_FW_LOAD_DIRECT; 364 #endif 365 #ifdef CONFIG_DRM_AMDGPU_CIK 366 case CHIP_BONAIRE: 367 case CHIP_KAVERI: 368 case CHIP_KABINI: 369 case CHIP_HAWAII: 370 case CHIP_MULLINS: 371 return AMDGPU_FW_LOAD_DIRECT; 372 #endif 373 case CHIP_TOPAZ: 374 case CHIP_TONGA: 375 case CHIP_FIJI: 376 case CHIP_CARRIZO: 377 case CHIP_STONEY: 378 case CHIP_POLARIS10: 379 case CHIP_POLARIS11: 380 case CHIP_POLARIS12: 381 case CHIP_VEGAM: 382 return AMDGPU_FW_LOAD_SMU; 383 case CHIP_VEGA10: 384 case CHIP_RAVEN: 385 case CHIP_VEGA12: 386 case CHIP_VEGA20: 387 case CHIP_ARCTURUS: 388 case CHIP_RENOIR: 389 case CHIP_NAVI10: 390 case CHIP_NAVI14: 391 case CHIP_NAVI12: 392 case CHIP_SIENNA_CICHLID: 393 case CHIP_NAVY_FLOUNDER: 394 if (!load_type) 395 return AMDGPU_FW_LOAD_DIRECT; 396 else 397 return AMDGPU_FW_LOAD_PSP; 398 default: 399 DRM_ERROR("Unknown firmware load type\n"); 400 } 401 402 return AMDGPU_FW_LOAD_DIRECT; 403 } 404 405 #define FW_VERSION_ATTR(name, mode, field) \ 406 static ssize_t show_##name(struct device *dev, \ 407 struct device_attribute *attr, \ 408 char *buf) \ 409 { \ 410 struct drm_device *ddev = dev_get_drvdata(dev); \ 411 struct amdgpu_device *adev = drm_to_adev(ddev); \ 412 \ 413 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \ 414 } \ 415 static DEVICE_ATTR(name, mode, show_##name, NULL) 416 417 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 418 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 419 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 420 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 421 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 422 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 423 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 424 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 425 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 426 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 427 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 428 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 429 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version); 430 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version); 431 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version); 432 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version); 433 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 434 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 435 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 436 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 437 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 438 439 static struct attribute *fw_attrs[] = { 440 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 441 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 442 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 443 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 444 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 445 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 446 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 447 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 448 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 449 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 450 &dev_attr_dmcu_fw_version.attr, NULL 451 }; 452 453 static const struct attribute_group fw_attr_group = { 454 .name = "fw_version", 455 .attrs = fw_attrs 456 }; 457 458 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 459 { 460 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 461 } 462 463 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 464 { 465 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 466 } 467 468 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 469 struct amdgpu_firmware_info *ucode, 470 uint64_t mc_addr, void *kptr) 471 { 472 const struct common_firmware_header *header = NULL; 473 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 474 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 475 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 476 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 477 478 if (NULL == ucode->fw) 479 return 0; 480 481 ucode->mc_addr = mc_addr; 482 ucode->kaddr = kptr; 483 484 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 485 return 0; 486 487 header = (const struct common_firmware_header *)ucode->fw->data; 488 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 489 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 490 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 491 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 492 493 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 494 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && 495 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && 496 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && 497 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && 498 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES && 499 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA && 500 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && 501 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && 502 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && 503 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM && 504 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM && 505 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && 506 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV && 507 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) { 508 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 509 510 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 511 le32_to_cpu(header->ucode_array_offset_bytes)), 512 ucode->ucode_size); 513 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || 514 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { 515 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 516 le32_to_cpu(cp_hdr->jt_size) * 4; 517 518 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 519 le32_to_cpu(header->ucode_array_offset_bytes)), 520 ucode->ucode_size); 521 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 522 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { 523 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 524 525 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 526 le32_to_cpu(header->ucode_array_offset_bytes) + 527 le32_to_cpu(cp_hdr->jt_offset) * 4), 528 ucode->ucode_size); 529 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { 530 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 531 le32_to_cpu(dmcu_hdr->intv_size_bytes); 532 533 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 534 le32_to_cpu(header->ucode_array_offset_bytes)), 535 ucode->ucode_size); 536 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { 537 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 538 539 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 540 le32_to_cpu(header->ucode_array_offset_bytes) + 541 le32_to_cpu(dmcu_hdr->intv_offset_bytes)), 542 ucode->ucode_size); 543 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) { 544 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 545 memcpy(ucode->kaddr, 546 (void *)((uint8_t *)ucode->fw->data + 547 le32_to_cpu(header->ucode_array_offset_bytes)), 548 ucode->ucode_size); 549 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { 550 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 551 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, 552 ucode->ucode_size); 553 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) { 554 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 555 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, 556 ucode->ucode_size); 557 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 558 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 559 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, 560 ucode->ucode_size); 561 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) { 562 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 563 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode, 564 ucode->ucode_size); 565 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) { 566 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 567 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode, 568 ucode->ucode_size); 569 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) { 570 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 571 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data + 572 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)), 573 ucode->ucode_size); 574 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) { 575 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 576 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data + 577 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)), 578 ucode->ucode_size); 579 } 580 581 return 0; 582 } 583 584 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 585 uint64_t mc_addr, void *kptr) 586 { 587 const struct gfx_firmware_header_v1_0 *header = NULL; 588 const struct common_firmware_header *comm_hdr = NULL; 589 uint8_t* src_addr = NULL; 590 uint8_t* dst_addr = NULL; 591 592 if (NULL == ucode->fw) 593 return 0; 594 595 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 596 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 597 dst_addr = ucode->kaddr + 598 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 599 PAGE_SIZE); 600 src_addr = (uint8_t *)ucode->fw->data + 601 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 602 (le32_to_cpu(header->jt_offset) * 4); 603 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 604 605 return 0; 606 } 607 608 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 609 { 610 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 611 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 612 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 613 &adev->firmware.fw_buf, 614 &adev->firmware.fw_buf_mc, 615 &adev->firmware.fw_buf_ptr); 616 if (!adev->firmware.fw_buf) { 617 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 618 return -ENOMEM; 619 } else if (amdgpu_sriov_vf(adev)) { 620 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 621 } 622 } 623 return 0; 624 } 625 626 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 627 { 628 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) 629 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 630 &adev->firmware.fw_buf_mc, 631 &adev->firmware.fw_buf_ptr); 632 } 633 634 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 635 { 636 uint64_t fw_offset = 0; 637 int i; 638 struct amdgpu_firmware_info *ucode = NULL; 639 640 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 641 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 642 return 0; 643 /* 644 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 645 * ucode info here 646 */ 647 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 648 if (amdgpu_sriov_vf(adev)) 649 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 650 else 651 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 652 } else { 653 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 654 } 655 656 for (i = 0; i < adev->firmware.max_ucodes; i++) { 657 ucode = &adev->firmware.ucode[i]; 658 if (ucode->fw) { 659 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 660 adev->firmware.fw_buf_ptr + fw_offset); 661 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 662 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 663 const struct gfx_firmware_header_v1_0 *cp_hdr; 664 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 665 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 666 adev->firmware.fw_buf_ptr + fw_offset); 667 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 668 } 669 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 670 } 671 } 672 return 0; 673 } 674