1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include "amdgpu.h" 30 31 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 32 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 33 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 34 35 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 36 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 37 38 #define AMDGPU_POISON 0xd0bed0be 39 40 struct amdgpu_vram_reservation { 41 struct list_head node; 42 struct drm_mm_node mm_node; 43 }; 44 45 struct amdgpu_vram_mgr { 46 struct ttm_resource_manager manager; 47 struct drm_mm mm; 48 spinlock_t lock; 49 struct list_head reservations_pending; 50 struct list_head reserved_pages; 51 atomic64_t usage; 52 atomic64_t vis_usage; 53 }; 54 55 struct amdgpu_gtt_mgr { 56 struct ttm_resource_manager manager; 57 struct drm_mm mm; 58 spinlock_t lock; 59 atomic64_t available; 60 }; 61 62 struct amdgpu_mman { 63 struct ttm_device bdev; 64 bool initialized; 65 void __iomem *aper_base_kaddr; 66 67 /* buffer handling */ 68 const struct amdgpu_buffer_funcs *buffer_funcs; 69 struct amdgpu_ring *buffer_funcs_ring; 70 bool buffer_funcs_enabled; 71 72 struct mutex gtt_window_lock; 73 /* Scheduler entity for buffer moves */ 74 struct drm_sched_entity entity; 75 76 struct amdgpu_vram_mgr vram_mgr; 77 struct amdgpu_gtt_mgr gtt_mgr; 78 79 uint64_t stolen_vga_size; 80 struct amdgpu_bo *stolen_vga_memory; 81 uint64_t stolen_extended_size; 82 struct amdgpu_bo *stolen_extended_memory; 83 bool keep_stolen_vga_memory; 84 85 /* discovery */ 86 uint8_t *discovery_bin; 87 uint32_t discovery_tmr_size; 88 struct amdgpu_bo *discovery_memory; 89 90 /* firmware VRAM reservation */ 91 u64 fw_vram_usage_start_offset; 92 u64 fw_vram_usage_size; 93 struct amdgpu_bo *fw_vram_usage_reserved_bo; 94 void *fw_vram_usage_va; 95 }; 96 97 struct amdgpu_copy_mem { 98 struct ttm_buffer_object *bo; 99 struct ttm_resource *mem; 100 unsigned long offset; 101 }; 102 103 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 104 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 105 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 106 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 107 108 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 109 uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man); 110 int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man); 111 112 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 113 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 114 struct ttm_resource *mem, 115 u64 offset, u64 size, 116 struct device *dev, 117 enum dma_data_direction dir, 118 struct sg_table **sgt); 119 void amdgpu_vram_mgr_free_sgt(struct device *dev, 120 enum dma_data_direction dir, 121 struct sg_table *sgt); 122 uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man); 123 uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_resource_manager *man); 124 int amdgpu_vram_mgr_reserve_range(struct ttm_resource_manager *man, 125 uint64_t start, uint64_t size); 126 int amdgpu_vram_mgr_query_page_status(struct ttm_resource_manager *man, 127 uint64_t start); 128 129 int amdgpu_ttm_init(struct amdgpu_device *adev); 130 void amdgpu_ttm_fini(struct amdgpu_device *adev); 131 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 132 bool enable); 133 134 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 135 uint64_t dst_offset, uint32_t byte_count, 136 struct dma_resv *resv, 137 struct dma_fence **fence, bool direct_submit, 138 bool vm_needs_flush, bool tmz); 139 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 140 const struct amdgpu_copy_mem *src, 141 const struct amdgpu_copy_mem *dst, 142 uint64_t size, bool tmz, 143 struct dma_resv *resv, 144 struct dma_fence **f); 145 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 146 uint32_t src_data, 147 struct dma_resv *resv, 148 struct dma_fence **fence); 149 150 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 151 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 152 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 153 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 154 155 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 156 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); 157 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm); 158 #else 159 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 160 struct page **pages) 161 { 162 return -EPERM; 163 } 164 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 165 { 166 return false; 167 } 168 #endif 169 170 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); 171 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 172 uint64_t addr, uint32_t flags); 173 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 174 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 175 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 176 unsigned long end); 177 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 178 int *last_invalidated); 179 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 180 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 181 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 182 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 183 struct ttm_resource *mem); 184 185 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 186 187 #endif 188