1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_TTM_H__
25 #define __AMDGPU_TTM_H__
26 
27 #include <linux/dma-direction.h>
28 #include <drm/gpu_scheduler.h>
29 #include "amdgpu.h"
30 
31 #define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
32 #define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)
33 #define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)
34 
35 #define AMDGPU_PL_FLAG_GDS		(TTM_PL_FLAG_PRIV << 0)
36 #define AMDGPU_PL_FLAG_GWS		(TTM_PL_FLAG_PRIV << 1)
37 #define AMDGPU_PL_FLAG_OA		(TTM_PL_FLAG_PRIV << 2)
38 
39 #define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
40 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2
41 
42 #define AMDGPU_POISON	0xd0bed0be
43 
44 struct amdgpu_mman {
45 	struct ttm_bo_device		bdev;
46 	bool				mem_global_referenced;
47 	bool				initialized;
48 	void __iomem			*aper_base_kaddr;
49 
50 #if defined(CONFIG_DEBUG_FS)
51 	struct dentry			*debugfs_entries[8];
52 #endif
53 
54 	/* buffer handling */
55 	const struct amdgpu_buffer_funcs	*buffer_funcs;
56 	struct amdgpu_ring			*buffer_funcs_ring;
57 	bool					buffer_funcs_enabled;
58 
59 	struct mutex				gtt_window_lock;
60 	/* Scheduler entity for buffer moves */
61 	struct drm_sched_entity			entity;
62 };
63 
64 struct amdgpu_copy_mem {
65 	struct ttm_buffer_object	*bo;
66 	struct ttm_mem_reg		*mem;
67 	unsigned long			offset;
68 };
69 
70 extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
71 extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
72 
73 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
74 uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
75 int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
76 
77 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
78 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
79 			      struct ttm_mem_reg *mem,
80 			      struct device *dev,
81 			      enum dma_data_direction dir,
82 			      struct sg_table **sgt);
83 void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev,
84 			      struct device *dev,
85 			      enum dma_data_direction dir,
86 			      struct sg_table *sgt);
87 uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
88 uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
89 
90 int amdgpu_ttm_init(struct amdgpu_device *adev);
91 void amdgpu_ttm_late_init(struct amdgpu_device *adev);
92 void amdgpu_ttm_fini(struct amdgpu_device *adev);
93 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
94 					bool enable);
95 
96 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
97 		       uint64_t dst_offset, uint32_t byte_count,
98 		       struct dma_resv *resv,
99 		       struct dma_fence **fence, bool direct_submit,
100 		       bool vm_needs_flush, bool tmz);
101 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
102 			       const struct amdgpu_copy_mem *src,
103 			       const struct amdgpu_copy_mem *dst,
104 			       uint64_t size, bool tmz,
105 			       struct dma_resv *resv,
106 			       struct dma_fence **f);
107 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
108 			uint32_t src_data,
109 			struct dma_resv *resv,
110 			struct dma_fence **fence);
111 
112 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
113 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
114 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
115 
116 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
117 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
118 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
119 #else
120 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
121 					       struct page **pages)
122 {
123 	return -EPERM;
124 }
125 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
126 {
127 	return false;
128 }
129 #endif
130 
131 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
132 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
133 				     uint32_t flags);
134 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
135 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
136 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
137 				  unsigned long end);
138 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
139 				       int *last_invalidated);
140 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
141 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
142 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
143 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
144 				 struct ttm_mem_reg *mem);
145 
146 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
147 
148 #endif
149