1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include "amdgpu.h" 30 31 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 32 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 33 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 34 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 35 36 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 37 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 38 39 #define AMDGPU_POISON 0xd0bed0be 40 41 struct amdgpu_vram_mgr { 42 struct ttm_resource_manager manager; 43 struct drm_mm mm; 44 spinlock_t lock; 45 struct list_head reservations_pending; 46 struct list_head reserved_pages; 47 atomic64_t usage; 48 atomic64_t vis_usage; 49 }; 50 51 struct amdgpu_gtt_mgr { 52 struct ttm_resource_manager manager; 53 struct drm_mm mm; 54 spinlock_t lock; 55 atomic64_t used; 56 }; 57 58 struct amdgpu_preempt_mgr { 59 struct ttm_resource_manager manager; 60 atomic64_t used; 61 }; 62 63 struct amdgpu_mman { 64 struct ttm_device bdev; 65 bool initialized; 66 void __iomem *aper_base_kaddr; 67 68 /* buffer handling */ 69 const struct amdgpu_buffer_funcs *buffer_funcs; 70 struct amdgpu_ring *buffer_funcs_ring; 71 bool buffer_funcs_enabled; 72 73 struct mutex gtt_window_lock; 74 /* Scheduler entity for buffer moves */ 75 struct drm_sched_entity entity; 76 77 struct amdgpu_vram_mgr vram_mgr; 78 struct amdgpu_gtt_mgr gtt_mgr; 79 struct amdgpu_preempt_mgr preempt_mgr; 80 81 uint64_t stolen_vga_size; 82 struct amdgpu_bo *stolen_vga_memory; 83 uint64_t stolen_extended_size; 84 struct amdgpu_bo *stolen_extended_memory; 85 bool keep_stolen_vga_memory; 86 87 struct amdgpu_bo *stolen_reserved_memory; 88 uint64_t stolen_reserved_offset; 89 uint64_t stolen_reserved_size; 90 91 /* discovery */ 92 uint8_t *discovery_bin; 93 uint32_t discovery_tmr_size; 94 struct amdgpu_bo *discovery_memory; 95 96 /* firmware VRAM reservation */ 97 u64 fw_vram_usage_start_offset; 98 u64 fw_vram_usage_size; 99 struct amdgpu_bo *fw_vram_usage_reserved_bo; 100 void *fw_vram_usage_va; 101 102 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 103 struct amdgpu_bo *sdma_access_bo; 104 void *sdma_access_ptr; 105 }; 106 107 struct amdgpu_copy_mem { 108 struct ttm_buffer_object *bo; 109 struct ttm_resource *mem; 110 unsigned long offset; 111 }; 112 113 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 114 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 115 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 116 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 117 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 118 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 119 120 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 121 uint64_t amdgpu_gtt_mgr_usage(struct amdgpu_gtt_mgr *mgr); 122 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 123 124 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 125 126 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 127 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 128 struct ttm_resource *mem, 129 u64 offset, u64 size, 130 struct device *dev, 131 enum dma_data_direction dir, 132 struct sg_table **sgt); 133 void amdgpu_vram_mgr_free_sgt(struct device *dev, 134 enum dma_data_direction dir, 135 struct sg_table *sgt); 136 uint64_t amdgpu_vram_mgr_usage(struct amdgpu_vram_mgr *mgr); 137 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 138 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 139 uint64_t start, uint64_t size); 140 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 141 uint64_t start); 142 143 int amdgpu_ttm_init(struct amdgpu_device *adev); 144 void amdgpu_ttm_fini(struct amdgpu_device *adev); 145 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 146 bool enable); 147 148 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 149 uint64_t dst_offset, uint32_t byte_count, 150 struct dma_resv *resv, 151 struct dma_fence **fence, bool direct_submit, 152 bool vm_needs_flush, bool tmz); 153 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 154 const struct amdgpu_copy_mem *src, 155 const struct amdgpu_copy_mem *dst, 156 uint64_t size, bool tmz, 157 struct dma_resv *resv, 158 struct dma_fence **f); 159 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 160 uint32_t src_data, 161 struct dma_resv *resv, 162 struct dma_fence **fence); 163 164 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 165 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 166 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 167 168 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 169 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); 170 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm); 171 #else 172 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 173 struct page **pages) 174 { 175 return -EPERM; 176 } 177 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 178 { 179 return false; 180 } 181 #endif 182 183 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); 184 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 185 uint64_t *user_addr); 186 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 187 uint64_t addr, uint32_t flags); 188 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 189 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 190 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 191 unsigned long end, unsigned long *userptr); 192 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 193 int *last_invalidated); 194 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 195 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 196 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 197 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 198 struct ttm_resource *mem); 199 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 200 201 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 202 203 #endif 204