1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 52 #include <drm/drm_debugfs.h> 53 #include <drm/amdgpu_drm.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "amdgpu_atomfirmware.h" 62 #include "bif/bif_4_1_d.h" 63 64 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 65 66 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 67 unsigned int type, 68 uint64_t size) 69 { 70 return ttm_range_man_init(&adev->mman.bdev, type, 71 TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED, 72 false, size >> PAGE_SHIFT); 73 } 74 75 /** 76 * amdgpu_evict_flags - Compute placement flags 77 * 78 * @bo: The buffer object to evict 79 * @placement: Possible destination(s) for evicted BO 80 * 81 * Fill in placement data when ttm_bo_evict() is called 82 */ 83 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 84 struct ttm_placement *placement) 85 { 86 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 87 struct amdgpu_bo *abo; 88 static const struct ttm_place placements = { 89 .fpfn = 0, 90 .lpfn = 0, 91 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 92 }; 93 94 /* Don't handle scatter gather BOs */ 95 if (bo->type == ttm_bo_type_sg) { 96 placement->num_placement = 0; 97 placement->num_busy_placement = 0; 98 return; 99 } 100 101 /* Object isn't an AMDGPU object so ignore */ 102 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 103 placement->placement = &placements; 104 placement->busy_placement = &placements; 105 placement->num_placement = 1; 106 placement->num_busy_placement = 1; 107 return; 108 } 109 110 abo = ttm_to_amdgpu_bo(bo); 111 switch (bo->mem.mem_type) { 112 case AMDGPU_PL_GDS: 113 case AMDGPU_PL_GWS: 114 case AMDGPU_PL_OA: 115 placement->num_placement = 0; 116 placement->num_busy_placement = 0; 117 return; 118 119 case TTM_PL_VRAM: 120 if (!adev->mman.buffer_funcs_enabled) { 121 /* Move to system memory */ 122 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 123 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 124 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 125 amdgpu_bo_in_cpu_visible_vram(abo)) { 126 127 /* Try evicting to the CPU inaccessible part of VRAM 128 * first, but only set GTT as busy placement, so this 129 * BO will be evicted to GTT rather than causing other 130 * BOs to be evicted from VRAM 131 */ 132 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 133 AMDGPU_GEM_DOMAIN_GTT); 134 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 abo->placements[0].lpfn = 0; 136 abo->placement.busy_placement = &abo->placements[1]; 137 abo->placement.num_busy_placement = 1; 138 } else { 139 /* Move to GTT memory */ 140 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 141 } 142 break; 143 case TTM_PL_TT: 144 default: 145 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 146 break; 147 } 148 *placement = abo->placement; 149 } 150 151 /** 152 * amdgpu_verify_access - Verify access for a mmap call 153 * 154 * @bo: The buffer object to map 155 * @filp: The file pointer from the process performing the mmap 156 * 157 * This is called by ttm_bo_mmap() to verify whether a process 158 * has the right to mmap a BO to their process space. 159 */ 160 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 161 { 162 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 163 164 /* 165 * Don't verify access for KFD BOs. They don't have a GEM 166 * object associated with them. 167 */ 168 if (abo->kfd_bo) 169 return 0; 170 171 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 172 return -EPERM; 173 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 174 filp->private_data); 175 } 176 177 /** 178 * amdgpu_move_null - Register memory for a buffer object 179 * 180 * @bo: The bo to assign the memory to 181 * @new_mem: The memory to be assigned. 182 * 183 * Assign the memory from new_mem to the memory of the buffer object bo. 184 */ 185 static void amdgpu_move_null(struct ttm_buffer_object *bo, 186 struct ttm_resource *new_mem) 187 { 188 struct ttm_resource *old_mem = &bo->mem; 189 190 BUG_ON(old_mem->mm_node != NULL); 191 *old_mem = *new_mem; 192 new_mem->mm_node = NULL; 193 } 194 195 /** 196 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. 197 * 198 * @bo: The bo to assign the memory to. 199 * @mm_node: Memory manager node for drm allocator. 200 * @mem: The region where the bo resides. 201 * 202 */ 203 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 204 struct drm_mm_node *mm_node, 205 struct ttm_resource *mem) 206 { 207 uint64_t addr = 0; 208 209 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { 210 addr = mm_node->start << PAGE_SHIFT; 211 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev), 212 mem->mem_type); 213 } 214 return addr; 215 } 216 217 /** 218 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to 219 * @offset. It also modifies the offset to be within the drm_mm_node returned 220 * 221 * @mem: The region where the bo resides. 222 * @offset: The offset that drm_mm_node is used for finding. 223 * 224 */ 225 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem, 226 uint64_t *offset) 227 { 228 struct drm_mm_node *mm_node = mem->mm_node; 229 230 while (*offset >= (mm_node->size << PAGE_SHIFT)) { 231 *offset -= (mm_node->size << PAGE_SHIFT); 232 ++mm_node; 233 } 234 return mm_node; 235 } 236 237 /** 238 * amdgpu_ttm_map_buffer - Map memory into the GART windows 239 * @bo: buffer object to map 240 * @mem: memory object to map 241 * @mm_node: drm_mm node object to map 242 * @num_pages: number of pages to map 243 * @offset: offset into @mm_node where to start 244 * @window: which GART window to use 245 * @ring: DMA ring to use for the copy 246 * @tmz: if we should setup a TMZ enabled mapping 247 * @addr: resulting address inside the MC address space 248 * 249 * Setup one of the GART windows to access a specific piece of memory or return 250 * the physical address for local memory. 251 */ 252 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 253 struct ttm_resource *mem, 254 struct drm_mm_node *mm_node, 255 unsigned num_pages, uint64_t offset, 256 unsigned window, struct amdgpu_ring *ring, 257 bool tmz, uint64_t *addr) 258 { 259 struct amdgpu_device *adev = ring->adev; 260 struct amdgpu_job *job; 261 unsigned num_dw, num_bytes; 262 struct dma_fence *fence; 263 uint64_t src_addr, dst_addr; 264 void *cpu_addr; 265 uint64_t flags; 266 unsigned int i; 267 int r; 268 269 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 270 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 271 272 /* Map only what can't be accessed directly */ 273 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 274 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; 275 return 0; 276 } 277 278 *addr = adev->gmc.gart_start; 279 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 280 AMDGPU_GPU_PAGE_SIZE; 281 *addr += offset & ~PAGE_MASK; 282 283 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 284 num_bytes = num_pages * 8; 285 286 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 287 AMDGPU_IB_POOL_DELAYED, &job); 288 if (r) 289 return r; 290 291 src_addr = num_dw * 4; 292 src_addr += job->ibs[0].gpu_addr; 293 294 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 295 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 296 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 297 dst_addr, num_bytes, false); 298 299 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 300 WARN_ON(job->ibs[0].length_dw > num_dw); 301 302 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 303 if (tmz) 304 flags |= AMDGPU_PTE_TMZ; 305 306 cpu_addr = &job->ibs[0].ptr[num_dw]; 307 308 if (mem->mem_type == TTM_PL_TT) { 309 struct ttm_dma_tt *dma; 310 dma_addr_t *dma_address; 311 312 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm); 313 dma_address = &dma->dma_address[offset >> PAGE_SHIFT]; 314 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, 315 cpu_addr); 316 if (r) 317 goto error_free; 318 } else { 319 dma_addr_t dma_address; 320 321 dma_address = (mm_node->start << PAGE_SHIFT) + offset; 322 dma_address += adev->vm_manager.vram_base_offset; 323 324 for (i = 0; i < num_pages; ++i) { 325 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 326 &dma_address, flags, cpu_addr); 327 if (r) 328 goto error_free; 329 330 dma_address += PAGE_SIZE; 331 } 332 } 333 334 r = amdgpu_job_submit(job, &adev->mman.entity, 335 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 336 if (r) 337 goto error_free; 338 339 dma_fence_put(fence); 340 341 return r; 342 343 error_free: 344 amdgpu_job_free(job); 345 return r; 346 } 347 348 /** 349 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 350 * @adev: amdgpu device 351 * @src: buffer/address where to read from 352 * @dst: buffer/address where to write to 353 * @size: number of bytes to copy 354 * @tmz: if a secure copy should be used 355 * @resv: resv object to sync to 356 * @f: Returns the last fence if multiple jobs are submitted. 357 * 358 * The function copies @size bytes from {src->mem + src->offset} to 359 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 360 * move and different for a BO to BO copy. 361 * 362 */ 363 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 364 const struct amdgpu_copy_mem *src, 365 const struct amdgpu_copy_mem *dst, 366 uint64_t size, bool tmz, 367 struct dma_resv *resv, 368 struct dma_fence **f) 369 { 370 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 371 AMDGPU_GPU_PAGE_SIZE); 372 373 uint64_t src_node_size, dst_node_size, src_offset, dst_offset; 374 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 375 struct drm_mm_node *src_mm, *dst_mm; 376 struct dma_fence *fence = NULL; 377 int r = 0; 378 379 if (!adev->mman.buffer_funcs_enabled) { 380 DRM_ERROR("Trying to move memory with ring turned off.\n"); 381 return -EINVAL; 382 } 383 384 src_offset = src->offset; 385 if (src->mem->mm_node) { 386 src_mm = amdgpu_find_mm_node(src->mem, &src_offset); 387 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; 388 } else { 389 src_mm = NULL; 390 src_node_size = ULLONG_MAX; 391 } 392 393 dst_offset = dst->offset; 394 if (dst->mem->mm_node) { 395 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); 396 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; 397 } else { 398 dst_mm = NULL; 399 dst_node_size = ULLONG_MAX; 400 } 401 402 mutex_lock(&adev->mman.gtt_window_lock); 403 404 while (size) { 405 uint32_t src_page_offset = src_offset & ~PAGE_MASK; 406 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; 407 struct dma_fence *next; 408 uint32_t cur_size; 409 uint64_t from, to; 410 411 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 412 * begins at an offset, then adjust the size accordingly 413 */ 414 cur_size = max(src_page_offset, dst_page_offset); 415 cur_size = min(min3(src_node_size, dst_node_size, size), 416 (uint64_t)(GTT_MAX_BYTES - cur_size)); 417 418 /* Map src to window 0 and dst to window 1. */ 419 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, 420 PFN_UP(cur_size + src_page_offset), 421 src_offset, 0, ring, tmz, &from); 422 if (r) 423 goto error; 424 425 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, 426 PFN_UP(cur_size + dst_page_offset), 427 dst_offset, 1, ring, tmz, &to); 428 if (r) 429 goto error; 430 431 r = amdgpu_copy_buffer(ring, from, to, cur_size, 432 resv, &next, false, true, tmz); 433 if (r) 434 goto error; 435 436 dma_fence_put(fence); 437 fence = next; 438 439 size -= cur_size; 440 if (!size) 441 break; 442 443 src_node_size -= cur_size; 444 if (!src_node_size) { 445 ++src_mm; 446 src_node_size = src_mm->size << PAGE_SHIFT; 447 src_offset = 0; 448 } else { 449 src_offset += cur_size; 450 } 451 452 dst_node_size -= cur_size; 453 if (!dst_node_size) { 454 ++dst_mm; 455 dst_node_size = dst_mm->size << PAGE_SHIFT; 456 dst_offset = 0; 457 } else { 458 dst_offset += cur_size; 459 } 460 } 461 error: 462 mutex_unlock(&adev->mman.gtt_window_lock); 463 if (f) 464 *f = dma_fence_get(fence); 465 dma_fence_put(fence); 466 return r; 467 } 468 469 /** 470 * amdgpu_move_blit - Copy an entire buffer to another buffer 471 * 472 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 473 * help move buffers to and from VRAM. 474 */ 475 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 476 bool evict, 477 struct ttm_resource *new_mem, 478 struct ttm_resource *old_mem) 479 { 480 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 481 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 482 struct amdgpu_copy_mem src, dst; 483 struct dma_fence *fence = NULL; 484 int r; 485 486 src.bo = bo; 487 dst.bo = bo; 488 src.mem = old_mem; 489 dst.mem = new_mem; 490 src.offset = 0; 491 dst.offset = 0; 492 493 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 494 new_mem->num_pages << PAGE_SHIFT, 495 amdgpu_bo_encrypted(abo), 496 bo->base.resv, &fence); 497 if (r) 498 goto error; 499 500 /* clear the space being freed */ 501 if (old_mem->mem_type == TTM_PL_VRAM && 502 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 503 struct dma_fence *wipe_fence = NULL; 504 505 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 506 NULL, &wipe_fence); 507 if (r) { 508 goto error; 509 } else if (wipe_fence) { 510 dma_fence_put(fence); 511 fence = wipe_fence; 512 } 513 } 514 515 /* Always block for VM page tables before committing the new location */ 516 if (bo->type == ttm_bo_type_kernel) 517 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem); 518 else 519 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 520 dma_fence_put(fence); 521 return r; 522 523 error: 524 if (fence) 525 dma_fence_wait(fence, false); 526 dma_fence_put(fence); 527 return r; 528 } 529 530 /** 531 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer 532 * 533 * Called by amdgpu_bo_move(). 534 */ 535 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 536 struct ttm_operation_ctx *ctx, 537 struct ttm_resource *new_mem) 538 { 539 struct ttm_resource *old_mem = &bo->mem; 540 struct ttm_resource tmp_mem; 541 struct ttm_place placements; 542 struct ttm_placement placement; 543 int r; 544 545 /* create space/pages for new_mem in GTT space */ 546 tmp_mem = *new_mem; 547 tmp_mem.mm_node = NULL; 548 placement.num_placement = 1; 549 placement.placement = &placements; 550 placement.num_busy_placement = 1; 551 placement.busy_placement = &placements; 552 placements.fpfn = 0; 553 placements.lpfn = 0; 554 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 555 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 556 if (unlikely(r)) { 557 pr_err("Failed to find GTT space for blit from VRAM\n"); 558 return r; 559 } 560 561 /* set caching flags */ 562 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 563 if (unlikely(r)) { 564 goto out_cleanup; 565 } 566 567 /* Bind the memory to the GTT space */ 568 r = ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem, ctx); 569 if (unlikely(r)) { 570 goto out_cleanup; 571 } 572 573 /* blit VRAM to GTT */ 574 r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem); 575 if (unlikely(r)) { 576 goto out_cleanup; 577 } 578 579 /* move BO (in tmp_mem) to new_mem */ 580 r = ttm_bo_move_ttm(bo, ctx, new_mem); 581 out_cleanup: 582 ttm_resource_free(bo, &tmp_mem); 583 return r; 584 } 585 586 /** 587 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM 588 * 589 * Called by amdgpu_bo_move(). 590 */ 591 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 592 struct ttm_operation_ctx *ctx, 593 struct ttm_resource *new_mem) 594 { 595 struct ttm_resource *old_mem = &bo->mem; 596 struct ttm_resource tmp_mem; 597 struct ttm_placement placement; 598 struct ttm_place placements; 599 int r; 600 601 /* make space in GTT for old_mem buffer */ 602 tmp_mem = *new_mem; 603 tmp_mem.mm_node = NULL; 604 placement.num_placement = 1; 605 placement.placement = &placements; 606 placement.num_busy_placement = 1; 607 placement.busy_placement = &placements; 608 placements.fpfn = 0; 609 placements.lpfn = 0; 610 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 611 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 612 if (unlikely(r)) { 613 pr_err("Failed to find GTT space for blit to VRAM\n"); 614 return r; 615 } 616 617 /* move/bind old memory to GTT space */ 618 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); 619 if (unlikely(r)) { 620 goto out_cleanup; 621 } 622 623 /* copy to VRAM */ 624 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 625 if (unlikely(r)) { 626 goto out_cleanup; 627 } 628 out_cleanup: 629 ttm_resource_free(bo, &tmp_mem); 630 return r; 631 } 632 633 /** 634 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 635 * 636 * Called by amdgpu_bo_move() 637 */ 638 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 639 struct ttm_resource *mem) 640 { 641 struct drm_mm_node *nodes = mem->mm_node; 642 643 if (mem->mem_type == TTM_PL_SYSTEM || 644 mem->mem_type == TTM_PL_TT) 645 return true; 646 if (mem->mem_type != TTM_PL_VRAM) 647 return false; 648 649 /* ttm_resource_ioremap only supports contiguous memory */ 650 if (nodes->size != mem->num_pages) 651 return false; 652 653 return ((nodes->start + nodes->size) << PAGE_SHIFT) 654 <= adev->gmc.visible_vram_size; 655 } 656 657 /** 658 * amdgpu_bo_move - Move a buffer object to a new memory location 659 * 660 * Called by ttm_bo_handle_move_mem() 661 */ 662 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 663 struct ttm_operation_ctx *ctx, 664 struct ttm_resource *new_mem) 665 { 666 struct amdgpu_device *adev; 667 struct amdgpu_bo *abo; 668 struct ttm_resource *old_mem = &bo->mem; 669 int r; 670 671 /* Can't move a pinned BO */ 672 abo = ttm_to_amdgpu_bo(bo); 673 if (WARN_ON_ONCE(abo->pin_count > 0)) 674 return -EINVAL; 675 676 adev = amdgpu_ttm_adev(bo->bdev); 677 678 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 679 amdgpu_move_null(bo, new_mem); 680 return 0; 681 } 682 if ((old_mem->mem_type == TTM_PL_TT && 683 new_mem->mem_type == TTM_PL_SYSTEM) || 684 (old_mem->mem_type == TTM_PL_SYSTEM && 685 new_mem->mem_type == TTM_PL_TT)) { 686 /* bind is enough */ 687 amdgpu_move_null(bo, new_mem); 688 return 0; 689 } 690 if (old_mem->mem_type == AMDGPU_PL_GDS || 691 old_mem->mem_type == AMDGPU_PL_GWS || 692 old_mem->mem_type == AMDGPU_PL_OA || 693 new_mem->mem_type == AMDGPU_PL_GDS || 694 new_mem->mem_type == AMDGPU_PL_GWS || 695 new_mem->mem_type == AMDGPU_PL_OA) { 696 /* Nothing to save here */ 697 amdgpu_move_null(bo, new_mem); 698 return 0; 699 } 700 701 if (!adev->mman.buffer_funcs_enabled) { 702 r = -ENODEV; 703 goto memcpy; 704 } 705 706 if (old_mem->mem_type == TTM_PL_VRAM && 707 new_mem->mem_type == TTM_PL_SYSTEM) { 708 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); 709 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 710 new_mem->mem_type == TTM_PL_VRAM) { 711 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); 712 } else { 713 r = amdgpu_move_blit(bo, evict, 714 new_mem, old_mem); 715 } 716 717 if (r) { 718 memcpy: 719 /* Check that all memory is CPU accessible */ 720 if (!amdgpu_mem_visible(adev, old_mem) || 721 !amdgpu_mem_visible(adev, new_mem)) { 722 pr_err("Move buffer fallback to memcpy unavailable\n"); 723 return r; 724 } 725 726 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 727 if (r) 728 return r; 729 } 730 731 if (bo->type == ttm_bo_type_device && 732 new_mem->mem_type == TTM_PL_VRAM && 733 old_mem->mem_type != TTM_PL_VRAM) { 734 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 735 * accesses the BO after it's moved. 736 */ 737 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 738 } 739 740 /* update statistics */ 741 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 742 return 0; 743 } 744 745 /** 746 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 747 * 748 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 749 */ 750 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) 751 { 752 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 753 struct drm_mm_node *mm_node = mem->mm_node; 754 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 755 756 switch (mem->mem_type) { 757 case TTM_PL_SYSTEM: 758 /* system memory */ 759 return 0; 760 case TTM_PL_TT: 761 break; 762 case TTM_PL_VRAM: 763 mem->bus.offset = mem->start << PAGE_SHIFT; 764 /* check if it's visible */ 765 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 766 return -EINVAL; 767 /* Only physically contiguous buffers apply. In a contiguous 768 * buffer, size of the first mm_node would match the number of 769 * pages in ttm_resource. 770 */ 771 if (adev->mman.aper_base_kaddr && 772 (mm_node->size == mem->num_pages)) 773 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 774 mem->bus.offset; 775 776 mem->bus.offset += adev->gmc.aper_base; 777 mem->bus.is_iomem = true; 778 break; 779 default: 780 return -EINVAL; 781 } 782 return 0; 783 } 784 785 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 786 unsigned long page_offset) 787 { 788 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 789 uint64_t offset = (page_offset << PAGE_SHIFT); 790 struct drm_mm_node *mm; 791 792 mm = amdgpu_find_mm_node(&bo->mem, &offset); 793 offset += adev->gmc.aper_base; 794 return mm->start + (offset >> PAGE_SHIFT); 795 } 796 797 /** 798 * amdgpu_ttm_domain_start - Returns GPU start address 799 * @adev: amdgpu device object 800 * @type: type of the memory 801 * 802 * Returns: 803 * GPU start address of a memory domain 804 */ 805 806 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 807 { 808 switch (type) { 809 case TTM_PL_TT: 810 return adev->gmc.gart_start; 811 case TTM_PL_VRAM: 812 return adev->gmc.vram_start; 813 } 814 815 return 0; 816 } 817 818 /* 819 * TTM backend functions. 820 */ 821 struct amdgpu_ttm_tt { 822 struct ttm_dma_tt ttm; 823 struct drm_gem_object *gobj; 824 u64 offset; 825 uint64_t userptr; 826 struct task_struct *usertask; 827 uint32_t userflags; 828 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 829 struct hmm_range *range; 830 #endif 831 }; 832 833 #ifdef CONFIG_DRM_AMDGPU_USERPTR 834 /** 835 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 836 * memory and start HMM tracking CPU page table update 837 * 838 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 839 * once afterwards to stop HMM tracking 840 */ 841 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 842 { 843 struct ttm_tt *ttm = bo->tbo.ttm; 844 struct amdgpu_ttm_tt *gtt = (void *)ttm; 845 unsigned long start = gtt->userptr; 846 struct vm_area_struct *vma; 847 struct hmm_range *range; 848 unsigned long timeout; 849 struct mm_struct *mm; 850 unsigned long i; 851 int r = 0; 852 853 mm = bo->notifier.mm; 854 if (unlikely(!mm)) { 855 DRM_DEBUG_DRIVER("BO is not registered?\n"); 856 return -EFAULT; 857 } 858 859 /* Another get_user_pages is running at the same time?? */ 860 if (WARN_ON(gtt->range)) 861 return -EFAULT; 862 863 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 864 return -ESRCH; 865 866 range = kzalloc(sizeof(*range), GFP_KERNEL); 867 if (unlikely(!range)) { 868 r = -ENOMEM; 869 goto out; 870 } 871 range->notifier = &bo->notifier; 872 range->start = bo->notifier.interval_tree.start; 873 range->end = bo->notifier.interval_tree.last + 1; 874 range->default_flags = HMM_PFN_REQ_FAULT; 875 if (!amdgpu_ttm_tt_is_readonly(ttm)) 876 range->default_flags |= HMM_PFN_REQ_WRITE; 877 878 range->hmm_pfns = kvmalloc_array(ttm->num_pages, 879 sizeof(*range->hmm_pfns), GFP_KERNEL); 880 if (unlikely(!range->hmm_pfns)) { 881 r = -ENOMEM; 882 goto out_free_ranges; 883 } 884 885 mmap_read_lock(mm); 886 vma = find_vma(mm, start); 887 if (unlikely(!vma || start < vma->vm_start)) { 888 r = -EFAULT; 889 goto out_unlock; 890 } 891 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 892 vma->vm_file)) { 893 r = -EPERM; 894 goto out_unlock; 895 } 896 mmap_read_unlock(mm); 897 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 898 899 retry: 900 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 901 902 mmap_read_lock(mm); 903 r = hmm_range_fault(range); 904 mmap_read_unlock(mm); 905 if (unlikely(r)) { 906 /* 907 * FIXME: This timeout should encompass the retry from 908 * mmu_interval_read_retry() as well. 909 */ 910 if (r == -EBUSY && !time_after(jiffies, timeout)) 911 goto retry; 912 goto out_free_pfns; 913 } 914 915 /* 916 * Due to default_flags, all pages are HMM_PFN_VALID or 917 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside 918 * the notifier_lock, and mmu_interval_read_retry() must be done first. 919 */ 920 for (i = 0; i < ttm->num_pages; i++) 921 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); 922 923 gtt->range = range; 924 mmput(mm); 925 926 return 0; 927 928 out_unlock: 929 mmap_read_unlock(mm); 930 out_free_pfns: 931 kvfree(range->hmm_pfns); 932 out_free_ranges: 933 kfree(range); 934 out: 935 mmput(mm); 936 return r; 937 } 938 939 /** 940 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 941 * Check if the pages backing this ttm range have been invalidated 942 * 943 * Returns: true if pages are still valid 944 */ 945 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 946 { 947 struct amdgpu_ttm_tt *gtt = (void *)ttm; 948 bool r = false; 949 950 if (!gtt || !gtt->userptr) 951 return false; 952 953 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n", 954 gtt->userptr, ttm->num_pages); 955 956 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 957 "No user pages to check\n"); 958 959 if (gtt->range) { 960 /* 961 * FIXME: Must always hold notifier_lock for this, and must 962 * not ignore the return code. 963 */ 964 r = mmu_interval_read_retry(gtt->range->notifier, 965 gtt->range->notifier_seq); 966 kvfree(gtt->range->hmm_pfns); 967 kfree(gtt->range); 968 gtt->range = NULL; 969 } 970 971 return !r; 972 } 973 #endif 974 975 /** 976 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 977 * 978 * Called by amdgpu_cs_list_validate(). This creates the page list 979 * that backs user memory and will ultimately be mapped into the device 980 * address space. 981 */ 982 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 983 { 984 unsigned long i; 985 986 for (i = 0; i < ttm->num_pages; ++i) 987 ttm->pages[i] = pages ? pages[i] : NULL; 988 } 989 990 /** 991 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 992 * 993 * Called by amdgpu_ttm_backend_bind() 994 **/ 995 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, 996 struct ttm_tt *ttm) 997 { 998 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 999 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1000 int r; 1001 1002 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1003 enum dma_data_direction direction = write ? 1004 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1005 1006 /* Allocate an SG array and squash pages into it */ 1007 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 1008 ttm->num_pages << PAGE_SHIFT, 1009 GFP_KERNEL); 1010 if (r) 1011 goto release_sg; 1012 1013 /* Map SG to device */ 1014 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 1015 if (r) 1016 goto release_sg; 1017 1018 /* convert SG to linear array of pages and dma addresses */ 1019 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1020 gtt->ttm.dma_address, ttm->num_pages); 1021 1022 return 0; 1023 1024 release_sg: 1025 kfree(ttm->sg); 1026 return r; 1027 } 1028 1029 /** 1030 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 1031 */ 1032 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, 1033 struct ttm_tt *ttm) 1034 { 1035 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1036 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1037 1038 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1039 enum dma_data_direction direction = write ? 1040 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1041 1042 /* double check that we don't free the table twice */ 1043 if (!ttm->sg->sgl) 1044 return; 1045 1046 /* unmap the pages mapped to the device */ 1047 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 1048 sg_free_table(ttm->sg); 1049 1050 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 1051 if (gtt->range) { 1052 unsigned long i; 1053 1054 for (i = 0; i < ttm->num_pages; i++) { 1055 if (ttm->pages[i] != 1056 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 1057 break; 1058 } 1059 1060 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 1061 } 1062 #endif 1063 } 1064 1065 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 1066 struct ttm_buffer_object *tbo, 1067 uint64_t flags) 1068 { 1069 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 1070 struct ttm_tt *ttm = tbo->ttm; 1071 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1072 int r; 1073 1074 if (amdgpu_bo_encrypted(abo)) 1075 flags |= AMDGPU_PTE_TMZ; 1076 1077 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 1078 uint64_t page_idx = 1; 1079 1080 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 1081 ttm->pages, gtt->ttm.dma_address, flags); 1082 if (r) 1083 goto gart_bind_fail; 1084 1085 /* The memory type of the first page defaults to UC. Now 1086 * modify the memory type to NC from the second page of 1087 * the BO onward. 1088 */ 1089 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1090 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 1091 1092 r = amdgpu_gart_bind(adev, 1093 gtt->offset + (page_idx << PAGE_SHIFT), 1094 ttm->num_pages - page_idx, 1095 &ttm->pages[page_idx], 1096 &(gtt->ttm.dma_address[page_idx]), flags); 1097 } else { 1098 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1099 ttm->pages, gtt->ttm.dma_address, flags); 1100 } 1101 1102 gart_bind_fail: 1103 if (r) 1104 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1105 ttm->num_pages, gtt->offset); 1106 1107 return r; 1108 } 1109 1110 /** 1111 * amdgpu_ttm_backend_bind - Bind GTT memory 1112 * 1113 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 1114 * This handles binding GTT memory to the device address space. 1115 */ 1116 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, 1117 struct ttm_tt *ttm, 1118 struct ttm_resource *bo_mem) 1119 { 1120 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1121 struct amdgpu_ttm_tt *gtt = (void*)ttm; 1122 uint64_t flags; 1123 int r = 0; 1124 1125 if (gtt->userptr) { 1126 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 1127 if (r) { 1128 DRM_ERROR("failed to pin userptr\n"); 1129 return r; 1130 } 1131 } 1132 if (!ttm->num_pages) { 1133 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 1134 ttm->num_pages, bo_mem, ttm); 1135 } 1136 1137 if (bo_mem->mem_type == AMDGPU_PL_GDS || 1138 bo_mem->mem_type == AMDGPU_PL_GWS || 1139 bo_mem->mem_type == AMDGPU_PL_OA) 1140 return -EINVAL; 1141 1142 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 1143 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 1144 return 0; 1145 } 1146 1147 /* compute PTE flags relevant to this BO memory */ 1148 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 1149 1150 /* bind pages into GART page tables */ 1151 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 1152 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1153 ttm->pages, gtt->ttm.dma_address, flags); 1154 1155 if (r) 1156 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1157 ttm->num_pages, gtt->offset); 1158 return r; 1159 } 1160 1161 /** 1162 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object 1163 */ 1164 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1165 { 1166 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1167 struct ttm_operation_ctx ctx = { false, false }; 1168 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; 1169 struct ttm_resource tmp; 1170 struct ttm_placement placement; 1171 struct ttm_place placements; 1172 uint64_t addr, flags; 1173 int r; 1174 1175 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1176 return 0; 1177 1178 addr = amdgpu_gmc_agp_addr(bo); 1179 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1180 bo->mem.start = addr >> PAGE_SHIFT; 1181 } else { 1182 1183 /* allocate GART space */ 1184 tmp = bo->mem; 1185 tmp.mm_node = NULL; 1186 placement.num_placement = 1; 1187 placement.placement = &placements; 1188 placement.num_busy_placement = 1; 1189 placement.busy_placement = &placements; 1190 placements.fpfn = 0; 1191 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1192 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | 1193 TTM_PL_FLAG_TT; 1194 1195 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1196 if (unlikely(r)) 1197 return r; 1198 1199 /* compute PTE flags for this buffer object */ 1200 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1201 1202 /* Bind pages */ 1203 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1204 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1205 if (unlikely(r)) { 1206 ttm_resource_free(bo, &tmp); 1207 return r; 1208 } 1209 1210 ttm_resource_free(bo, &bo->mem); 1211 bo->mem = tmp; 1212 } 1213 1214 return 0; 1215 } 1216 1217 /** 1218 * amdgpu_ttm_recover_gart - Rebind GTT pages 1219 * 1220 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1221 * rebind GTT pages during a GPU reset. 1222 */ 1223 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1224 { 1225 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1226 uint64_t flags; 1227 int r; 1228 1229 if (!tbo->ttm) 1230 return 0; 1231 1232 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1233 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1234 1235 return r; 1236 } 1237 1238 /** 1239 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1240 * 1241 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1242 * ttm_tt_destroy(). 1243 */ 1244 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, 1245 struct ttm_tt *ttm) 1246 { 1247 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1248 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1249 int r; 1250 1251 /* if the pages have userptr pinning then clear that first */ 1252 if (gtt->userptr) 1253 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1254 1255 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1256 return; 1257 1258 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1259 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1260 if (r) 1261 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", 1262 gtt->ttm.ttm.num_pages, gtt->offset); 1263 } 1264 1265 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev, 1266 struct ttm_tt *ttm) 1267 { 1268 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1269 1270 if (gtt->usertask) 1271 put_task_struct(gtt->usertask); 1272 1273 ttm_dma_tt_fini(>t->ttm); 1274 kfree(gtt); 1275 } 1276 1277 static struct ttm_backend_func amdgpu_backend_func = { 1278 .bind = &amdgpu_ttm_backend_bind, 1279 .unbind = &amdgpu_ttm_backend_unbind, 1280 .destroy = &amdgpu_ttm_backend_destroy, 1281 }; 1282 1283 /** 1284 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1285 * 1286 * @bo: The buffer object to create a GTT ttm_tt object around 1287 * 1288 * Called by ttm_tt_create(). 1289 */ 1290 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1291 uint32_t page_flags) 1292 { 1293 struct amdgpu_ttm_tt *gtt; 1294 1295 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1296 if (gtt == NULL) { 1297 return NULL; 1298 } 1299 gtt->ttm.ttm.func = &amdgpu_backend_func; 1300 gtt->gobj = &bo->base; 1301 1302 /* allocate space for the uninitialized page entries */ 1303 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) { 1304 kfree(gtt); 1305 return NULL; 1306 } 1307 return >t->ttm.ttm; 1308 } 1309 1310 /** 1311 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1312 * 1313 * Map the pages of a ttm_tt object to an address space visible 1314 * to the underlying device. 1315 */ 1316 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev, 1317 struct ttm_tt *ttm, 1318 struct ttm_operation_ctx *ctx) 1319 { 1320 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1321 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1322 1323 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1324 if (gtt && gtt->userptr) { 1325 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1326 if (!ttm->sg) 1327 return -ENOMEM; 1328 1329 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1330 ttm->state = tt_unbound; 1331 return 0; 1332 } 1333 1334 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1335 if (!ttm->sg) { 1336 struct dma_buf_attachment *attach; 1337 struct sg_table *sgt; 1338 1339 attach = gtt->gobj->import_attach; 1340 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1341 if (IS_ERR(sgt)) 1342 return PTR_ERR(sgt); 1343 1344 ttm->sg = sgt; 1345 } 1346 1347 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1348 gtt->ttm.dma_address, 1349 ttm->num_pages); 1350 ttm->state = tt_unbound; 1351 return 0; 1352 } 1353 1354 #ifdef CONFIG_SWIOTLB 1355 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1356 return ttm_dma_populate(>t->ttm, adev->dev, ctx); 1357 } 1358 #endif 1359 1360 /* fall back to generic helper to populate the page array 1361 * and map them to the device */ 1362 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx); 1363 } 1364 1365 /** 1366 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1367 * 1368 * Unmaps pages of a ttm_tt object from the device address space and 1369 * unpopulates the page array backing it. 1370 */ 1371 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm) 1372 { 1373 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1374 struct amdgpu_device *adev; 1375 1376 if (gtt && gtt->userptr) { 1377 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1378 kfree(ttm->sg); 1379 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1380 return; 1381 } 1382 1383 if (ttm->sg && gtt->gobj->import_attach) { 1384 struct dma_buf_attachment *attach; 1385 1386 attach = gtt->gobj->import_attach; 1387 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1388 ttm->sg = NULL; 1389 return; 1390 } 1391 1392 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1393 return; 1394 1395 adev = amdgpu_ttm_adev(bdev); 1396 1397 #ifdef CONFIG_SWIOTLB 1398 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1399 ttm_dma_unpopulate(>t->ttm, adev->dev); 1400 return; 1401 } 1402 #endif 1403 1404 /* fall back to generic helper to unmap and unpopulate array */ 1405 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); 1406 } 1407 1408 /** 1409 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1410 * task 1411 * 1412 * @bo: The ttm_buffer_object to bind this userptr to 1413 * @addr: The address in the current tasks VM space to use 1414 * @flags: Requirements of userptr object. 1415 * 1416 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1417 * to current task 1418 */ 1419 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1420 uint64_t addr, uint32_t flags) 1421 { 1422 struct amdgpu_ttm_tt *gtt; 1423 1424 if (!bo->ttm) { 1425 /* TODO: We want a separate TTM object type for userptrs */ 1426 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1427 if (bo->ttm == NULL) 1428 return -ENOMEM; 1429 } 1430 1431 gtt = (void*)bo->ttm; 1432 gtt->userptr = addr; 1433 gtt->userflags = flags; 1434 1435 if (gtt->usertask) 1436 put_task_struct(gtt->usertask); 1437 gtt->usertask = current->group_leader; 1438 get_task_struct(gtt->usertask); 1439 1440 return 0; 1441 } 1442 1443 /** 1444 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1445 */ 1446 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1447 { 1448 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1449 1450 if (gtt == NULL) 1451 return NULL; 1452 1453 if (gtt->usertask == NULL) 1454 return NULL; 1455 1456 return gtt->usertask->mm; 1457 } 1458 1459 /** 1460 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1461 * address range for the current task. 1462 * 1463 */ 1464 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1465 unsigned long end) 1466 { 1467 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1468 unsigned long size; 1469 1470 if (gtt == NULL || !gtt->userptr) 1471 return false; 1472 1473 /* Return false if no part of the ttm_tt object lies within 1474 * the range 1475 */ 1476 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 1477 if (gtt->userptr > end || gtt->userptr + size <= start) 1478 return false; 1479 1480 return true; 1481 } 1482 1483 /** 1484 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1485 */ 1486 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1487 { 1488 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1489 1490 if (gtt == NULL || !gtt->userptr) 1491 return false; 1492 1493 return true; 1494 } 1495 1496 /** 1497 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1498 */ 1499 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1500 { 1501 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1502 1503 if (gtt == NULL) 1504 return false; 1505 1506 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1507 } 1508 1509 /** 1510 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1511 * 1512 * @ttm: The ttm_tt object to compute the flags for 1513 * @mem: The memory registry backing this ttm_tt object 1514 * 1515 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1516 */ 1517 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1518 { 1519 uint64_t flags = 0; 1520 1521 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1522 flags |= AMDGPU_PTE_VALID; 1523 1524 if (mem && mem->mem_type == TTM_PL_TT) { 1525 flags |= AMDGPU_PTE_SYSTEM; 1526 1527 if (ttm->caching_state == tt_cached) 1528 flags |= AMDGPU_PTE_SNOOPED; 1529 } 1530 1531 return flags; 1532 } 1533 1534 /** 1535 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1536 * 1537 * @ttm: The ttm_tt object to compute the flags for 1538 * @mem: The memory registry backing this ttm_tt object 1539 1540 * Figure out the flags to use for a VM PTE (Page Table Entry). 1541 */ 1542 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1543 struct ttm_resource *mem) 1544 { 1545 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1546 1547 flags |= adev->gart.gart_pte_flags; 1548 flags |= AMDGPU_PTE_READABLE; 1549 1550 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1551 flags |= AMDGPU_PTE_WRITEABLE; 1552 1553 return flags; 1554 } 1555 1556 /** 1557 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1558 * object. 1559 * 1560 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1561 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1562 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1563 * used to clean out a memory space. 1564 */ 1565 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1566 const struct ttm_place *place) 1567 { 1568 unsigned long num_pages = bo->mem.num_pages; 1569 struct drm_mm_node *node = bo->mem.mm_node; 1570 struct dma_resv_list *flist; 1571 struct dma_fence *f; 1572 int i; 1573 1574 if (bo->type == ttm_bo_type_kernel && 1575 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1576 return false; 1577 1578 /* If bo is a KFD BO, check if the bo belongs to the current process. 1579 * If true, then return false as any KFD process needs all its BOs to 1580 * be resident to run successfully 1581 */ 1582 flist = dma_resv_get_list(bo->base.resv); 1583 if (flist) { 1584 for (i = 0; i < flist->shared_count; ++i) { 1585 f = rcu_dereference_protected(flist->shared[i], 1586 dma_resv_held(bo->base.resv)); 1587 if (amdkfd_fence_check_mm(f, current->mm)) 1588 return false; 1589 } 1590 } 1591 1592 switch (bo->mem.mem_type) { 1593 case TTM_PL_TT: 1594 if (amdgpu_bo_is_amdgpu_bo(bo) && 1595 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1596 return false; 1597 return true; 1598 1599 case TTM_PL_VRAM: 1600 /* Check each drm MM node individually */ 1601 while (num_pages) { 1602 if (place->fpfn < (node->start + node->size) && 1603 !(place->lpfn && place->lpfn <= node->start)) 1604 return true; 1605 1606 num_pages -= node->size; 1607 ++node; 1608 } 1609 return false; 1610 1611 default: 1612 break; 1613 } 1614 1615 return ttm_bo_eviction_valuable(bo, place); 1616 } 1617 1618 /** 1619 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1620 * 1621 * @bo: The buffer object to read/write 1622 * @offset: Offset into buffer object 1623 * @buf: Secondary buffer to write/read from 1624 * @len: Length in bytes of access 1625 * @write: true if writing 1626 * 1627 * This is used to access VRAM that backs a buffer object via MMIO 1628 * access for debugging purposes. 1629 */ 1630 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1631 unsigned long offset, 1632 void *buf, int len, int write) 1633 { 1634 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1635 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1636 struct drm_mm_node *nodes; 1637 uint32_t value = 0; 1638 int ret = 0; 1639 uint64_t pos; 1640 unsigned long flags; 1641 1642 if (bo->mem.mem_type != TTM_PL_VRAM) 1643 return -EIO; 1644 1645 pos = offset; 1646 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); 1647 pos += (nodes->start << PAGE_SHIFT); 1648 1649 while (len && pos < adev->gmc.mc_vram_size) { 1650 uint64_t aligned_pos = pos & ~(uint64_t)3; 1651 uint64_t bytes = 4 - (pos & 3); 1652 uint32_t shift = (pos & 3) * 8; 1653 uint32_t mask = 0xffffffff << shift; 1654 1655 if (len < bytes) { 1656 mask &= 0xffffffff >> (bytes - len) * 8; 1657 bytes = len; 1658 } 1659 1660 if (mask != 0xffffffff) { 1661 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1662 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1663 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1664 if (!write || mask != 0xffffffff) 1665 value = RREG32_NO_KIQ(mmMM_DATA); 1666 if (write) { 1667 value &= ~mask; 1668 value |= (*(uint32_t *)buf << shift) & mask; 1669 WREG32_NO_KIQ(mmMM_DATA, value); 1670 } 1671 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1672 if (!write) { 1673 value = (value & mask) >> shift; 1674 memcpy(buf, &value, bytes); 1675 } 1676 } else { 1677 bytes = (nodes->start + nodes->size) << PAGE_SHIFT; 1678 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); 1679 1680 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, 1681 bytes, write); 1682 } 1683 1684 ret += bytes; 1685 buf = (uint8_t *)buf + bytes; 1686 pos += bytes; 1687 len -= bytes; 1688 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { 1689 ++nodes; 1690 pos = (nodes->start << PAGE_SHIFT); 1691 } 1692 } 1693 1694 return ret; 1695 } 1696 1697 static struct ttm_bo_driver amdgpu_bo_driver = { 1698 .ttm_tt_create = &amdgpu_ttm_tt_create, 1699 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1700 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1701 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1702 .evict_flags = &amdgpu_evict_flags, 1703 .move = &amdgpu_bo_move, 1704 .verify_access = &amdgpu_verify_access, 1705 .move_notify = &amdgpu_bo_move_notify, 1706 .release_notify = &amdgpu_bo_release_notify, 1707 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1708 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1709 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1710 .access_memory = &amdgpu_ttm_access_memory, 1711 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1712 }; 1713 1714 /* 1715 * Firmware Reservation functions 1716 */ 1717 /** 1718 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1719 * 1720 * @adev: amdgpu_device pointer 1721 * 1722 * free fw reserved vram if it has been reserved. 1723 */ 1724 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1725 { 1726 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, 1727 NULL, &adev->fw_vram_usage.va); 1728 } 1729 1730 /** 1731 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1732 * 1733 * @adev: amdgpu_device pointer 1734 * 1735 * create bo vram reservation from fw. 1736 */ 1737 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1738 { 1739 uint64_t vram_size = adev->gmc.visible_vram_size; 1740 1741 adev->fw_vram_usage.va = NULL; 1742 adev->fw_vram_usage.reserved_bo = NULL; 1743 1744 if (adev->fw_vram_usage.size == 0 || 1745 adev->fw_vram_usage.size > vram_size) 1746 return 0; 1747 1748 return amdgpu_bo_create_kernel_at(adev, 1749 adev->fw_vram_usage.start_offset, 1750 adev->fw_vram_usage.size, 1751 AMDGPU_GEM_DOMAIN_VRAM, 1752 &adev->fw_vram_usage.reserved_bo, 1753 &adev->fw_vram_usage.va); 1754 } 1755 1756 /* 1757 * Memoy training reservation functions 1758 */ 1759 1760 /** 1761 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1762 * 1763 * @adev: amdgpu_device pointer 1764 * 1765 * free memory training reserved vram if it has been reserved. 1766 */ 1767 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1768 { 1769 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1770 1771 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1772 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1773 ctx->c2p_bo = NULL; 1774 1775 return 0; 1776 } 1777 1778 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1779 { 1780 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1781 1782 memset(ctx, 0, sizeof(*ctx)); 1783 1784 ctx->c2p_train_data_offset = 1785 ALIGN((adev->gmc.mc_vram_size - adev->discovery_tmr_size - SZ_1M), SZ_1M); 1786 ctx->p2c_train_data_offset = 1787 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1788 ctx->train_data_size = 1789 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1790 1791 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1792 ctx->train_data_size, 1793 ctx->p2c_train_data_offset, 1794 ctx->c2p_train_data_offset); 1795 } 1796 1797 /* 1798 * reserve TMR memory at the top of VRAM which holds 1799 * IP Discovery data and is protected by PSP. 1800 */ 1801 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1802 { 1803 int ret; 1804 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1805 bool mem_train_support = false; 1806 1807 if (!amdgpu_sriov_vf(adev)) { 1808 ret = amdgpu_mem_train_support(adev); 1809 if (ret == 1) 1810 mem_train_support = true; 1811 else if (ret == -1) 1812 return -EINVAL; 1813 else 1814 DRM_DEBUG("memory training does not support!\n"); 1815 } 1816 1817 /* 1818 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1819 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1820 * 1821 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1822 * discovery data and G6 memory training data respectively 1823 */ 1824 adev->discovery_tmr_size = 1825 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1826 if (!adev->discovery_tmr_size) 1827 adev->discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1828 1829 if (mem_train_support) { 1830 /* reserve vram for mem train according to TMR location */ 1831 amdgpu_ttm_training_data_block_init(adev); 1832 ret = amdgpu_bo_create_kernel_at(adev, 1833 ctx->c2p_train_data_offset, 1834 ctx->train_data_size, 1835 AMDGPU_GEM_DOMAIN_VRAM, 1836 &ctx->c2p_bo, 1837 NULL); 1838 if (ret) { 1839 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1840 amdgpu_ttm_training_reserve_vram_fini(adev); 1841 return ret; 1842 } 1843 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1844 } 1845 1846 ret = amdgpu_bo_create_kernel_at(adev, 1847 adev->gmc.real_vram_size - adev->discovery_tmr_size, 1848 adev->discovery_tmr_size, 1849 AMDGPU_GEM_DOMAIN_VRAM, 1850 &adev->discovery_memory, 1851 NULL); 1852 if (ret) { 1853 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1854 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL); 1855 return ret; 1856 } 1857 1858 return 0; 1859 } 1860 1861 /** 1862 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1863 * gtt/vram related fields. 1864 * 1865 * This initializes all of the memory space pools that the TTM layer 1866 * will need such as the GTT space (system memory mapped to the device), 1867 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1868 * can be mapped per VMID. 1869 */ 1870 int amdgpu_ttm_init(struct amdgpu_device *adev) 1871 { 1872 uint64_t gtt_size; 1873 int r; 1874 u64 vis_vram_limit; 1875 void *stolen_vga_buf; 1876 1877 mutex_init(&adev->mman.gtt_window_lock); 1878 1879 /* No others user of address space so set it to 0 */ 1880 r = ttm_bo_device_init(&adev->mman.bdev, 1881 &amdgpu_bo_driver, 1882 adev->ddev->anon_inode->i_mapping, 1883 adev->ddev->vma_offset_manager, 1884 dma_addressing_limited(adev->dev)); 1885 if (r) { 1886 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1887 return r; 1888 } 1889 adev->mman.initialized = true; 1890 1891 /* We opt to avoid OOM on system pages allocations */ 1892 adev->mman.bdev.no_retry = true; 1893 1894 /* Initialize VRAM pool with all of VRAM divided into pages */ 1895 r = amdgpu_vram_mgr_init(adev); 1896 if (r) { 1897 DRM_ERROR("Failed initializing VRAM heap.\n"); 1898 return r; 1899 } 1900 1901 /* Reduce size of CPU-visible VRAM if requested */ 1902 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1903 if (amdgpu_vis_vram_limit > 0 && 1904 vis_vram_limit <= adev->gmc.visible_vram_size) 1905 adev->gmc.visible_vram_size = vis_vram_limit; 1906 1907 /* Change the size here instead of the init above so only lpfn is affected */ 1908 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1909 #ifdef CONFIG_64BIT 1910 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1911 adev->gmc.visible_vram_size); 1912 #endif 1913 1914 /* 1915 *The reserved vram for firmware must be pinned to the specified 1916 *place on the VRAM, so reserve it early. 1917 */ 1918 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1919 if (r) { 1920 return r; 1921 } 1922 1923 /* 1924 * only NAVI10 and onwards ASIC support for IP discovery. 1925 * If IP discovery enabled, a block of memory should be 1926 * reserved for IP discovey. 1927 */ 1928 if (adev->discovery_bin) { 1929 r = amdgpu_ttm_reserve_tmr(adev); 1930 if (r) 1931 return r; 1932 } 1933 1934 /* allocate memory as required for VGA 1935 * This is used for VGA emulation and pre-OS scanout buffers to 1936 * avoid display artifacts while transitioning between pre-OS 1937 * and driver. */ 1938 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, 1939 AMDGPU_GEM_DOMAIN_VRAM, 1940 &adev->stolen_vga_memory, 1941 NULL, &stolen_vga_buf); 1942 if (r) 1943 return r; 1944 1945 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1946 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1947 1948 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1949 * or whatever the user passed on module init */ 1950 if (amdgpu_gtt_size == -1) { 1951 struct sysinfo si; 1952 1953 si_meminfo(&si); 1954 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1955 adev->gmc.mc_vram_size), 1956 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1957 } 1958 else 1959 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1960 1961 /* Initialize GTT memory pool */ 1962 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1963 if (r) { 1964 DRM_ERROR("Failed initializing GTT heap.\n"); 1965 return r; 1966 } 1967 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1968 (unsigned)(gtt_size / (1024 * 1024))); 1969 1970 /* Initialize various on-chip memory pools */ 1971 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1972 if (r) { 1973 DRM_ERROR("Failed initializing GDS heap.\n"); 1974 return r; 1975 } 1976 1977 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1978 if (r) { 1979 DRM_ERROR("Failed initializing gws heap.\n"); 1980 return r; 1981 } 1982 1983 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1984 if (r) { 1985 DRM_ERROR("Failed initializing oa heap.\n"); 1986 return r; 1987 } 1988 1989 return 0; 1990 } 1991 1992 /** 1993 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm 1994 */ 1995 void amdgpu_ttm_late_init(struct amdgpu_device *adev) 1996 { 1997 void *stolen_vga_buf; 1998 /* return the VGA stolen memory (if any) back to VRAM */ 1999 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 2000 } 2001 2002 /** 2003 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2004 */ 2005 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2006 { 2007 if (!adev->mman.initialized) 2008 return; 2009 2010 amdgpu_ttm_training_reserve_vram_fini(adev); 2011 /* return the IP Discovery TMR memory back to VRAM */ 2012 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL); 2013 amdgpu_ttm_fw_reserve_vram_fini(adev); 2014 2015 if (adev->mman.aper_base_kaddr) 2016 iounmap(adev->mman.aper_base_kaddr); 2017 adev->mman.aper_base_kaddr = NULL; 2018 2019 amdgpu_vram_mgr_fini(adev); 2020 amdgpu_gtt_mgr_fini(adev); 2021 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 2022 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2023 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2024 ttm_bo_device_release(&adev->mman.bdev); 2025 adev->mman.initialized = false; 2026 DRM_INFO("amdgpu: ttm finalized\n"); 2027 } 2028 2029 /** 2030 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2031 * 2032 * @adev: amdgpu_device pointer 2033 * @enable: true when we can use buffer functions. 2034 * 2035 * Enable/disable use of buffer functions during suspend/resume. This should 2036 * only be called at bootup or when userspace isn't running. 2037 */ 2038 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2039 { 2040 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2041 uint64_t size; 2042 int r; 2043 2044 if (!adev->mman.initialized || adev->in_gpu_reset || 2045 adev->mman.buffer_funcs_enabled == enable) 2046 return; 2047 2048 if (enable) { 2049 struct amdgpu_ring *ring; 2050 struct drm_gpu_scheduler *sched; 2051 2052 ring = adev->mman.buffer_funcs_ring; 2053 sched = &ring->sched; 2054 r = drm_sched_entity_init(&adev->mman.entity, 2055 DRM_SCHED_PRIORITY_KERNEL, &sched, 2056 1, NULL); 2057 if (r) { 2058 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2059 r); 2060 return; 2061 } 2062 } else { 2063 drm_sched_entity_destroy(&adev->mman.entity); 2064 dma_fence_put(man->move); 2065 man->move = NULL; 2066 } 2067 2068 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2069 if (enable) 2070 size = adev->gmc.real_vram_size; 2071 else 2072 size = adev->gmc.visible_vram_size; 2073 man->size = size >> PAGE_SHIFT; 2074 adev->mman.buffer_funcs_enabled = enable; 2075 } 2076 2077 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 2078 { 2079 struct drm_file *file_priv = filp->private_data; 2080 struct amdgpu_device *adev = file_priv->minor->dev->dev_private; 2081 2082 if (adev == NULL) 2083 return -EINVAL; 2084 2085 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 2086 } 2087 2088 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2089 uint64_t dst_offset, uint32_t byte_count, 2090 struct dma_resv *resv, 2091 struct dma_fence **fence, bool direct_submit, 2092 bool vm_needs_flush, bool tmz) 2093 { 2094 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 2095 AMDGPU_IB_POOL_DELAYED; 2096 struct amdgpu_device *adev = ring->adev; 2097 struct amdgpu_job *job; 2098 2099 uint32_t max_bytes; 2100 unsigned num_loops, num_dw; 2101 unsigned i; 2102 int r; 2103 2104 if (direct_submit && !ring->sched.ready) { 2105 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2106 return -EINVAL; 2107 } 2108 2109 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2110 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2111 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2112 2113 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 2114 if (r) 2115 return r; 2116 2117 if (vm_needs_flush) { 2118 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 2119 job->vm_needs_flush = true; 2120 } 2121 if (resv) { 2122 r = amdgpu_sync_resv(adev, &job->sync, resv, 2123 AMDGPU_SYNC_ALWAYS, 2124 AMDGPU_FENCE_OWNER_UNDEFINED); 2125 if (r) { 2126 DRM_ERROR("sync failed (%d).\n", r); 2127 goto error_free; 2128 } 2129 } 2130 2131 for (i = 0; i < num_loops; i++) { 2132 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2133 2134 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2135 dst_offset, cur_size_in_bytes, tmz); 2136 2137 src_offset += cur_size_in_bytes; 2138 dst_offset += cur_size_in_bytes; 2139 byte_count -= cur_size_in_bytes; 2140 } 2141 2142 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2143 WARN_ON(job->ibs[0].length_dw > num_dw); 2144 if (direct_submit) 2145 r = amdgpu_job_submit_direct(job, ring, fence); 2146 else 2147 r = amdgpu_job_submit(job, &adev->mman.entity, 2148 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2149 if (r) 2150 goto error_free; 2151 2152 return r; 2153 2154 error_free: 2155 amdgpu_job_free(job); 2156 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2157 return r; 2158 } 2159 2160 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2161 uint32_t src_data, 2162 struct dma_resv *resv, 2163 struct dma_fence **fence) 2164 { 2165 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2166 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2167 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2168 2169 struct drm_mm_node *mm_node; 2170 unsigned long num_pages; 2171 unsigned int num_loops, num_dw; 2172 2173 struct amdgpu_job *job; 2174 int r; 2175 2176 if (!adev->mman.buffer_funcs_enabled) { 2177 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2178 return -EINVAL; 2179 } 2180 2181 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2182 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2183 if (r) 2184 return r; 2185 } 2186 2187 num_pages = bo->tbo.num_pages; 2188 mm_node = bo->tbo.mem.mm_node; 2189 num_loops = 0; 2190 while (num_pages) { 2191 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2192 2193 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); 2194 num_pages -= mm_node->size; 2195 ++mm_node; 2196 } 2197 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2198 2199 /* for IB padding */ 2200 num_dw += 64; 2201 2202 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2203 &job); 2204 if (r) 2205 return r; 2206 2207 if (resv) { 2208 r = amdgpu_sync_resv(adev, &job->sync, resv, 2209 AMDGPU_SYNC_ALWAYS, 2210 AMDGPU_FENCE_OWNER_UNDEFINED); 2211 if (r) { 2212 DRM_ERROR("sync failed (%d).\n", r); 2213 goto error_free; 2214 } 2215 } 2216 2217 num_pages = bo->tbo.num_pages; 2218 mm_node = bo->tbo.mem.mm_node; 2219 2220 while (num_pages) { 2221 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2222 uint64_t dst_addr; 2223 2224 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); 2225 while (byte_count) { 2226 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, 2227 max_bytes); 2228 2229 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 2230 dst_addr, cur_size_in_bytes); 2231 2232 dst_addr += cur_size_in_bytes; 2233 byte_count -= cur_size_in_bytes; 2234 } 2235 2236 num_pages -= mm_node->size; 2237 ++mm_node; 2238 } 2239 2240 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2241 WARN_ON(job->ibs[0].length_dw > num_dw); 2242 r = amdgpu_job_submit(job, &adev->mman.entity, 2243 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2244 if (r) 2245 goto error_free; 2246 2247 return 0; 2248 2249 error_free: 2250 amdgpu_job_free(job); 2251 return r; 2252 } 2253 2254 #if defined(CONFIG_DEBUG_FS) 2255 2256 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 2257 { 2258 struct drm_info_node *node = (struct drm_info_node *)m->private; 2259 unsigned ttm_pl = (uintptr_t)node->info_ent->data; 2260 struct drm_device *dev = node->minor->dev; 2261 struct amdgpu_device *adev = dev->dev_private; 2262 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); 2263 struct drm_printer p = drm_seq_file_printer(m); 2264 2265 man->func->debug(man, &p); 2266 return 0; 2267 } 2268 2269 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 2270 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, 2271 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, 2272 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, 2273 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, 2274 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, 2275 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 2276 #ifdef CONFIG_SWIOTLB 2277 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 2278 #endif 2279 }; 2280 2281 /** 2282 * amdgpu_ttm_vram_read - Linear read access to VRAM 2283 * 2284 * Accesses VRAM via MMIO for debugging purposes. 2285 */ 2286 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2287 size_t size, loff_t *pos) 2288 { 2289 struct amdgpu_device *adev = file_inode(f)->i_private; 2290 ssize_t result = 0; 2291 2292 if (size & 0x3 || *pos & 0x3) 2293 return -EINVAL; 2294 2295 if (*pos >= adev->gmc.mc_vram_size) 2296 return -ENXIO; 2297 2298 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2299 while (size) { 2300 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2301 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2302 2303 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2304 if (copy_to_user(buf, value, bytes)) 2305 return -EFAULT; 2306 2307 result += bytes; 2308 buf += bytes; 2309 *pos += bytes; 2310 size -= bytes; 2311 } 2312 2313 return result; 2314 } 2315 2316 /** 2317 * amdgpu_ttm_vram_write - Linear write access to VRAM 2318 * 2319 * Accesses VRAM via MMIO for debugging purposes. 2320 */ 2321 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2322 size_t size, loff_t *pos) 2323 { 2324 struct amdgpu_device *adev = file_inode(f)->i_private; 2325 ssize_t result = 0; 2326 int r; 2327 2328 if (size & 0x3 || *pos & 0x3) 2329 return -EINVAL; 2330 2331 if (*pos >= adev->gmc.mc_vram_size) 2332 return -ENXIO; 2333 2334 while (size) { 2335 unsigned long flags; 2336 uint32_t value; 2337 2338 if (*pos >= adev->gmc.mc_vram_size) 2339 return result; 2340 2341 r = get_user(value, (uint32_t *)buf); 2342 if (r) 2343 return r; 2344 2345 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2346 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2347 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2348 WREG32_NO_KIQ(mmMM_DATA, value); 2349 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2350 2351 result += 4; 2352 buf += 4; 2353 *pos += 4; 2354 size -= 4; 2355 } 2356 2357 return result; 2358 } 2359 2360 static const struct file_operations amdgpu_ttm_vram_fops = { 2361 .owner = THIS_MODULE, 2362 .read = amdgpu_ttm_vram_read, 2363 .write = amdgpu_ttm_vram_write, 2364 .llseek = default_llseek, 2365 }; 2366 2367 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2368 2369 /** 2370 * amdgpu_ttm_gtt_read - Linear read access to GTT memory 2371 */ 2372 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 2373 size_t size, loff_t *pos) 2374 { 2375 struct amdgpu_device *adev = file_inode(f)->i_private; 2376 ssize_t result = 0; 2377 int r; 2378 2379 while (size) { 2380 loff_t p = *pos / PAGE_SIZE; 2381 unsigned off = *pos & ~PAGE_MASK; 2382 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 2383 struct page *page; 2384 void *ptr; 2385 2386 if (p >= adev->gart.num_cpu_pages) 2387 return result; 2388 2389 page = adev->gart.pages[p]; 2390 if (page) { 2391 ptr = kmap(page); 2392 ptr += off; 2393 2394 r = copy_to_user(buf, ptr, cur_size); 2395 kunmap(adev->gart.pages[p]); 2396 } else 2397 r = clear_user(buf, cur_size); 2398 2399 if (r) 2400 return -EFAULT; 2401 2402 result += cur_size; 2403 buf += cur_size; 2404 *pos += cur_size; 2405 size -= cur_size; 2406 } 2407 2408 return result; 2409 } 2410 2411 static const struct file_operations amdgpu_ttm_gtt_fops = { 2412 .owner = THIS_MODULE, 2413 .read = amdgpu_ttm_gtt_read, 2414 .llseek = default_llseek 2415 }; 2416 2417 #endif 2418 2419 /** 2420 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2421 * 2422 * This function is used to read memory that has been mapped to the 2423 * GPU and the known addresses are not physical addresses but instead 2424 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2425 */ 2426 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2427 size_t size, loff_t *pos) 2428 { 2429 struct amdgpu_device *adev = file_inode(f)->i_private; 2430 struct iommu_domain *dom; 2431 ssize_t result = 0; 2432 int r; 2433 2434 /* retrieve the IOMMU domain if any for this device */ 2435 dom = iommu_get_domain_for_dev(adev->dev); 2436 2437 while (size) { 2438 phys_addr_t addr = *pos & PAGE_MASK; 2439 loff_t off = *pos & ~PAGE_MASK; 2440 size_t bytes = PAGE_SIZE - off; 2441 unsigned long pfn; 2442 struct page *p; 2443 void *ptr; 2444 2445 bytes = bytes < size ? bytes : size; 2446 2447 /* Translate the bus address to a physical address. If 2448 * the domain is NULL it means there is no IOMMU active 2449 * and the address translation is the identity 2450 */ 2451 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2452 2453 pfn = addr >> PAGE_SHIFT; 2454 if (!pfn_valid(pfn)) 2455 return -EPERM; 2456 2457 p = pfn_to_page(pfn); 2458 if (p->mapping != adev->mman.bdev.dev_mapping) 2459 return -EPERM; 2460 2461 ptr = kmap(p); 2462 r = copy_to_user(buf, ptr + off, bytes); 2463 kunmap(p); 2464 if (r) 2465 return -EFAULT; 2466 2467 size -= bytes; 2468 *pos += bytes; 2469 result += bytes; 2470 } 2471 2472 return result; 2473 } 2474 2475 /** 2476 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2477 * 2478 * This function is used to write memory that has been mapped to the 2479 * GPU and the known addresses are not physical addresses but instead 2480 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2481 */ 2482 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2483 size_t size, loff_t *pos) 2484 { 2485 struct amdgpu_device *adev = file_inode(f)->i_private; 2486 struct iommu_domain *dom; 2487 ssize_t result = 0; 2488 int r; 2489 2490 dom = iommu_get_domain_for_dev(adev->dev); 2491 2492 while (size) { 2493 phys_addr_t addr = *pos & PAGE_MASK; 2494 loff_t off = *pos & ~PAGE_MASK; 2495 size_t bytes = PAGE_SIZE - off; 2496 unsigned long pfn; 2497 struct page *p; 2498 void *ptr; 2499 2500 bytes = bytes < size ? bytes : size; 2501 2502 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2503 2504 pfn = addr >> PAGE_SHIFT; 2505 if (!pfn_valid(pfn)) 2506 return -EPERM; 2507 2508 p = pfn_to_page(pfn); 2509 if (p->mapping != adev->mman.bdev.dev_mapping) 2510 return -EPERM; 2511 2512 ptr = kmap(p); 2513 r = copy_from_user(ptr + off, buf, bytes); 2514 kunmap(p); 2515 if (r) 2516 return -EFAULT; 2517 2518 size -= bytes; 2519 *pos += bytes; 2520 result += bytes; 2521 } 2522 2523 return result; 2524 } 2525 2526 static const struct file_operations amdgpu_ttm_iomem_fops = { 2527 .owner = THIS_MODULE, 2528 .read = amdgpu_iomem_read, 2529 .write = amdgpu_iomem_write, 2530 .llseek = default_llseek 2531 }; 2532 2533 static const struct { 2534 char *name; 2535 const struct file_operations *fops; 2536 int domain; 2537 } ttm_debugfs_entries[] = { 2538 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, 2539 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2540 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, 2541 #endif 2542 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, 2543 }; 2544 2545 #endif 2546 2547 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2548 { 2549 #if defined(CONFIG_DEBUG_FS) 2550 unsigned count; 2551 2552 struct drm_minor *minor = adev->ddev->primary; 2553 struct dentry *ent, *root = minor->debugfs_root; 2554 2555 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { 2556 ent = debugfs_create_file( 2557 ttm_debugfs_entries[count].name, 2558 S_IFREG | S_IRUGO, root, 2559 adev, 2560 ttm_debugfs_entries[count].fops); 2561 if (IS_ERR(ent)) 2562 return PTR_ERR(ent); 2563 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) 2564 i_size_write(ent->d_inode, adev->gmc.mc_vram_size); 2565 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) 2566 i_size_write(ent->d_inode, adev->gmc.gart_size); 2567 adev->mman.debugfs_entries[count] = ent; 2568 } 2569 2570 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 2571 2572 #ifdef CONFIG_SWIOTLB 2573 if (!(adev->need_swiotlb && swiotlb_nr_tbl())) 2574 --count; 2575 #endif 2576 2577 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 2578 #else 2579 return 0; 2580 #endif 2581 } 2582