1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <ttm/ttm_bo_api.h> 33 #include <ttm/ttm_bo_driver.h> 34 #include <ttm/ttm_placement.h> 35 #include <ttm/ttm_module.h> 36 #include <ttm/ttm_page_alloc.h> 37 #include <ttm/ttm_memory.h> 38 #include <drm/drmP.h> 39 #include <drm/amdgpu_drm.h> 40 #include <linux/seq_file.h> 41 #include <linux/slab.h> 42 #include <linux/swiotlb.h> 43 #include <linux/swap.h> 44 #include <linux/pagemap.h> 45 #include <linux/debugfs.h> 46 #include "amdgpu.h" 47 #include "bif/bif_4_1_d.h" 48 49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 50 51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); 53 54 55 /* 56 * Global memory. 57 */ 58 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) 59 { 60 return ttm_mem_global_init(ref->object); 61 } 62 63 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) 64 { 65 ttm_mem_global_release(ref->object); 66 } 67 68 int amdgpu_ttm_global_init(struct amdgpu_device *adev) 69 { 70 struct drm_global_reference *global_ref; 71 struct amdgpu_ring *ring; 72 struct amd_sched_rq *rq; 73 int r; 74 75 adev->mman.mem_global_referenced = false; 76 global_ref = &adev->mman.mem_global_ref; 77 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 78 global_ref->size = sizeof(struct ttm_mem_global); 79 global_ref->init = &amdgpu_ttm_mem_global_init; 80 global_ref->release = &amdgpu_ttm_mem_global_release; 81 r = drm_global_item_ref(global_ref); 82 if (r) { 83 DRM_ERROR("Failed setting up TTM memory accounting " 84 "subsystem.\n"); 85 goto error_mem; 86 } 87 88 adev->mman.bo_global_ref.mem_glob = 89 adev->mman.mem_global_ref.object; 90 global_ref = &adev->mman.bo_global_ref.ref; 91 global_ref->global_type = DRM_GLOBAL_TTM_BO; 92 global_ref->size = sizeof(struct ttm_bo_global); 93 global_ref->init = &ttm_bo_global_init; 94 global_ref->release = &ttm_bo_global_release; 95 r = drm_global_item_ref(global_ref); 96 if (r) { 97 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 98 goto error_bo; 99 } 100 101 ring = adev->mman.buffer_funcs_ring; 102 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; 103 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, 104 rq, amdgpu_sched_jobs); 105 if (r) { 106 DRM_ERROR("Failed setting up TTM BO move run queue.\n"); 107 goto error_entity; 108 } 109 110 adev->mman.mem_global_referenced = true; 111 112 return 0; 113 114 error_entity: 115 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 116 error_bo: 117 drm_global_item_unref(&adev->mman.mem_global_ref); 118 error_mem: 119 return r; 120 } 121 122 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) 123 { 124 if (adev->mman.mem_global_referenced) { 125 amd_sched_entity_fini(adev->mman.entity.sched, 126 &adev->mman.entity); 127 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 128 drm_global_item_unref(&adev->mman.mem_global_ref); 129 adev->mman.mem_global_referenced = false; 130 } 131 } 132 133 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 134 { 135 return 0; 136 } 137 138 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 139 struct ttm_mem_type_manager *man) 140 { 141 struct amdgpu_device *adev; 142 143 adev = amdgpu_ttm_adev(bdev); 144 145 switch (type) { 146 case TTM_PL_SYSTEM: 147 /* System memory */ 148 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 149 man->available_caching = TTM_PL_MASK_CACHING; 150 man->default_caching = TTM_PL_FLAG_CACHED; 151 break; 152 case TTM_PL_TT: 153 man->func = &amdgpu_gtt_mgr_func; 154 man->gpu_offset = adev->mc.gtt_start; 155 man->available_caching = TTM_PL_MASK_CACHING; 156 man->default_caching = TTM_PL_FLAG_CACHED; 157 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 158 break; 159 case TTM_PL_VRAM: 160 /* "On-card" video ram */ 161 man->func = &amdgpu_vram_mgr_func; 162 man->gpu_offset = adev->mc.vram_start; 163 man->flags = TTM_MEMTYPE_FLAG_FIXED | 164 TTM_MEMTYPE_FLAG_MAPPABLE; 165 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 166 man->default_caching = TTM_PL_FLAG_WC; 167 break; 168 case AMDGPU_PL_GDS: 169 case AMDGPU_PL_GWS: 170 case AMDGPU_PL_OA: 171 /* On-chip GDS memory*/ 172 man->func = &ttm_bo_manager_func; 173 man->gpu_offset = 0; 174 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; 175 man->available_caching = TTM_PL_FLAG_UNCACHED; 176 man->default_caching = TTM_PL_FLAG_UNCACHED; 177 break; 178 default: 179 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 180 return -EINVAL; 181 } 182 return 0; 183 } 184 185 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 186 struct ttm_placement *placement) 187 { 188 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 189 struct amdgpu_bo *abo; 190 static struct ttm_place placements = { 191 .fpfn = 0, 192 .lpfn = 0, 193 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 194 }; 195 unsigned i; 196 197 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { 198 placement->placement = &placements; 199 placement->busy_placement = &placements; 200 placement->num_placement = 1; 201 placement->num_busy_placement = 1; 202 return; 203 } 204 abo = container_of(bo, struct amdgpu_bo, tbo); 205 switch (bo->mem.mem_type) { 206 case TTM_PL_VRAM: 207 if (adev->mman.buffer_funcs_ring->ready == false) { 208 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 209 } else { 210 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 211 for (i = 0; i < abo->placement.num_placement; ++i) { 212 if (!(abo->placements[i].flags & 213 TTM_PL_FLAG_TT)) 214 continue; 215 216 if (abo->placements[i].lpfn) 217 continue; 218 219 /* set an upper limit to force directly 220 * allocating address space for the BO. 221 */ 222 abo->placements[i].lpfn = 223 adev->mc.gtt_size >> PAGE_SHIFT; 224 } 225 } 226 break; 227 case TTM_PL_TT: 228 default: 229 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 230 } 231 *placement = abo->placement; 232 } 233 234 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 235 { 236 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo); 237 238 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 239 return -EPERM; 240 return drm_vma_node_verify_access(&abo->gem_base.vma_node, 241 filp->private_data); 242 } 243 244 static void amdgpu_move_null(struct ttm_buffer_object *bo, 245 struct ttm_mem_reg *new_mem) 246 { 247 struct ttm_mem_reg *old_mem = &bo->mem; 248 249 BUG_ON(old_mem->mm_node != NULL); 250 *old_mem = *new_mem; 251 new_mem->mm_node = NULL; 252 } 253 254 static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 255 struct drm_mm_node *mm_node, 256 struct ttm_mem_reg *mem, 257 uint64_t *addr) 258 { 259 int r; 260 261 switch (mem->mem_type) { 262 case TTM_PL_TT: 263 r = amdgpu_ttm_bind(bo, mem); 264 if (r) 265 return r; 266 267 case TTM_PL_VRAM: 268 *addr = mm_node->start << PAGE_SHIFT; 269 *addr += bo->bdev->man[mem->mem_type].gpu_offset; 270 break; 271 default: 272 DRM_ERROR("Unknown placement %d\n", mem->mem_type); 273 return -EINVAL; 274 } 275 276 return 0; 277 } 278 279 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 280 bool evict, bool no_wait_gpu, 281 struct ttm_mem_reg *new_mem, 282 struct ttm_mem_reg *old_mem) 283 { 284 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 285 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 286 287 struct drm_mm_node *old_mm, *new_mm; 288 uint64_t old_start, old_size, new_start, new_size; 289 unsigned long num_pages; 290 struct dma_fence *fence = NULL; 291 int r; 292 293 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); 294 295 if (!ring->ready) { 296 DRM_ERROR("Trying to move memory with ring turned off.\n"); 297 return -EINVAL; 298 } 299 300 old_mm = old_mem->mm_node; 301 r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start); 302 if (r) 303 return r; 304 old_size = old_mm->size; 305 306 307 new_mm = new_mem->mm_node; 308 r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start); 309 if (r) 310 return r; 311 new_size = new_mm->size; 312 313 num_pages = new_mem->num_pages; 314 while (num_pages) { 315 unsigned long cur_pages = min(old_size, new_size); 316 struct dma_fence *next; 317 318 r = amdgpu_copy_buffer(ring, old_start, new_start, 319 cur_pages * PAGE_SIZE, 320 bo->resv, &next, false); 321 if (r) 322 goto error; 323 324 dma_fence_put(fence); 325 fence = next; 326 327 num_pages -= cur_pages; 328 if (!num_pages) 329 break; 330 331 old_size -= cur_pages; 332 if (!old_size) { 333 r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem, 334 &old_start); 335 if (r) 336 goto error; 337 old_size = old_mm->size; 338 } else { 339 old_start += cur_pages * PAGE_SIZE; 340 } 341 342 new_size -= cur_pages; 343 if (!new_size) { 344 r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem, 345 &new_start); 346 if (r) 347 goto error; 348 349 new_size = new_mm->size; 350 } else { 351 new_start += cur_pages * PAGE_SIZE; 352 } 353 } 354 355 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 356 dma_fence_put(fence); 357 return r; 358 359 error: 360 if (fence) 361 dma_fence_wait(fence, false); 362 dma_fence_put(fence); 363 return r; 364 } 365 366 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, 367 bool evict, bool interruptible, 368 bool no_wait_gpu, 369 struct ttm_mem_reg *new_mem) 370 { 371 struct amdgpu_device *adev; 372 struct ttm_mem_reg *old_mem = &bo->mem; 373 struct ttm_mem_reg tmp_mem; 374 struct ttm_place placements; 375 struct ttm_placement placement; 376 int r; 377 378 adev = amdgpu_ttm_adev(bo->bdev); 379 tmp_mem = *new_mem; 380 tmp_mem.mm_node = NULL; 381 placement.num_placement = 1; 382 placement.placement = &placements; 383 placement.num_busy_placement = 1; 384 placement.busy_placement = &placements; 385 placements.fpfn = 0; 386 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT; 387 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 388 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 389 interruptible, no_wait_gpu); 390 if (unlikely(r)) { 391 return r; 392 } 393 394 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 395 if (unlikely(r)) { 396 goto out_cleanup; 397 } 398 399 r = ttm_tt_bind(bo->ttm, &tmp_mem); 400 if (unlikely(r)) { 401 goto out_cleanup; 402 } 403 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 404 if (unlikely(r)) { 405 goto out_cleanup; 406 } 407 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); 408 out_cleanup: 409 ttm_bo_mem_put(bo, &tmp_mem); 410 return r; 411 } 412 413 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, 414 bool evict, bool interruptible, 415 bool no_wait_gpu, 416 struct ttm_mem_reg *new_mem) 417 { 418 struct amdgpu_device *adev; 419 struct ttm_mem_reg *old_mem = &bo->mem; 420 struct ttm_mem_reg tmp_mem; 421 struct ttm_placement placement; 422 struct ttm_place placements; 423 int r; 424 425 adev = amdgpu_ttm_adev(bo->bdev); 426 tmp_mem = *new_mem; 427 tmp_mem.mm_node = NULL; 428 placement.num_placement = 1; 429 placement.placement = &placements; 430 placement.num_busy_placement = 1; 431 placement.busy_placement = &placements; 432 placements.fpfn = 0; 433 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT; 434 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 435 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 436 interruptible, no_wait_gpu); 437 if (unlikely(r)) { 438 return r; 439 } 440 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); 441 if (unlikely(r)) { 442 goto out_cleanup; 443 } 444 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 445 if (unlikely(r)) { 446 goto out_cleanup; 447 } 448 out_cleanup: 449 ttm_bo_mem_put(bo, &tmp_mem); 450 return r; 451 } 452 453 static int amdgpu_bo_move(struct ttm_buffer_object *bo, 454 bool evict, bool interruptible, 455 bool no_wait_gpu, 456 struct ttm_mem_reg *new_mem) 457 { 458 struct amdgpu_device *adev; 459 struct amdgpu_bo *abo; 460 struct ttm_mem_reg *old_mem = &bo->mem; 461 int r; 462 463 /* Can't move a pinned BO */ 464 abo = container_of(bo, struct amdgpu_bo, tbo); 465 if (WARN_ON_ONCE(abo->pin_count > 0)) 466 return -EINVAL; 467 468 adev = amdgpu_ttm_adev(bo->bdev); 469 470 /* remember the eviction */ 471 if (evict) 472 atomic64_inc(&adev->num_evictions); 473 474 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 475 amdgpu_move_null(bo, new_mem); 476 return 0; 477 } 478 if ((old_mem->mem_type == TTM_PL_TT && 479 new_mem->mem_type == TTM_PL_SYSTEM) || 480 (old_mem->mem_type == TTM_PL_SYSTEM && 481 new_mem->mem_type == TTM_PL_TT)) { 482 /* bind is enough */ 483 amdgpu_move_null(bo, new_mem); 484 return 0; 485 } 486 if (adev->mman.buffer_funcs == NULL || 487 adev->mman.buffer_funcs_ring == NULL || 488 !adev->mman.buffer_funcs_ring->ready) { 489 /* use memcpy */ 490 goto memcpy; 491 } 492 493 if (old_mem->mem_type == TTM_PL_VRAM && 494 new_mem->mem_type == TTM_PL_SYSTEM) { 495 r = amdgpu_move_vram_ram(bo, evict, interruptible, 496 no_wait_gpu, new_mem); 497 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 498 new_mem->mem_type == TTM_PL_VRAM) { 499 r = amdgpu_move_ram_vram(bo, evict, interruptible, 500 no_wait_gpu, new_mem); 501 } else { 502 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 503 } 504 505 if (r) { 506 memcpy: 507 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); 508 if (r) { 509 return r; 510 } 511 } 512 513 /* update statistics */ 514 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 515 return 0; 516 } 517 518 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 519 { 520 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 521 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 522 523 mem->bus.addr = NULL; 524 mem->bus.offset = 0; 525 mem->bus.size = mem->num_pages << PAGE_SHIFT; 526 mem->bus.base = 0; 527 mem->bus.is_iomem = false; 528 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 529 return -EINVAL; 530 switch (mem->mem_type) { 531 case TTM_PL_SYSTEM: 532 /* system memory */ 533 return 0; 534 case TTM_PL_TT: 535 break; 536 case TTM_PL_VRAM: 537 mem->bus.offset = mem->start << PAGE_SHIFT; 538 /* check if it's visible */ 539 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) 540 return -EINVAL; 541 mem->bus.base = adev->mc.aper_base; 542 mem->bus.is_iomem = true; 543 #ifdef __alpha__ 544 /* 545 * Alpha: use bus.addr to hold the ioremap() return, 546 * so we can modify bus.base below. 547 */ 548 if (mem->placement & TTM_PL_FLAG_WC) 549 mem->bus.addr = 550 ioremap_wc(mem->bus.base + mem->bus.offset, 551 mem->bus.size); 552 else 553 mem->bus.addr = 554 ioremap_nocache(mem->bus.base + mem->bus.offset, 555 mem->bus.size); 556 557 /* 558 * Alpha: Use just the bus offset plus 559 * the hose/domain memory base for bus.base. 560 * It then can be used to build PTEs for VRAM 561 * access, as done in ttm_bo_vm_fault(). 562 */ 563 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 564 adev->ddev->hose->dense_mem_base; 565 #endif 566 break; 567 default: 568 return -EINVAL; 569 } 570 return 0; 571 } 572 573 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 574 { 575 } 576 577 /* 578 * TTM backend functions. 579 */ 580 struct amdgpu_ttm_gup_task_list { 581 struct list_head list; 582 struct task_struct *task; 583 }; 584 585 struct amdgpu_ttm_tt { 586 struct ttm_dma_tt ttm; 587 struct amdgpu_device *adev; 588 u64 offset; 589 uint64_t userptr; 590 struct mm_struct *usermm; 591 uint32_t userflags; 592 spinlock_t guptasklock; 593 struct list_head guptasks; 594 atomic_t mmu_invalidations; 595 struct list_head list; 596 }; 597 598 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) 599 { 600 struct amdgpu_ttm_tt *gtt = (void *)ttm; 601 unsigned int flags = 0; 602 unsigned pinned = 0; 603 int r; 604 605 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 606 flags |= FOLL_WRITE; 607 608 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { 609 /* check that we only use anonymous memory 610 to prevent problems with writeback */ 611 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 612 struct vm_area_struct *vma; 613 614 vma = find_vma(gtt->usermm, gtt->userptr); 615 if (!vma || vma->vm_file || vma->vm_end < end) 616 return -EPERM; 617 } 618 619 do { 620 unsigned num_pages = ttm->num_pages - pinned; 621 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 622 struct page **p = pages + pinned; 623 struct amdgpu_ttm_gup_task_list guptask; 624 625 guptask.task = current; 626 spin_lock(>t->guptasklock); 627 list_add(&guptask.list, >t->guptasks); 628 spin_unlock(>t->guptasklock); 629 630 r = get_user_pages(userptr, num_pages, flags, p, NULL); 631 632 spin_lock(>t->guptasklock); 633 list_del(&guptask.list); 634 spin_unlock(>t->guptasklock); 635 636 if (r < 0) 637 goto release_pages; 638 639 pinned += r; 640 641 } while (pinned < ttm->num_pages); 642 643 return 0; 644 645 release_pages: 646 release_pages(pages, pinned, 0); 647 return r; 648 } 649 650 /* prepare the sg table with the user pages */ 651 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 652 { 653 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 654 struct amdgpu_ttm_tt *gtt = (void *)ttm; 655 unsigned nents; 656 int r; 657 658 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 659 enum dma_data_direction direction = write ? 660 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 661 662 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 663 ttm->num_pages << PAGE_SHIFT, 664 GFP_KERNEL); 665 if (r) 666 goto release_sg; 667 668 r = -ENOMEM; 669 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 670 if (nents != ttm->sg->nents) 671 goto release_sg; 672 673 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 674 gtt->ttm.dma_address, ttm->num_pages); 675 676 return 0; 677 678 release_sg: 679 kfree(ttm->sg); 680 return r; 681 } 682 683 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 684 { 685 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 686 struct amdgpu_ttm_tt *gtt = (void *)ttm; 687 struct sg_page_iter sg_iter; 688 689 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 690 enum dma_data_direction direction = write ? 691 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 692 693 /* double check that we don't free the table twice */ 694 if (!ttm->sg->sgl) 695 return; 696 697 /* free the sg table and pages again */ 698 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 699 700 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { 701 struct page *page = sg_page_iter_page(&sg_iter); 702 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 703 set_page_dirty(page); 704 705 mark_page_accessed(page); 706 put_page(page); 707 } 708 709 sg_free_table(ttm->sg); 710 } 711 712 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 713 struct ttm_mem_reg *bo_mem) 714 { 715 struct amdgpu_ttm_tt *gtt = (void*)ttm; 716 int r; 717 718 if (gtt->userptr) { 719 r = amdgpu_ttm_tt_pin_userptr(ttm); 720 if (r) { 721 DRM_ERROR("failed to pin userptr\n"); 722 return r; 723 } 724 } 725 if (!ttm->num_pages) { 726 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 727 ttm->num_pages, bo_mem, ttm); 728 } 729 730 if (bo_mem->mem_type == AMDGPU_PL_GDS || 731 bo_mem->mem_type == AMDGPU_PL_GWS || 732 bo_mem->mem_type == AMDGPU_PL_OA) 733 return -EINVAL; 734 735 return 0; 736 } 737 738 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) 739 { 740 struct amdgpu_ttm_tt *gtt = (void *)ttm; 741 742 return gtt && !list_empty(>t->list); 743 } 744 745 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) 746 { 747 struct ttm_tt *ttm = bo->ttm; 748 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 749 uint32_t flags; 750 int r; 751 752 if (!ttm || amdgpu_ttm_is_bound(ttm)) 753 return 0; 754 755 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo, 756 NULL, bo_mem); 757 if (r) { 758 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r); 759 return r; 760 } 761 762 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 763 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 764 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, 765 ttm->pages, gtt->ttm.dma_address, flags); 766 767 if (r) { 768 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 769 ttm->num_pages, gtt->offset); 770 return r; 771 } 772 spin_lock(>t->adev->gtt_list_lock); 773 list_add_tail(>t->list, >t->adev->gtt_list); 774 spin_unlock(>t->adev->gtt_list_lock); 775 return 0; 776 } 777 778 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) 779 { 780 struct amdgpu_ttm_tt *gtt, *tmp; 781 struct ttm_mem_reg bo_mem; 782 uint32_t flags; 783 int r; 784 785 bo_mem.mem_type = TTM_PL_TT; 786 spin_lock(&adev->gtt_list_lock); 787 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) { 788 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem); 789 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, 790 gtt->ttm.ttm.pages, gtt->ttm.dma_address, 791 flags); 792 if (r) { 793 spin_unlock(&adev->gtt_list_lock); 794 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 795 gtt->ttm.ttm.num_pages, gtt->offset); 796 return r; 797 } 798 } 799 spin_unlock(&adev->gtt_list_lock); 800 return 0; 801 } 802 803 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 804 { 805 struct amdgpu_ttm_tt *gtt = (void *)ttm; 806 807 if (gtt->userptr) 808 amdgpu_ttm_tt_unpin_userptr(ttm); 809 810 if (!amdgpu_ttm_is_bound(ttm)) 811 return 0; 812 813 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 814 if (gtt->adev->gart.ready) 815 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); 816 817 spin_lock(>t->adev->gtt_list_lock); 818 list_del_init(>t->list); 819 spin_unlock(>t->adev->gtt_list_lock); 820 821 return 0; 822 } 823 824 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 825 { 826 struct amdgpu_ttm_tt *gtt = (void *)ttm; 827 828 ttm_dma_tt_fini(>t->ttm); 829 kfree(gtt); 830 } 831 832 static struct ttm_backend_func amdgpu_backend_func = { 833 .bind = &amdgpu_ttm_backend_bind, 834 .unbind = &amdgpu_ttm_backend_unbind, 835 .destroy = &amdgpu_ttm_backend_destroy, 836 }; 837 838 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, 839 unsigned long size, uint32_t page_flags, 840 struct page *dummy_read_page) 841 { 842 struct amdgpu_device *adev; 843 struct amdgpu_ttm_tt *gtt; 844 845 adev = amdgpu_ttm_adev(bdev); 846 847 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 848 if (gtt == NULL) { 849 return NULL; 850 } 851 gtt->ttm.ttm.func = &amdgpu_backend_func; 852 gtt->adev = adev; 853 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 854 kfree(gtt); 855 return NULL; 856 } 857 INIT_LIST_HEAD(>t->list); 858 return >t->ttm.ttm; 859 } 860 861 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) 862 { 863 struct amdgpu_device *adev; 864 struct amdgpu_ttm_tt *gtt = (void *)ttm; 865 unsigned i; 866 int r; 867 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 868 869 if (ttm->state != tt_unpopulated) 870 return 0; 871 872 if (gtt && gtt->userptr) { 873 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 874 if (!ttm->sg) 875 return -ENOMEM; 876 877 ttm->page_flags |= TTM_PAGE_FLAG_SG; 878 ttm->state = tt_unbound; 879 return 0; 880 } 881 882 if (slave && ttm->sg) { 883 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 884 gtt->ttm.dma_address, ttm->num_pages); 885 ttm->state = tt_unbound; 886 return 0; 887 } 888 889 adev = amdgpu_ttm_adev(ttm->bdev); 890 891 #ifdef CONFIG_SWIOTLB 892 if (swiotlb_nr_tbl()) { 893 return ttm_dma_populate(>t->ttm, adev->dev); 894 } 895 #endif 896 897 r = ttm_pool_populate(ttm); 898 if (r) { 899 return r; 900 } 901 902 for (i = 0; i < ttm->num_pages; i++) { 903 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], 904 0, PAGE_SIZE, 905 PCI_DMA_BIDIRECTIONAL); 906 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { 907 while (i--) { 908 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 909 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 910 gtt->ttm.dma_address[i] = 0; 911 } 912 ttm_pool_unpopulate(ttm); 913 return -EFAULT; 914 } 915 } 916 return 0; 917 } 918 919 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 920 { 921 struct amdgpu_device *adev; 922 struct amdgpu_ttm_tt *gtt = (void *)ttm; 923 unsigned i; 924 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 925 926 if (gtt && gtt->userptr) { 927 kfree(ttm->sg); 928 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 929 return; 930 } 931 932 if (slave) 933 return; 934 935 adev = amdgpu_ttm_adev(ttm->bdev); 936 937 #ifdef CONFIG_SWIOTLB 938 if (swiotlb_nr_tbl()) { 939 ttm_dma_unpopulate(>t->ttm, adev->dev); 940 return; 941 } 942 #endif 943 944 for (i = 0; i < ttm->num_pages; i++) { 945 if (gtt->ttm.dma_address[i]) { 946 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 947 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 948 } 949 } 950 951 ttm_pool_unpopulate(ttm); 952 } 953 954 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 955 uint32_t flags) 956 { 957 struct amdgpu_ttm_tt *gtt = (void *)ttm; 958 959 if (gtt == NULL) 960 return -EINVAL; 961 962 gtt->userptr = addr; 963 gtt->usermm = current->mm; 964 gtt->userflags = flags; 965 spin_lock_init(>t->guptasklock); 966 INIT_LIST_HEAD(>t->guptasks); 967 atomic_set(>t->mmu_invalidations, 0); 968 969 return 0; 970 } 971 972 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 973 { 974 struct amdgpu_ttm_tt *gtt = (void *)ttm; 975 976 if (gtt == NULL) 977 return NULL; 978 979 return gtt->usermm; 980 } 981 982 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 983 unsigned long end) 984 { 985 struct amdgpu_ttm_tt *gtt = (void *)ttm; 986 struct amdgpu_ttm_gup_task_list *entry; 987 unsigned long size; 988 989 if (gtt == NULL || !gtt->userptr) 990 return false; 991 992 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 993 if (gtt->userptr > end || gtt->userptr + size <= start) 994 return false; 995 996 spin_lock(>t->guptasklock); 997 list_for_each_entry(entry, >t->guptasks, list) { 998 if (entry->task == current) { 999 spin_unlock(>t->guptasklock); 1000 return false; 1001 } 1002 } 1003 spin_unlock(>t->guptasklock); 1004 1005 atomic_inc(>t->mmu_invalidations); 1006 1007 return true; 1008 } 1009 1010 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1011 int *last_invalidated) 1012 { 1013 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1014 int prev_invalidated = *last_invalidated; 1015 1016 *last_invalidated = atomic_read(>t->mmu_invalidations); 1017 return prev_invalidated != *last_invalidated; 1018 } 1019 1020 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1021 { 1022 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1023 1024 if (gtt == NULL) 1025 return false; 1026 1027 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1028 } 1029 1030 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1031 struct ttm_mem_reg *mem) 1032 { 1033 uint32_t flags = 0; 1034 1035 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1036 flags |= AMDGPU_PTE_VALID; 1037 1038 if (mem && mem->mem_type == TTM_PL_TT) { 1039 flags |= AMDGPU_PTE_SYSTEM; 1040 1041 if (ttm->caching_state == tt_cached) 1042 flags |= AMDGPU_PTE_SNOOPED; 1043 } 1044 1045 if (adev->asic_type >= CHIP_TONGA) 1046 flags |= AMDGPU_PTE_EXECUTABLE; 1047 1048 flags |= AMDGPU_PTE_READABLE; 1049 1050 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1051 flags |= AMDGPU_PTE_WRITEABLE; 1052 1053 return flags; 1054 } 1055 1056 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo) 1057 { 1058 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1059 unsigned i, j; 1060 1061 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { 1062 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i]; 1063 1064 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) 1065 if (&tbo->lru == lru->lru[j]) 1066 lru->lru[j] = tbo->lru.prev; 1067 1068 if (&tbo->swap == lru->swap_lru) 1069 lru->swap_lru = tbo->swap.prev; 1070 } 1071 } 1072 1073 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo) 1074 { 1075 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1076 unsigned log2_size = min(ilog2(tbo->num_pages), 1077 AMDGPU_TTM_LRU_SIZE - 1); 1078 1079 return &adev->mman.log2_size[log2_size]; 1080 } 1081 1082 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo) 1083 { 1084 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo); 1085 struct list_head *res = lru->lru[tbo->mem.mem_type]; 1086 1087 lru->lru[tbo->mem.mem_type] = &tbo->lru; 1088 while ((++lru)->lru[tbo->mem.mem_type] == res) 1089 lru->lru[tbo->mem.mem_type] = &tbo->lru; 1090 1091 return res; 1092 } 1093 1094 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo) 1095 { 1096 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo); 1097 struct list_head *res = lru->swap_lru; 1098 1099 lru->swap_lru = &tbo->swap; 1100 while ((++lru)->swap_lru == res) 1101 lru->swap_lru = &tbo->swap; 1102 1103 return res; 1104 } 1105 1106 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1107 const struct ttm_place *place) 1108 { 1109 if (bo->mem.mem_type == TTM_PL_VRAM && 1110 bo->mem.start == AMDGPU_BO_INVALID_OFFSET) { 1111 unsigned long num_pages = bo->mem.num_pages; 1112 struct drm_mm_node *node = bo->mem.mm_node; 1113 1114 /* Check each drm MM node individually */ 1115 while (num_pages) { 1116 if (place->fpfn < (node->start + node->size) && 1117 !(place->lpfn && place->lpfn <= node->start)) 1118 return true; 1119 1120 num_pages -= node->size; 1121 ++node; 1122 } 1123 1124 return false; 1125 } 1126 1127 return ttm_bo_eviction_valuable(bo, place); 1128 } 1129 1130 static struct ttm_bo_driver amdgpu_bo_driver = { 1131 .ttm_tt_create = &amdgpu_ttm_tt_create, 1132 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1133 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1134 .invalidate_caches = &amdgpu_invalidate_caches, 1135 .init_mem_type = &amdgpu_init_mem_type, 1136 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1137 .evict_flags = &amdgpu_evict_flags, 1138 .move = &amdgpu_bo_move, 1139 .verify_access = &amdgpu_verify_access, 1140 .move_notify = &amdgpu_bo_move_notify, 1141 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1142 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1143 .io_mem_free = &amdgpu_ttm_io_mem_free, 1144 .lru_removal = &amdgpu_ttm_lru_removal, 1145 .lru_tail = &amdgpu_ttm_lru_tail, 1146 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail, 1147 }; 1148 1149 int amdgpu_ttm_init(struct amdgpu_device *adev) 1150 { 1151 unsigned i, j; 1152 int r; 1153 1154 /* No others user of address space so set it to 0 */ 1155 r = ttm_bo_device_init(&adev->mman.bdev, 1156 adev->mman.bo_global_ref.ref.object, 1157 &amdgpu_bo_driver, 1158 adev->ddev->anon_inode->i_mapping, 1159 DRM_FILE_PAGE_OFFSET, 1160 adev->need_dma32); 1161 if (r) { 1162 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1163 return r; 1164 } 1165 1166 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { 1167 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i]; 1168 1169 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) 1170 lru->lru[j] = &adev->mman.bdev.man[j].lru; 1171 lru->swap_lru = &adev->mman.bdev.glob->swap_lru; 1172 } 1173 1174 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) 1175 adev->mman.guard.lru[j] = NULL; 1176 adev->mman.guard.swap_lru = NULL; 1177 1178 adev->mman.initialized = true; 1179 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1180 adev->mc.real_vram_size >> PAGE_SHIFT); 1181 if (r) { 1182 DRM_ERROR("Failed initializing VRAM heap.\n"); 1183 return r; 1184 } 1185 /* Change the size here instead of the init above so only lpfn is affected */ 1186 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 1187 1188 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, 1189 AMDGPU_GEM_DOMAIN_VRAM, 1190 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1191 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1192 NULL, NULL, &adev->stollen_vga_memory); 1193 if (r) { 1194 return r; 1195 } 1196 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1197 if (r) 1198 return r; 1199 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); 1200 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1201 if (r) { 1202 amdgpu_bo_unref(&adev->stollen_vga_memory); 1203 return r; 1204 } 1205 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1206 (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); 1207 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, 1208 adev->mc.gtt_size >> PAGE_SHIFT); 1209 if (r) { 1210 DRM_ERROR("Failed initializing GTT heap.\n"); 1211 return r; 1212 } 1213 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1214 (unsigned)(adev->mc.gtt_size / (1024 * 1024))); 1215 1216 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; 1217 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; 1218 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; 1219 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; 1220 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; 1221 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; 1222 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; 1223 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; 1224 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; 1225 /* GDS Memory */ 1226 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 1227 adev->gds.mem.total_size >> PAGE_SHIFT); 1228 if (r) { 1229 DRM_ERROR("Failed initializing GDS heap.\n"); 1230 return r; 1231 } 1232 1233 /* GWS */ 1234 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 1235 adev->gds.gws.total_size >> PAGE_SHIFT); 1236 if (r) { 1237 DRM_ERROR("Failed initializing gws heap.\n"); 1238 return r; 1239 } 1240 1241 /* OA */ 1242 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 1243 adev->gds.oa.total_size >> PAGE_SHIFT); 1244 if (r) { 1245 DRM_ERROR("Failed initializing oa heap.\n"); 1246 return r; 1247 } 1248 1249 r = amdgpu_ttm_debugfs_init(adev); 1250 if (r) { 1251 DRM_ERROR("Failed to init debugfs\n"); 1252 return r; 1253 } 1254 return 0; 1255 } 1256 1257 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1258 { 1259 int r; 1260 1261 if (!adev->mman.initialized) 1262 return; 1263 amdgpu_ttm_debugfs_fini(adev); 1264 if (adev->stollen_vga_memory) { 1265 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1266 if (r == 0) { 1267 amdgpu_bo_unpin(adev->stollen_vga_memory); 1268 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1269 } 1270 amdgpu_bo_unref(&adev->stollen_vga_memory); 1271 } 1272 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 1273 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 1274 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 1275 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 1276 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 1277 ttm_bo_device_release(&adev->mman.bdev); 1278 amdgpu_gart_fini(adev); 1279 amdgpu_ttm_global_fini(adev); 1280 adev->mman.initialized = false; 1281 DRM_INFO("amdgpu: ttm finalized\n"); 1282 } 1283 1284 /* this should only be called at bootup or when userspace 1285 * isn't running */ 1286 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) 1287 { 1288 struct ttm_mem_type_manager *man; 1289 1290 if (!adev->mman.initialized) 1291 return; 1292 1293 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 1294 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1295 man->size = size >> PAGE_SHIFT; 1296 } 1297 1298 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1299 { 1300 struct drm_file *file_priv; 1301 struct amdgpu_device *adev; 1302 1303 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 1304 return -EINVAL; 1305 1306 file_priv = filp->private_data; 1307 adev = file_priv->minor->dev->dev_private; 1308 if (adev == NULL) 1309 return -EINVAL; 1310 1311 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1312 } 1313 1314 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 1315 uint64_t src_offset, 1316 uint64_t dst_offset, 1317 uint32_t byte_count, 1318 struct reservation_object *resv, 1319 struct dma_fence **fence, bool direct_submit) 1320 { 1321 struct amdgpu_device *adev = ring->adev; 1322 struct amdgpu_job *job; 1323 1324 uint32_t max_bytes; 1325 unsigned num_loops, num_dw; 1326 unsigned i; 1327 int r; 1328 1329 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1330 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1331 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; 1332 1333 /* for IB padding */ 1334 while (num_dw & 0x7) 1335 num_dw++; 1336 1337 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1338 if (r) 1339 return r; 1340 1341 if (resv) { 1342 r = amdgpu_sync_resv(adev, &job->sync, resv, 1343 AMDGPU_FENCE_OWNER_UNDEFINED); 1344 if (r) { 1345 DRM_ERROR("sync failed (%d).\n", r); 1346 goto error_free; 1347 } 1348 } 1349 1350 for (i = 0; i < num_loops; i++) { 1351 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1352 1353 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1354 dst_offset, cur_size_in_bytes); 1355 1356 src_offset += cur_size_in_bytes; 1357 dst_offset += cur_size_in_bytes; 1358 byte_count -= cur_size_in_bytes; 1359 } 1360 1361 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1362 WARN_ON(job->ibs[0].length_dw > num_dw); 1363 if (direct_submit) { 1364 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, 1365 NULL, NULL, fence); 1366 job->fence = dma_fence_get(*fence); 1367 if (r) 1368 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1369 amdgpu_job_free(job); 1370 } else { 1371 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1372 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1373 if (r) 1374 goto error_free; 1375 } 1376 1377 return r; 1378 1379 error_free: 1380 amdgpu_job_free(job); 1381 return r; 1382 } 1383 1384 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1385 uint32_t src_data, 1386 struct reservation_object *resv, 1387 struct dma_fence **fence) 1388 { 1389 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1390 struct amdgpu_job *job; 1391 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1392 1393 uint32_t max_bytes, byte_count; 1394 uint64_t dst_offset; 1395 unsigned int num_loops, num_dw; 1396 unsigned int i; 1397 int r; 1398 1399 byte_count = bo->tbo.num_pages << PAGE_SHIFT; 1400 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1401 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1402 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1403 1404 /* for IB padding */ 1405 while (num_dw & 0x7) 1406 num_dw++; 1407 1408 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1409 if (r) 1410 return r; 1411 1412 if (resv) { 1413 r = amdgpu_sync_resv(adev, &job->sync, resv, 1414 AMDGPU_FENCE_OWNER_UNDEFINED); 1415 if (r) { 1416 DRM_ERROR("sync failed (%d).\n", r); 1417 goto error_free; 1418 } 1419 } 1420 1421 dst_offset = bo->tbo.mem.start << PAGE_SHIFT; 1422 for (i = 0; i < num_loops; i++) { 1423 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1424 1425 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 1426 dst_offset, cur_size_in_bytes); 1427 1428 dst_offset += cur_size_in_bytes; 1429 byte_count -= cur_size_in_bytes; 1430 } 1431 1432 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1433 WARN_ON(job->ibs[0].length_dw > num_dw); 1434 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1435 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1436 if (r) 1437 goto error_free; 1438 1439 return 0; 1440 1441 error_free: 1442 amdgpu_job_free(job); 1443 return r; 1444 } 1445 1446 #if defined(CONFIG_DEBUG_FS) 1447 1448 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 1449 { 1450 struct drm_info_node *node = (struct drm_info_node *)m->private; 1451 unsigned ttm_pl = *(int *)node->info_ent->data; 1452 struct drm_device *dev = node->minor->dev; 1453 struct amdgpu_device *adev = dev->dev_private; 1454 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; 1455 int ret; 1456 struct ttm_bo_global *glob = adev->mman.bdev.glob; 1457 1458 spin_lock(&glob->lru_lock); 1459 ret = drm_mm_dump_table(m, mm); 1460 spin_unlock(&glob->lru_lock); 1461 if (ttm_pl == TTM_PL_VRAM) 1462 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", 1463 adev->mman.bdev.man[ttm_pl].size, 1464 (u64)atomic64_read(&adev->vram_usage) >> 20, 1465 (u64)atomic64_read(&adev->vram_vis_usage) >> 20); 1466 return ret; 1467 } 1468 1469 static int ttm_pl_vram = TTM_PL_VRAM; 1470 static int ttm_pl_tt = TTM_PL_TT; 1471 1472 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 1473 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, 1474 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, 1475 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 1476 #ifdef CONFIG_SWIOTLB 1477 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 1478 #endif 1479 }; 1480 1481 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 1482 size_t size, loff_t *pos) 1483 { 1484 struct amdgpu_device *adev = f->f_inode->i_private; 1485 ssize_t result = 0; 1486 int r; 1487 1488 if (size & 0x3 || *pos & 0x3) 1489 return -EINVAL; 1490 1491 while (size) { 1492 unsigned long flags; 1493 uint32_t value; 1494 1495 if (*pos >= adev->mc.mc_vram_size) 1496 return result; 1497 1498 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1499 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 1500 WREG32(mmMM_INDEX_HI, *pos >> 31); 1501 value = RREG32(mmMM_DATA); 1502 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1503 1504 r = put_user(value, (uint32_t *)buf); 1505 if (r) 1506 return r; 1507 1508 result += 4; 1509 buf += 4; 1510 *pos += 4; 1511 size -= 4; 1512 } 1513 1514 return result; 1515 } 1516 1517 static const struct file_operations amdgpu_ttm_vram_fops = { 1518 .owner = THIS_MODULE, 1519 .read = amdgpu_ttm_vram_read, 1520 .llseek = default_llseek 1521 }; 1522 1523 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1524 1525 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 1526 size_t size, loff_t *pos) 1527 { 1528 struct amdgpu_device *adev = f->f_inode->i_private; 1529 ssize_t result = 0; 1530 int r; 1531 1532 while (size) { 1533 loff_t p = *pos / PAGE_SIZE; 1534 unsigned off = *pos & ~PAGE_MASK; 1535 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1536 struct page *page; 1537 void *ptr; 1538 1539 if (p >= adev->gart.num_cpu_pages) 1540 return result; 1541 1542 page = adev->gart.pages[p]; 1543 if (page) { 1544 ptr = kmap(page); 1545 ptr += off; 1546 1547 r = copy_to_user(buf, ptr, cur_size); 1548 kunmap(adev->gart.pages[p]); 1549 } else 1550 r = clear_user(buf, cur_size); 1551 1552 if (r) 1553 return -EFAULT; 1554 1555 result += cur_size; 1556 buf += cur_size; 1557 *pos += cur_size; 1558 size -= cur_size; 1559 } 1560 1561 return result; 1562 } 1563 1564 static const struct file_operations amdgpu_ttm_gtt_fops = { 1565 .owner = THIS_MODULE, 1566 .read = amdgpu_ttm_gtt_read, 1567 .llseek = default_llseek 1568 }; 1569 1570 #endif 1571 1572 #endif 1573 1574 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 1575 { 1576 #if defined(CONFIG_DEBUG_FS) 1577 unsigned count; 1578 1579 struct drm_minor *minor = adev->ddev->primary; 1580 struct dentry *ent, *root = minor->debugfs_root; 1581 1582 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, 1583 adev, &amdgpu_ttm_vram_fops); 1584 if (IS_ERR(ent)) 1585 return PTR_ERR(ent); 1586 i_size_write(ent->d_inode, adev->mc.mc_vram_size); 1587 adev->mman.vram = ent; 1588 1589 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1590 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, 1591 adev, &amdgpu_ttm_gtt_fops); 1592 if (IS_ERR(ent)) 1593 return PTR_ERR(ent); 1594 i_size_write(ent->d_inode, adev->mc.gtt_size); 1595 adev->mman.gtt = ent; 1596 1597 #endif 1598 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 1599 1600 #ifdef CONFIG_SWIOTLB 1601 if (!swiotlb_nr_tbl()) 1602 --count; 1603 #endif 1604 1605 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 1606 #else 1607 1608 return 0; 1609 #endif 1610 } 1611 1612 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) 1613 { 1614 #if defined(CONFIG_DEBUG_FS) 1615 1616 debugfs_remove(adev->mman.vram); 1617 adev->mman.vram = NULL; 1618 1619 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1620 debugfs_remove(adev->mman.gtt); 1621 adev->mman.gtt = NULL; 1622 #endif 1623 1624 #endif 1625 } 1626 1627 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev) 1628 { 1629 return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object); 1630 } 1631