1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 50 #include <drm/amdgpu_drm.h> 51 52 #include "amdgpu.h" 53 #include "amdgpu_object.h" 54 #include "amdgpu_trace.h" 55 #include "amdgpu_amdkfd.h" 56 #include "amdgpu_sdma.h" 57 #include "amdgpu_ras.h" 58 #include "amdgpu_atomfirmware.h" 59 #include "bif/bif_4_1_d.h" 60 61 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 62 63 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, 64 struct ttm_tt *ttm, 65 struct ttm_resource *bo_mem); 66 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, 67 struct ttm_tt *ttm); 68 69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 70 unsigned int type, 71 uint64_t size_in_page) 72 { 73 return ttm_range_man_init(&adev->mman.bdev, type, 74 false, size_in_page); 75 } 76 77 /** 78 * amdgpu_evict_flags - Compute placement flags 79 * 80 * @bo: The buffer object to evict 81 * @placement: Possible destination(s) for evicted BO 82 * 83 * Fill in placement data when ttm_bo_evict() is called 84 */ 85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 86 struct ttm_placement *placement) 87 { 88 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 89 struct amdgpu_bo *abo; 90 static const struct ttm_place placements = { 91 .fpfn = 0, 92 .lpfn = 0, 93 .mem_type = TTM_PL_SYSTEM, 94 .flags = 0 95 }; 96 97 /* Don't handle scatter gather BOs */ 98 if (bo->type == ttm_bo_type_sg) { 99 placement->num_placement = 0; 100 placement->num_busy_placement = 0; 101 return; 102 } 103 104 /* Object isn't an AMDGPU object so ignore */ 105 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 106 placement->placement = &placements; 107 placement->busy_placement = &placements; 108 placement->num_placement = 1; 109 placement->num_busy_placement = 1; 110 return; 111 } 112 113 abo = ttm_to_amdgpu_bo(bo); 114 switch (bo->mem.mem_type) { 115 case AMDGPU_PL_GDS: 116 case AMDGPU_PL_GWS: 117 case AMDGPU_PL_OA: 118 placement->num_placement = 0; 119 placement->num_busy_placement = 0; 120 return; 121 122 case TTM_PL_VRAM: 123 if (!adev->mman.buffer_funcs_enabled) { 124 /* Move to system memory */ 125 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 126 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 127 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 128 amdgpu_bo_in_cpu_visible_vram(abo)) { 129 130 /* Try evicting to the CPU inaccessible part of VRAM 131 * first, but only set GTT as busy placement, so this 132 * BO will be evicted to GTT rather than causing other 133 * BOs to be evicted from VRAM 134 */ 135 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 136 AMDGPU_GEM_DOMAIN_GTT); 137 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 138 abo->placements[0].lpfn = 0; 139 abo->placement.busy_placement = &abo->placements[1]; 140 abo->placement.num_busy_placement = 1; 141 } else { 142 /* Move to GTT memory */ 143 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 144 } 145 break; 146 case TTM_PL_TT: 147 default: 148 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 149 break; 150 } 151 *placement = abo->placement; 152 } 153 154 /** 155 * amdgpu_verify_access - Verify access for a mmap call 156 * 157 * @bo: The buffer object to map 158 * @filp: The file pointer from the process performing the mmap 159 * 160 * This is called by ttm_bo_mmap() to verify whether a process 161 * has the right to mmap a BO to their process space. 162 */ 163 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 164 { 165 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 166 167 /* 168 * Don't verify access for KFD BOs. They don't have a GEM 169 * object associated with them. 170 */ 171 if (abo->kfd_bo) 172 return 0; 173 174 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 175 return -EPERM; 176 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 177 filp->private_data); 178 } 179 180 /** 181 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. 182 * 183 * @bo: The bo to assign the memory to. 184 * @mm_node: Memory manager node for drm allocator. 185 * @mem: The region where the bo resides. 186 * 187 */ 188 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 189 struct drm_mm_node *mm_node, 190 struct ttm_resource *mem) 191 { 192 uint64_t addr = 0; 193 194 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { 195 addr = mm_node->start << PAGE_SHIFT; 196 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev), 197 mem->mem_type); 198 } 199 return addr; 200 } 201 202 /** 203 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to 204 * @offset. It also modifies the offset to be within the drm_mm_node returned 205 * 206 * @mem: The region where the bo resides. 207 * @offset: The offset that drm_mm_node is used for finding. 208 * 209 */ 210 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem, 211 uint64_t *offset) 212 { 213 struct drm_mm_node *mm_node = mem->mm_node; 214 215 while (*offset >= (mm_node->size << PAGE_SHIFT)) { 216 *offset -= (mm_node->size << PAGE_SHIFT); 217 ++mm_node; 218 } 219 return mm_node; 220 } 221 222 /** 223 * amdgpu_ttm_map_buffer - Map memory into the GART windows 224 * @bo: buffer object to map 225 * @mem: memory object to map 226 * @mm_node: drm_mm node object to map 227 * @num_pages: number of pages to map 228 * @offset: offset into @mm_node where to start 229 * @window: which GART window to use 230 * @ring: DMA ring to use for the copy 231 * @tmz: if we should setup a TMZ enabled mapping 232 * @addr: resulting address inside the MC address space 233 * 234 * Setup one of the GART windows to access a specific piece of memory or return 235 * the physical address for local memory. 236 */ 237 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 238 struct ttm_resource *mem, 239 struct drm_mm_node *mm_node, 240 unsigned num_pages, uint64_t offset, 241 unsigned window, struct amdgpu_ring *ring, 242 bool tmz, uint64_t *addr) 243 { 244 struct amdgpu_device *adev = ring->adev; 245 struct amdgpu_job *job; 246 unsigned num_dw, num_bytes; 247 struct dma_fence *fence; 248 uint64_t src_addr, dst_addr; 249 void *cpu_addr; 250 uint64_t flags; 251 unsigned int i; 252 int r; 253 254 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 255 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 256 257 /* Map only what can't be accessed directly */ 258 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 259 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; 260 return 0; 261 } 262 263 *addr = adev->gmc.gart_start; 264 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 265 AMDGPU_GPU_PAGE_SIZE; 266 *addr += offset & ~PAGE_MASK; 267 268 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 269 num_bytes = num_pages * 8; 270 271 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 272 AMDGPU_IB_POOL_DELAYED, &job); 273 if (r) 274 return r; 275 276 src_addr = num_dw * 4; 277 src_addr += job->ibs[0].gpu_addr; 278 279 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 280 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 281 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 282 dst_addr, num_bytes, false); 283 284 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 285 WARN_ON(job->ibs[0].length_dw > num_dw); 286 287 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 288 if (tmz) 289 flags |= AMDGPU_PTE_TMZ; 290 291 cpu_addr = &job->ibs[0].ptr[num_dw]; 292 293 if (mem->mem_type == TTM_PL_TT) { 294 dma_addr_t *dma_address; 295 296 dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT]; 297 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, 298 cpu_addr); 299 if (r) 300 goto error_free; 301 } else { 302 dma_addr_t dma_address; 303 304 dma_address = (mm_node->start << PAGE_SHIFT) + offset; 305 dma_address += adev->vm_manager.vram_base_offset; 306 307 for (i = 0; i < num_pages; ++i) { 308 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 309 &dma_address, flags, cpu_addr); 310 if (r) 311 goto error_free; 312 313 dma_address += PAGE_SIZE; 314 } 315 } 316 317 r = amdgpu_job_submit(job, &adev->mman.entity, 318 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 319 if (r) 320 goto error_free; 321 322 dma_fence_put(fence); 323 324 return r; 325 326 error_free: 327 amdgpu_job_free(job); 328 return r; 329 } 330 331 /** 332 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 333 * @adev: amdgpu device 334 * @src: buffer/address where to read from 335 * @dst: buffer/address where to write to 336 * @size: number of bytes to copy 337 * @tmz: if a secure copy should be used 338 * @resv: resv object to sync to 339 * @f: Returns the last fence if multiple jobs are submitted. 340 * 341 * The function copies @size bytes from {src->mem + src->offset} to 342 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 343 * move and different for a BO to BO copy. 344 * 345 */ 346 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 347 const struct amdgpu_copy_mem *src, 348 const struct amdgpu_copy_mem *dst, 349 uint64_t size, bool tmz, 350 struct dma_resv *resv, 351 struct dma_fence **f) 352 { 353 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 354 AMDGPU_GPU_PAGE_SIZE); 355 356 uint64_t src_node_size, dst_node_size, src_offset, dst_offset; 357 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 358 struct drm_mm_node *src_mm, *dst_mm; 359 struct dma_fence *fence = NULL; 360 int r = 0; 361 362 if (!adev->mman.buffer_funcs_enabled) { 363 DRM_ERROR("Trying to move memory with ring turned off.\n"); 364 return -EINVAL; 365 } 366 367 src_offset = src->offset; 368 if (src->mem->mm_node) { 369 src_mm = amdgpu_find_mm_node(src->mem, &src_offset); 370 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; 371 } else { 372 src_mm = NULL; 373 src_node_size = ULLONG_MAX; 374 } 375 376 dst_offset = dst->offset; 377 if (dst->mem->mm_node) { 378 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); 379 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; 380 } else { 381 dst_mm = NULL; 382 dst_node_size = ULLONG_MAX; 383 } 384 385 mutex_lock(&adev->mman.gtt_window_lock); 386 387 while (size) { 388 uint32_t src_page_offset = src_offset & ~PAGE_MASK; 389 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; 390 struct dma_fence *next; 391 uint32_t cur_size; 392 uint64_t from, to; 393 394 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 395 * begins at an offset, then adjust the size accordingly 396 */ 397 cur_size = max(src_page_offset, dst_page_offset); 398 cur_size = min(min3(src_node_size, dst_node_size, size), 399 (uint64_t)(GTT_MAX_BYTES - cur_size)); 400 401 /* Map src to window 0 and dst to window 1. */ 402 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, 403 PFN_UP(cur_size + src_page_offset), 404 src_offset, 0, ring, tmz, &from); 405 if (r) 406 goto error; 407 408 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, 409 PFN_UP(cur_size + dst_page_offset), 410 dst_offset, 1, ring, tmz, &to); 411 if (r) 412 goto error; 413 414 r = amdgpu_copy_buffer(ring, from, to, cur_size, 415 resv, &next, false, true, tmz); 416 if (r) 417 goto error; 418 419 dma_fence_put(fence); 420 fence = next; 421 422 size -= cur_size; 423 if (!size) 424 break; 425 426 src_node_size -= cur_size; 427 if (!src_node_size) { 428 ++src_mm; 429 src_node_size = src_mm->size << PAGE_SHIFT; 430 src_offset = 0; 431 } else { 432 src_offset += cur_size; 433 } 434 435 dst_node_size -= cur_size; 436 if (!dst_node_size) { 437 ++dst_mm; 438 dst_node_size = dst_mm->size << PAGE_SHIFT; 439 dst_offset = 0; 440 } else { 441 dst_offset += cur_size; 442 } 443 } 444 error: 445 mutex_unlock(&adev->mman.gtt_window_lock); 446 if (f) 447 *f = dma_fence_get(fence); 448 dma_fence_put(fence); 449 return r; 450 } 451 452 /* 453 * amdgpu_move_blit - Copy an entire buffer to another buffer 454 * 455 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 456 * help move buffers to and from VRAM. 457 */ 458 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 459 bool evict, 460 struct ttm_resource *new_mem, 461 struct ttm_resource *old_mem) 462 { 463 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 464 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 465 struct amdgpu_copy_mem src, dst; 466 struct dma_fence *fence = NULL; 467 int r; 468 469 src.bo = bo; 470 dst.bo = bo; 471 src.mem = old_mem; 472 dst.mem = new_mem; 473 src.offset = 0; 474 dst.offset = 0; 475 476 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 477 new_mem->num_pages << PAGE_SHIFT, 478 amdgpu_bo_encrypted(abo), 479 bo->base.resv, &fence); 480 if (r) 481 goto error; 482 483 /* clear the space being freed */ 484 if (old_mem->mem_type == TTM_PL_VRAM && 485 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 486 struct dma_fence *wipe_fence = NULL; 487 488 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 489 NULL, &wipe_fence); 490 if (r) { 491 goto error; 492 } else if (wipe_fence) { 493 dma_fence_put(fence); 494 fence = wipe_fence; 495 } 496 } 497 498 /* Always block for VM page tables before committing the new location */ 499 if (bo->type == ttm_bo_type_kernel) 500 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 501 else 502 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 503 dma_fence_put(fence); 504 return r; 505 506 error: 507 if (fence) 508 dma_fence_wait(fence, false); 509 dma_fence_put(fence); 510 return r; 511 } 512 513 /* 514 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 515 * 516 * Called by amdgpu_bo_move() 517 */ 518 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 519 struct ttm_resource *mem) 520 { 521 struct drm_mm_node *nodes = mem->mm_node; 522 523 if (mem->mem_type == TTM_PL_SYSTEM || 524 mem->mem_type == TTM_PL_TT) 525 return true; 526 if (mem->mem_type != TTM_PL_VRAM) 527 return false; 528 529 /* ttm_resource_ioremap only supports contiguous memory */ 530 if (nodes->size != mem->num_pages) 531 return false; 532 533 return ((nodes->start + nodes->size) << PAGE_SHIFT) 534 <= adev->gmc.visible_vram_size; 535 } 536 537 /* 538 * amdgpu_bo_move - Move a buffer object to a new memory location 539 * 540 * Called by ttm_bo_handle_move_mem() 541 */ 542 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 543 struct ttm_operation_ctx *ctx, 544 struct ttm_resource *new_mem, 545 struct ttm_place *hop) 546 { 547 struct amdgpu_device *adev; 548 struct amdgpu_bo *abo; 549 struct ttm_resource *old_mem = &bo->mem; 550 int r; 551 552 if (new_mem->mem_type == TTM_PL_TT) { 553 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 554 if (r) 555 return r; 556 } 557 558 /* Can't move a pinned BO */ 559 abo = ttm_to_amdgpu_bo(bo); 560 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 561 return -EINVAL; 562 563 adev = amdgpu_ttm_adev(bo->bdev); 564 565 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 566 ttm_bo_move_null(bo, new_mem); 567 goto out; 568 } 569 if (old_mem->mem_type == TTM_PL_SYSTEM && 570 new_mem->mem_type == TTM_PL_TT) { 571 ttm_bo_move_null(bo, new_mem); 572 goto out; 573 } 574 if (old_mem->mem_type == TTM_PL_TT && 575 new_mem->mem_type == TTM_PL_SYSTEM) { 576 r = ttm_bo_wait_ctx(bo, ctx); 577 if (r) 578 return r; 579 580 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 581 ttm_resource_free(bo, &bo->mem); 582 ttm_bo_assign_mem(bo, new_mem); 583 goto out; 584 } 585 586 if (old_mem->mem_type == AMDGPU_PL_GDS || 587 old_mem->mem_type == AMDGPU_PL_GWS || 588 old_mem->mem_type == AMDGPU_PL_OA || 589 new_mem->mem_type == AMDGPU_PL_GDS || 590 new_mem->mem_type == AMDGPU_PL_GWS || 591 new_mem->mem_type == AMDGPU_PL_OA) { 592 /* Nothing to save here */ 593 ttm_bo_move_null(bo, new_mem); 594 goto out; 595 } 596 597 if (adev->mman.buffer_funcs_enabled) { 598 if (((old_mem->mem_type == TTM_PL_SYSTEM && 599 new_mem->mem_type == TTM_PL_VRAM) || 600 (old_mem->mem_type == TTM_PL_VRAM && 601 new_mem->mem_type == TTM_PL_SYSTEM))) { 602 hop->fpfn = 0; 603 hop->lpfn = 0; 604 hop->mem_type = TTM_PL_TT; 605 hop->flags = 0; 606 return -EMULTIHOP; 607 } 608 609 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 610 } else { 611 r = -ENODEV; 612 } 613 614 if (r) { 615 /* Check that all memory is CPU accessible */ 616 if (!amdgpu_mem_visible(adev, old_mem) || 617 !amdgpu_mem_visible(adev, new_mem)) { 618 pr_err("Move buffer fallback to memcpy unavailable\n"); 619 return r; 620 } 621 622 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 623 if (r) 624 return r; 625 } 626 627 if (bo->type == ttm_bo_type_device && 628 new_mem->mem_type == TTM_PL_VRAM && 629 old_mem->mem_type != TTM_PL_VRAM) { 630 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 631 * accesses the BO after it's moved. 632 */ 633 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 634 } 635 636 out: 637 /* update statistics */ 638 atomic64_add(bo->base.size, &adev->num_bytes_moved); 639 amdgpu_bo_move_notify(bo, evict, new_mem); 640 return 0; 641 } 642 643 /* 644 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 645 * 646 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 647 */ 648 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) 649 { 650 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 651 struct drm_mm_node *mm_node = mem->mm_node; 652 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 653 654 switch (mem->mem_type) { 655 case TTM_PL_SYSTEM: 656 /* system memory */ 657 return 0; 658 case TTM_PL_TT: 659 break; 660 case TTM_PL_VRAM: 661 mem->bus.offset = mem->start << PAGE_SHIFT; 662 /* check if it's visible */ 663 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 664 return -EINVAL; 665 /* Only physically contiguous buffers apply. In a contiguous 666 * buffer, size of the first mm_node would match the number of 667 * pages in ttm_resource. 668 */ 669 if (adev->mman.aper_base_kaddr && 670 (mm_node->size == mem->num_pages)) 671 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 672 mem->bus.offset; 673 674 mem->bus.offset += adev->gmc.aper_base; 675 mem->bus.is_iomem = true; 676 mem->bus.caching = ttm_write_combined; 677 break; 678 default: 679 return -EINVAL; 680 } 681 return 0; 682 } 683 684 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 685 unsigned long page_offset) 686 { 687 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 688 uint64_t offset = (page_offset << PAGE_SHIFT); 689 struct drm_mm_node *mm; 690 691 mm = amdgpu_find_mm_node(&bo->mem, &offset); 692 offset += adev->gmc.aper_base; 693 return mm->start + (offset >> PAGE_SHIFT); 694 } 695 696 /** 697 * amdgpu_ttm_domain_start - Returns GPU start address 698 * @adev: amdgpu device object 699 * @type: type of the memory 700 * 701 * Returns: 702 * GPU start address of a memory domain 703 */ 704 705 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 706 { 707 switch (type) { 708 case TTM_PL_TT: 709 return adev->gmc.gart_start; 710 case TTM_PL_VRAM: 711 return adev->gmc.vram_start; 712 } 713 714 return 0; 715 } 716 717 /* 718 * TTM backend functions. 719 */ 720 struct amdgpu_ttm_tt { 721 struct ttm_tt ttm; 722 struct drm_gem_object *gobj; 723 u64 offset; 724 uint64_t userptr; 725 struct task_struct *usertask; 726 uint32_t userflags; 727 bool bound; 728 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 729 struct hmm_range *range; 730 #endif 731 }; 732 733 #ifdef CONFIG_DRM_AMDGPU_USERPTR 734 /* 735 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 736 * memory and start HMM tracking CPU page table update 737 * 738 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 739 * once afterwards to stop HMM tracking 740 */ 741 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 742 { 743 struct ttm_tt *ttm = bo->tbo.ttm; 744 struct amdgpu_ttm_tt *gtt = (void *)ttm; 745 unsigned long start = gtt->userptr; 746 struct vm_area_struct *vma; 747 struct hmm_range *range; 748 unsigned long timeout; 749 struct mm_struct *mm; 750 unsigned long i; 751 int r = 0; 752 753 mm = bo->notifier.mm; 754 if (unlikely(!mm)) { 755 DRM_DEBUG_DRIVER("BO is not registered?\n"); 756 return -EFAULT; 757 } 758 759 /* Another get_user_pages is running at the same time?? */ 760 if (WARN_ON(gtt->range)) 761 return -EFAULT; 762 763 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 764 return -ESRCH; 765 766 range = kzalloc(sizeof(*range), GFP_KERNEL); 767 if (unlikely(!range)) { 768 r = -ENOMEM; 769 goto out; 770 } 771 range->notifier = &bo->notifier; 772 range->start = bo->notifier.interval_tree.start; 773 range->end = bo->notifier.interval_tree.last + 1; 774 range->default_flags = HMM_PFN_REQ_FAULT; 775 if (!amdgpu_ttm_tt_is_readonly(ttm)) 776 range->default_flags |= HMM_PFN_REQ_WRITE; 777 778 range->hmm_pfns = kvmalloc_array(ttm->num_pages, 779 sizeof(*range->hmm_pfns), GFP_KERNEL); 780 if (unlikely(!range->hmm_pfns)) { 781 r = -ENOMEM; 782 goto out_free_ranges; 783 } 784 785 mmap_read_lock(mm); 786 vma = find_vma(mm, start); 787 if (unlikely(!vma || start < vma->vm_start)) { 788 r = -EFAULT; 789 goto out_unlock; 790 } 791 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 792 vma->vm_file)) { 793 r = -EPERM; 794 goto out_unlock; 795 } 796 mmap_read_unlock(mm); 797 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 798 799 retry: 800 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 801 802 mmap_read_lock(mm); 803 r = hmm_range_fault(range); 804 mmap_read_unlock(mm); 805 if (unlikely(r)) { 806 /* 807 * FIXME: This timeout should encompass the retry from 808 * mmu_interval_read_retry() as well. 809 */ 810 if (r == -EBUSY && !time_after(jiffies, timeout)) 811 goto retry; 812 goto out_free_pfns; 813 } 814 815 /* 816 * Due to default_flags, all pages are HMM_PFN_VALID or 817 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside 818 * the notifier_lock, and mmu_interval_read_retry() must be done first. 819 */ 820 for (i = 0; i < ttm->num_pages; i++) 821 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); 822 823 gtt->range = range; 824 mmput(mm); 825 826 return 0; 827 828 out_unlock: 829 mmap_read_unlock(mm); 830 out_free_pfns: 831 kvfree(range->hmm_pfns); 832 out_free_ranges: 833 kfree(range); 834 out: 835 mmput(mm); 836 return r; 837 } 838 839 /* 840 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 841 * Check if the pages backing this ttm range have been invalidated 842 * 843 * Returns: true if pages are still valid 844 */ 845 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 846 { 847 struct amdgpu_ttm_tt *gtt = (void *)ttm; 848 bool r = false; 849 850 if (!gtt || !gtt->userptr) 851 return false; 852 853 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 854 gtt->userptr, ttm->num_pages); 855 856 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 857 "No user pages to check\n"); 858 859 if (gtt->range) { 860 /* 861 * FIXME: Must always hold notifier_lock for this, and must 862 * not ignore the return code. 863 */ 864 r = mmu_interval_read_retry(gtt->range->notifier, 865 gtt->range->notifier_seq); 866 kvfree(gtt->range->hmm_pfns); 867 kfree(gtt->range); 868 gtt->range = NULL; 869 } 870 871 return !r; 872 } 873 #endif 874 875 /* 876 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 877 * 878 * Called by amdgpu_cs_list_validate(). This creates the page list 879 * that backs user memory and will ultimately be mapped into the device 880 * address space. 881 */ 882 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 883 { 884 unsigned long i; 885 886 for (i = 0; i < ttm->num_pages; ++i) 887 ttm->pages[i] = pages ? pages[i] : NULL; 888 } 889 890 /* 891 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 892 * 893 * Called by amdgpu_ttm_backend_bind() 894 **/ 895 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, 896 struct ttm_tt *ttm) 897 { 898 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 899 struct amdgpu_ttm_tt *gtt = (void *)ttm; 900 int r; 901 902 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 903 enum dma_data_direction direction = write ? 904 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 905 906 /* Allocate an SG array and squash pages into it */ 907 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 908 ttm->num_pages << PAGE_SHIFT, 909 GFP_KERNEL); 910 if (r) 911 goto release_sg; 912 913 /* Map SG to device */ 914 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 915 if (r) 916 goto release_sg; 917 918 /* convert SG to linear array of pages and dma addresses */ 919 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 920 ttm->num_pages); 921 922 return 0; 923 924 release_sg: 925 kfree(ttm->sg); 926 ttm->sg = NULL; 927 return r; 928 } 929 930 /* 931 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 932 */ 933 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, 934 struct ttm_tt *ttm) 935 { 936 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 937 struct amdgpu_ttm_tt *gtt = (void *)ttm; 938 939 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 940 enum dma_data_direction direction = write ? 941 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 942 943 /* double check that we don't free the table twice */ 944 if (!ttm->sg->sgl) 945 return; 946 947 /* unmap the pages mapped to the device */ 948 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 949 sg_free_table(ttm->sg); 950 951 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 952 if (gtt->range) { 953 unsigned long i; 954 955 for (i = 0; i < ttm->num_pages; i++) { 956 if (ttm->pages[i] != 957 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 958 break; 959 } 960 961 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 962 } 963 #endif 964 } 965 966 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 967 struct ttm_buffer_object *tbo, 968 uint64_t flags) 969 { 970 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 971 struct ttm_tt *ttm = tbo->ttm; 972 struct amdgpu_ttm_tt *gtt = (void *)ttm; 973 int r; 974 975 if (amdgpu_bo_encrypted(abo)) 976 flags |= AMDGPU_PTE_TMZ; 977 978 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 979 uint64_t page_idx = 1; 980 981 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 982 ttm->pages, gtt->ttm.dma_address, flags); 983 if (r) 984 goto gart_bind_fail; 985 986 /* The memory type of the first page defaults to UC. Now 987 * modify the memory type to NC from the second page of 988 * the BO onward. 989 */ 990 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 991 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 992 993 r = amdgpu_gart_bind(adev, 994 gtt->offset + (page_idx << PAGE_SHIFT), 995 ttm->num_pages - page_idx, 996 &ttm->pages[page_idx], 997 &(gtt->ttm.dma_address[page_idx]), flags); 998 } else { 999 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1000 ttm->pages, gtt->ttm.dma_address, flags); 1001 } 1002 1003 gart_bind_fail: 1004 if (r) 1005 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 1006 ttm->num_pages, gtt->offset); 1007 1008 return r; 1009 } 1010 1011 /* 1012 * amdgpu_ttm_backend_bind - Bind GTT memory 1013 * 1014 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 1015 * This handles binding GTT memory to the device address space. 1016 */ 1017 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, 1018 struct ttm_tt *ttm, 1019 struct ttm_resource *bo_mem) 1020 { 1021 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1022 struct amdgpu_ttm_tt *gtt = (void*)ttm; 1023 uint64_t flags; 1024 int r = 0; 1025 1026 if (!bo_mem) 1027 return -EINVAL; 1028 1029 if (gtt->bound) 1030 return 0; 1031 1032 if (gtt->userptr) { 1033 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 1034 if (r) { 1035 DRM_ERROR("failed to pin userptr\n"); 1036 return r; 1037 } 1038 } 1039 if (!ttm->num_pages) { 1040 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 1041 ttm->num_pages, bo_mem, ttm); 1042 } 1043 1044 if (bo_mem->mem_type == AMDGPU_PL_GDS || 1045 bo_mem->mem_type == AMDGPU_PL_GWS || 1046 bo_mem->mem_type == AMDGPU_PL_OA) 1047 return -EINVAL; 1048 1049 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 1050 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 1051 return 0; 1052 } 1053 1054 /* compute PTE flags relevant to this BO memory */ 1055 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 1056 1057 /* bind pages into GART page tables */ 1058 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 1059 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1060 ttm->pages, gtt->ttm.dma_address, flags); 1061 1062 if (r) 1063 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 1064 ttm->num_pages, gtt->offset); 1065 gtt->bound = true; 1066 return r; 1067 } 1068 1069 /* 1070 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 1071 * through AGP or GART aperture. 1072 * 1073 * If bo is accessible through AGP aperture, then use AGP aperture 1074 * to access bo; otherwise allocate logical space in GART aperture 1075 * and map bo to GART aperture. 1076 */ 1077 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1078 { 1079 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1080 struct ttm_operation_ctx ctx = { false, false }; 1081 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 1082 struct ttm_resource tmp; 1083 struct ttm_placement placement; 1084 struct ttm_place placements; 1085 uint64_t addr, flags; 1086 int r; 1087 1088 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1089 return 0; 1090 1091 addr = amdgpu_gmc_agp_addr(bo); 1092 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1093 bo->mem.start = addr >> PAGE_SHIFT; 1094 } else { 1095 1096 /* allocate GART space */ 1097 tmp = bo->mem; 1098 tmp.mm_node = NULL; 1099 placement.num_placement = 1; 1100 placement.placement = &placements; 1101 placement.num_busy_placement = 1; 1102 placement.busy_placement = &placements; 1103 placements.fpfn = 0; 1104 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1105 placements.mem_type = TTM_PL_TT; 1106 placements.flags = bo->mem.placement; 1107 1108 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1109 if (unlikely(r)) 1110 return r; 1111 1112 /* compute PTE flags for this buffer object */ 1113 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1114 1115 /* Bind pages */ 1116 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1117 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1118 if (unlikely(r)) { 1119 ttm_resource_free(bo, &tmp); 1120 return r; 1121 } 1122 1123 ttm_resource_free(bo, &bo->mem); 1124 bo->mem = tmp; 1125 } 1126 1127 return 0; 1128 } 1129 1130 /* 1131 * amdgpu_ttm_recover_gart - Rebind GTT pages 1132 * 1133 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1134 * rebind GTT pages during a GPU reset. 1135 */ 1136 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1137 { 1138 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1139 uint64_t flags; 1140 int r; 1141 1142 if (!tbo->ttm) 1143 return 0; 1144 1145 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1146 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1147 1148 return r; 1149 } 1150 1151 /* 1152 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1153 * 1154 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1155 * ttm_tt_destroy(). 1156 */ 1157 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, 1158 struct ttm_tt *ttm) 1159 { 1160 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1161 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1162 int r; 1163 1164 if (!gtt->bound) 1165 return; 1166 1167 /* if the pages have userptr pinning then clear that first */ 1168 if (gtt->userptr) 1169 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1170 1171 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1172 return; 1173 1174 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1175 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1176 if (r) 1177 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1178 gtt->ttm.num_pages, gtt->offset); 1179 gtt->bound = false; 1180 } 1181 1182 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev, 1183 struct ttm_tt *ttm) 1184 { 1185 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1186 1187 amdgpu_ttm_backend_unbind(bdev, ttm); 1188 ttm_tt_destroy_common(bdev, ttm); 1189 if (gtt->usertask) 1190 put_task_struct(gtt->usertask); 1191 1192 ttm_tt_fini(>t->ttm); 1193 kfree(gtt); 1194 } 1195 1196 /** 1197 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1198 * 1199 * @bo: The buffer object to create a GTT ttm_tt object around 1200 * @page_flags: Page flags to be added to the ttm_tt object 1201 * 1202 * Called by ttm_tt_create(). 1203 */ 1204 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1205 uint32_t page_flags) 1206 { 1207 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1208 struct amdgpu_ttm_tt *gtt; 1209 enum ttm_caching caching; 1210 1211 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1212 if (gtt == NULL) { 1213 return NULL; 1214 } 1215 gtt->gobj = &bo->base; 1216 1217 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1218 caching = ttm_write_combined; 1219 else 1220 caching = ttm_cached; 1221 1222 /* allocate space for the uninitialized page entries */ 1223 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1224 kfree(gtt); 1225 return NULL; 1226 } 1227 return >t->ttm; 1228 } 1229 1230 /* 1231 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1232 * 1233 * Map the pages of a ttm_tt object to an address space visible 1234 * to the underlying device. 1235 */ 1236 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev, 1237 struct ttm_tt *ttm, 1238 struct ttm_operation_ctx *ctx) 1239 { 1240 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1241 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1242 1243 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1244 if (gtt && gtt->userptr) { 1245 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1246 if (!ttm->sg) 1247 return -ENOMEM; 1248 1249 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1250 return 0; 1251 } 1252 1253 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1254 if (!ttm->sg) { 1255 struct dma_buf_attachment *attach; 1256 struct sg_table *sgt; 1257 1258 attach = gtt->gobj->import_attach; 1259 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1260 if (IS_ERR(sgt)) 1261 return PTR_ERR(sgt); 1262 1263 ttm->sg = sgt; 1264 } 1265 1266 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 1267 ttm->num_pages); 1268 return 0; 1269 } 1270 1271 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1272 } 1273 1274 /* 1275 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1276 * 1277 * Unmaps pages of a ttm_tt object from the device address space and 1278 * unpopulates the page array backing it. 1279 */ 1280 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, 1281 struct ttm_tt *ttm) 1282 { 1283 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1284 struct amdgpu_device *adev; 1285 1286 if (gtt && gtt->userptr) { 1287 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1288 kfree(ttm->sg); 1289 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1290 return; 1291 } 1292 1293 if (ttm->sg && gtt->gobj->import_attach) { 1294 struct dma_buf_attachment *attach; 1295 1296 attach = gtt->gobj->import_attach; 1297 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1298 ttm->sg = NULL; 1299 return; 1300 } 1301 1302 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1303 return; 1304 1305 adev = amdgpu_ttm_adev(bdev); 1306 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1307 } 1308 1309 /** 1310 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1311 * task 1312 * 1313 * @bo: The ttm_buffer_object to bind this userptr to 1314 * @addr: The address in the current tasks VM space to use 1315 * @flags: Requirements of userptr object. 1316 * 1317 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1318 * to current task 1319 */ 1320 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1321 uint64_t addr, uint32_t flags) 1322 { 1323 struct amdgpu_ttm_tt *gtt; 1324 1325 if (!bo->ttm) { 1326 /* TODO: We want a separate TTM object type for userptrs */ 1327 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1328 if (bo->ttm == NULL) 1329 return -ENOMEM; 1330 } 1331 1332 gtt = (void *)bo->ttm; 1333 gtt->userptr = addr; 1334 gtt->userflags = flags; 1335 1336 if (gtt->usertask) 1337 put_task_struct(gtt->usertask); 1338 gtt->usertask = current->group_leader; 1339 get_task_struct(gtt->usertask); 1340 1341 return 0; 1342 } 1343 1344 /* 1345 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1346 */ 1347 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1348 { 1349 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1350 1351 if (gtt == NULL) 1352 return NULL; 1353 1354 if (gtt->usertask == NULL) 1355 return NULL; 1356 1357 return gtt->usertask->mm; 1358 } 1359 1360 /* 1361 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1362 * address range for the current task. 1363 * 1364 */ 1365 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1366 unsigned long end) 1367 { 1368 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1369 unsigned long size; 1370 1371 if (gtt == NULL || !gtt->userptr) 1372 return false; 1373 1374 /* Return false if no part of the ttm_tt object lies within 1375 * the range 1376 */ 1377 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1378 if (gtt->userptr > end || gtt->userptr + size <= start) 1379 return false; 1380 1381 return true; 1382 } 1383 1384 /* 1385 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1386 */ 1387 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1388 { 1389 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1390 1391 if (gtt == NULL || !gtt->userptr) 1392 return false; 1393 1394 return true; 1395 } 1396 1397 /* 1398 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1399 */ 1400 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1401 { 1402 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1403 1404 if (gtt == NULL) 1405 return false; 1406 1407 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1408 } 1409 1410 /** 1411 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1412 * 1413 * @ttm: The ttm_tt object to compute the flags for 1414 * @mem: The memory registry backing this ttm_tt object 1415 * 1416 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1417 */ 1418 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1419 { 1420 uint64_t flags = 0; 1421 1422 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1423 flags |= AMDGPU_PTE_VALID; 1424 1425 if (mem && mem->mem_type == TTM_PL_TT) { 1426 flags |= AMDGPU_PTE_SYSTEM; 1427 1428 if (ttm->caching == ttm_cached) 1429 flags |= AMDGPU_PTE_SNOOPED; 1430 } 1431 1432 return flags; 1433 } 1434 1435 /** 1436 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1437 * 1438 * @adev: amdgpu_device pointer 1439 * @ttm: The ttm_tt object to compute the flags for 1440 * @mem: The memory registry backing this ttm_tt object 1441 * 1442 * Figure out the flags to use for a VM PTE (Page Table Entry). 1443 */ 1444 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1445 struct ttm_resource *mem) 1446 { 1447 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1448 1449 flags |= adev->gart.gart_pte_flags; 1450 flags |= AMDGPU_PTE_READABLE; 1451 1452 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1453 flags |= AMDGPU_PTE_WRITEABLE; 1454 1455 return flags; 1456 } 1457 1458 /* 1459 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1460 * object. 1461 * 1462 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1463 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1464 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1465 * used to clean out a memory space. 1466 */ 1467 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1468 const struct ttm_place *place) 1469 { 1470 unsigned long num_pages = bo->mem.num_pages; 1471 struct drm_mm_node *node = bo->mem.mm_node; 1472 struct dma_resv_list *flist; 1473 struct dma_fence *f; 1474 int i; 1475 1476 if (bo->type == ttm_bo_type_kernel && 1477 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1478 return false; 1479 1480 /* If bo is a KFD BO, check if the bo belongs to the current process. 1481 * If true, then return false as any KFD process needs all its BOs to 1482 * be resident to run successfully 1483 */ 1484 flist = dma_resv_get_list(bo->base.resv); 1485 if (flist) { 1486 for (i = 0; i < flist->shared_count; ++i) { 1487 f = rcu_dereference_protected(flist->shared[i], 1488 dma_resv_held(bo->base.resv)); 1489 if (amdkfd_fence_check_mm(f, current->mm)) 1490 return false; 1491 } 1492 } 1493 1494 switch (bo->mem.mem_type) { 1495 case TTM_PL_TT: 1496 if (amdgpu_bo_is_amdgpu_bo(bo) && 1497 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1498 return false; 1499 return true; 1500 1501 case TTM_PL_VRAM: 1502 /* Check each drm MM node individually */ 1503 while (num_pages) { 1504 if (place->fpfn < (node->start + node->size) && 1505 !(place->lpfn && place->lpfn <= node->start)) 1506 return true; 1507 1508 num_pages -= node->size; 1509 ++node; 1510 } 1511 return false; 1512 1513 default: 1514 break; 1515 } 1516 1517 return ttm_bo_eviction_valuable(bo, place); 1518 } 1519 1520 /** 1521 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1522 * 1523 * @bo: The buffer object to read/write 1524 * @offset: Offset into buffer object 1525 * @buf: Secondary buffer to write/read from 1526 * @len: Length in bytes of access 1527 * @write: true if writing 1528 * 1529 * This is used to access VRAM that backs a buffer object via MMIO 1530 * access for debugging purposes. 1531 */ 1532 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1533 unsigned long offset, 1534 void *buf, int len, int write) 1535 { 1536 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1537 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1538 struct drm_mm_node *nodes; 1539 uint32_t value = 0; 1540 int ret = 0; 1541 uint64_t pos; 1542 unsigned long flags; 1543 1544 if (bo->mem.mem_type != TTM_PL_VRAM) 1545 return -EIO; 1546 1547 pos = offset; 1548 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); 1549 pos += (nodes->start << PAGE_SHIFT); 1550 1551 while (len && pos < adev->gmc.mc_vram_size) { 1552 uint64_t aligned_pos = pos & ~(uint64_t)3; 1553 uint64_t bytes = 4 - (pos & 3); 1554 uint32_t shift = (pos & 3) * 8; 1555 uint32_t mask = 0xffffffff << shift; 1556 1557 if (len < bytes) { 1558 mask &= 0xffffffff >> (bytes - len) * 8; 1559 bytes = len; 1560 } 1561 1562 if (mask != 0xffffffff) { 1563 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1564 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1565 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1566 if (!write || mask != 0xffffffff) 1567 value = RREG32_NO_KIQ(mmMM_DATA); 1568 if (write) { 1569 value &= ~mask; 1570 value |= (*(uint32_t *)buf << shift) & mask; 1571 WREG32_NO_KIQ(mmMM_DATA, value); 1572 } 1573 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1574 if (!write) { 1575 value = (value & mask) >> shift; 1576 memcpy(buf, &value, bytes); 1577 } 1578 } else { 1579 bytes = (nodes->start + nodes->size) << PAGE_SHIFT; 1580 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); 1581 1582 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, 1583 bytes, write); 1584 } 1585 1586 ret += bytes; 1587 buf = (uint8_t *)buf + bytes; 1588 pos += bytes; 1589 len -= bytes; 1590 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { 1591 ++nodes; 1592 pos = (nodes->start << PAGE_SHIFT); 1593 } 1594 } 1595 1596 return ret; 1597 } 1598 1599 static void 1600 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1601 { 1602 amdgpu_bo_move_notify(bo, false, NULL); 1603 } 1604 1605 static struct ttm_bo_driver amdgpu_bo_driver = { 1606 .ttm_tt_create = &amdgpu_ttm_tt_create, 1607 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1608 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1609 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1610 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1611 .evict_flags = &amdgpu_evict_flags, 1612 .move = &amdgpu_bo_move, 1613 .verify_access = &amdgpu_verify_access, 1614 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1615 .release_notify = &amdgpu_bo_release_notify, 1616 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1617 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1618 .access_memory = &amdgpu_ttm_access_memory, 1619 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1620 }; 1621 1622 /* 1623 * Firmware Reservation functions 1624 */ 1625 /** 1626 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1627 * 1628 * @adev: amdgpu_device pointer 1629 * 1630 * free fw reserved vram if it has been reserved. 1631 */ 1632 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1633 { 1634 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1635 NULL, &adev->mman.fw_vram_usage_va); 1636 } 1637 1638 /** 1639 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1640 * 1641 * @adev: amdgpu_device pointer 1642 * 1643 * create bo vram reservation from fw. 1644 */ 1645 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1646 { 1647 uint64_t vram_size = adev->gmc.visible_vram_size; 1648 1649 adev->mman.fw_vram_usage_va = NULL; 1650 adev->mman.fw_vram_usage_reserved_bo = NULL; 1651 1652 if (adev->mman.fw_vram_usage_size == 0 || 1653 adev->mman.fw_vram_usage_size > vram_size) 1654 return 0; 1655 1656 return amdgpu_bo_create_kernel_at(adev, 1657 adev->mman.fw_vram_usage_start_offset, 1658 adev->mman.fw_vram_usage_size, 1659 AMDGPU_GEM_DOMAIN_VRAM, 1660 &adev->mman.fw_vram_usage_reserved_bo, 1661 &adev->mman.fw_vram_usage_va); 1662 } 1663 1664 /* 1665 * Memoy training reservation functions 1666 */ 1667 1668 /** 1669 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1670 * 1671 * @adev: amdgpu_device pointer 1672 * 1673 * free memory training reserved vram if it has been reserved. 1674 */ 1675 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1676 { 1677 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1678 1679 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1680 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1681 ctx->c2p_bo = NULL; 1682 1683 return 0; 1684 } 1685 1686 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1687 { 1688 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1689 1690 memset(ctx, 0, sizeof(*ctx)); 1691 1692 ctx->c2p_train_data_offset = 1693 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1694 ctx->p2c_train_data_offset = 1695 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1696 ctx->train_data_size = 1697 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1698 1699 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1700 ctx->train_data_size, 1701 ctx->p2c_train_data_offset, 1702 ctx->c2p_train_data_offset); 1703 } 1704 1705 /* 1706 * reserve TMR memory at the top of VRAM which holds 1707 * IP Discovery data and is protected by PSP. 1708 */ 1709 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1710 { 1711 int ret; 1712 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1713 bool mem_train_support = false; 1714 1715 if (!amdgpu_sriov_vf(adev)) { 1716 ret = amdgpu_mem_train_support(adev); 1717 if (ret == 1) 1718 mem_train_support = true; 1719 else if (ret == -1) 1720 return -EINVAL; 1721 else 1722 DRM_DEBUG("memory training does not support!\n"); 1723 } 1724 1725 /* 1726 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1727 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1728 * 1729 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1730 * discovery data and G6 memory training data respectively 1731 */ 1732 adev->mman.discovery_tmr_size = 1733 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1734 if (!adev->mman.discovery_tmr_size) 1735 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1736 1737 if (mem_train_support) { 1738 /* reserve vram for mem train according to TMR location */ 1739 amdgpu_ttm_training_data_block_init(adev); 1740 ret = amdgpu_bo_create_kernel_at(adev, 1741 ctx->c2p_train_data_offset, 1742 ctx->train_data_size, 1743 AMDGPU_GEM_DOMAIN_VRAM, 1744 &ctx->c2p_bo, 1745 NULL); 1746 if (ret) { 1747 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1748 amdgpu_ttm_training_reserve_vram_fini(adev); 1749 return ret; 1750 } 1751 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1752 } 1753 1754 ret = amdgpu_bo_create_kernel_at(adev, 1755 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1756 adev->mman.discovery_tmr_size, 1757 AMDGPU_GEM_DOMAIN_VRAM, 1758 &adev->mman.discovery_memory, 1759 NULL); 1760 if (ret) { 1761 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1762 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1763 return ret; 1764 } 1765 1766 return 0; 1767 } 1768 1769 /* 1770 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1771 * gtt/vram related fields. 1772 * 1773 * This initializes all of the memory space pools that the TTM layer 1774 * will need such as the GTT space (system memory mapped to the device), 1775 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1776 * can be mapped per VMID. 1777 */ 1778 int amdgpu_ttm_init(struct amdgpu_device *adev) 1779 { 1780 uint64_t gtt_size; 1781 int r; 1782 u64 vis_vram_limit; 1783 1784 mutex_init(&adev->mman.gtt_window_lock); 1785 1786 /* No others user of address space so set it to 0 */ 1787 r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1788 adev_to_drm(adev)->anon_inode->i_mapping, 1789 adev_to_drm(adev)->vma_offset_manager, 1790 adev->need_swiotlb, 1791 dma_addressing_limited(adev->dev)); 1792 if (r) { 1793 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1794 return r; 1795 } 1796 adev->mman.initialized = true; 1797 1798 /* Initialize VRAM pool with all of VRAM divided into pages */ 1799 r = amdgpu_vram_mgr_init(adev); 1800 if (r) { 1801 DRM_ERROR("Failed initializing VRAM heap.\n"); 1802 return r; 1803 } 1804 1805 /* Reduce size of CPU-visible VRAM if requested */ 1806 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1807 if (amdgpu_vis_vram_limit > 0 && 1808 vis_vram_limit <= adev->gmc.visible_vram_size) 1809 adev->gmc.visible_vram_size = vis_vram_limit; 1810 1811 /* Change the size here instead of the init above so only lpfn is affected */ 1812 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1813 #ifdef CONFIG_64BIT 1814 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1815 adev->gmc.visible_vram_size); 1816 #endif 1817 1818 /* 1819 *The reserved vram for firmware must be pinned to the specified 1820 *place on the VRAM, so reserve it early. 1821 */ 1822 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1823 if (r) { 1824 return r; 1825 } 1826 1827 /* 1828 * only NAVI10 and onwards ASIC support for IP discovery. 1829 * If IP discovery enabled, a block of memory should be 1830 * reserved for IP discovey. 1831 */ 1832 if (adev->mman.discovery_bin) { 1833 r = amdgpu_ttm_reserve_tmr(adev); 1834 if (r) 1835 return r; 1836 } 1837 1838 /* allocate memory as required for VGA 1839 * This is used for VGA emulation and pre-OS scanout buffers to 1840 * avoid display artifacts while transitioning between pre-OS 1841 * and driver. */ 1842 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1843 AMDGPU_GEM_DOMAIN_VRAM, 1844 &adev->mman.stolen_vga_memory, 1845 NULL); 1846 if (r) 1847 return r; 1848 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1849 adev->mman.stolen_extended_size, 1850 AMDGPU_GEM_DOMAIN_VRAM, 1851 &adev->mman.stolen_extended_memory, 1852 NULL); 1853 if (r) 1854 return r; 1855 1856 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1857 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1858 1859 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1860 * or whatever the user passed on module init */ 1861 if (amdgpu_gtt_size == -1) { 1862 struct sysinfo si; 1863 1864 si_meminfo(&si); 1865 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1866 adev->gmc.mc_vram_size), 1867 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1868 } 1869 else 1870 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1871 1872 /* Initialize GTT memory pool */ 1873 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1874 if (r) { 1875 DRM_ERROR("Failed initializing GTT heap.\n"); 1876 return r; 1877 } 1878 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1879 (unsigned)(gtt_size / (1024 * 1024))); 1880 1881 /* Initialize various on-chip memory pools */ 1882 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1883 if (r) { 1884 DRM_ERROR("Failed initializing GDS heap.\n"); 1885 return r; 1886 } 1887 1888 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1889 if (r) { 1890 DRM_ERROR("Failed initializing gws heap.\n"); 1891 return r; 1892 } 1893 1894 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1895 if (r) { 1896 DRM_ERROR("Failed initializing oa heap.\n"); 1897 return r; 1898 } 1899 1900 return 0; 1901 } 1902 1903 /* 1904 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1905 */ 1906 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1907 { 1908 if (!adev->mman.initialized) 1909 return; 1910 1911 amdgpu_ttm_training_reserve_vram_fini(adev); 1912 /* return the stolen vga memory back to VRAM */ 1913 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1914 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1915 /* return the IP Discovery TMR memory back to VRAM */ 1916 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1917 amdgpu_ttm_fw_reserve_vram_fini(adev); 1918 1919 if (adev->mman.aper_base_kaddr) 1920 iounmap(adev->mman.aper_base_kaddr); 1921 adev->mman.aper_base_kaddr = NULL; 1922 1923 amdgpu_vram_mgr_fini(adev); 1924 amdgpu_gtt_mgr_fini(adev); 1925 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1926 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1927 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1928 ttm_bo_device_release(&adev->mman.bdev); 1929 adev->mman.initialized = false; 1930 DRM_INFO("amdgpu: ttm finalized\n"); 1931 } 1932 1933 /** 1934 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1935 * 1936 * @adev: amdgpu_device pointer 1937 * @enable: true when we can use buffer functions. 1938 * 1939 * Enable/disable use of buffer functions during suspend/resume. This should 1940 * only be called at bootup or when userspace isn't running. 1941 */ 1942 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1943 { 1944 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1945 uint64_t size; 1946 int r; 1947 1948 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1949 adev->mman.buffer_funcs_enabled == enable) 1950 return; 1951 1952 if (enable) { 1953 struct amdgpu_ring *ring; 1954 struct drm_gpu_scheduler *sched; 1955 1956 ring = adev->mman.buffer_funcs_ring; 1957 sched = &ring->sched; 1958 r = drm_sched_entity_init(&adev->mman.entity, 1959 DRM_SCHED_PRIORITY_KERNEL, &sched, 1960 1, NULL); 1961 if (r) { 1962 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1963 r); 1964 return; 1965 } 1966 } else { 1967 drm_sched_entity_destroy(&adev->mman.entity); 1968 dma_fence_put(man->move); 1969 man->move = NULL; 1970 } 1971 1972 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1973 if (enable) 1974 size = adev->gmc.real_vram_size; 1975 else 1976 size = adev->gmc.visible_vram_size; 1977 man->size = size >> PAGE_SHIFT; 1978 adev->mman.buffer_funcs_enabled = enable; 1979 } 1980 1981 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) 1982 { 1983 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 1984 vm_fault_t ret; 1985 1986 ret = ttm_bo_vm_reserve(bo, vmf); 1987 if (ret) 1988 return ret; 1989 1990 ret = amdgpu_bo_fault_reserve_notify(bo); 1991 if (ret) 1992 goto unlock; 1993 1994 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 1995 TTM_BO_VM_NUM_PREFAULT, 1); 1996 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 1997 return ret; 1998 1999 unlock: 2000 dma_resv_unlock(bo->base.resv); 2001 return ret; 2002 } 2003 2004 static struct vm_operations_struct amdgpu_ttm_vm_ops = { 2005 .fault = amdgpu_ttm_fault, 2006 .open = ttm_bo_vm_open, 2007 .close = ttm_bo_vm_close, 2008 .access = ttm_bo_vm_access 2009 }; 2010 2011 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 2012 { 2013 struct drm_file *file_priv = filp->private_data; 2014 struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); 2015 int r; 2016 2017 r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); 2018 if (unlikely(r != 0)) 2019 return r; 2020 2021 vma->vm_ops = &amdgpu_ttm_vm_ops; 2022 return 0; 2023 } 2024 2025 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2026 uint64_t dst_offset, uint32_t byte_count, 2027 struct dma_resv *resv, 2028 struct dma_fence **fence, bool direct_submit, 2029 bool vm_needs_flush, bool tmz) 2030 { 2031 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 2032 AMDGPU_IB_POOL_DELAYED; 2033 struct amdgpu_device *adev = ring->adev; 2034 struct amdgpu_job *job; 2035 2036 uint32_t max_bytes; 2037 unsigned num_loops, num_dw; 2038 unsigned i; 2039 int r; 2040 2041 if (direct_submit && !ring->sched.ready) { 2042 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2043 return -EINVAL; 2044 } 2045 2046 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2047 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2048 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2049 2050 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 2051 if (r) 2052 return r; 2053 2054 if (vm_needs_flush) { 2055 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 2056 job->vm_needs_flush = true; 2057 } 2058 if (resv) { 2059 r = amdgpu_sync_resv(adev, &job->sync, resv, 2060 AMDGPU_SYNC_ALWAYS, 2061 AMDGPU_FENCE_OWNER_UNDEFINED); 2062 if (r) { 2063 DRM_ERROR("sync failed (%d).\n", r); 2064 goto error_free; 2065 } 2066 } 2067 2068 for (i = 0; i < num_loops; i++) { 2069 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2070 2071 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2072 dst_offset, cur_size_in_bytes, tmz); 2073 2074 src_offset += cur_size_in_bytes; 2075 dst_offset += cur_size_in_bytes; 2076 byte_count -= cur_size_in_bytes; 2077 } 2078 2079 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2080 WARN_ON(job->ibs[0].length_dw > num_dw); 2081 if (direct_submit) 2082 r = amdgpu_job_submit_direct(job, ring, fence); 2083 else 2084 r = amdgpu_job_submit(job, &adev->mman.entity, 2085 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2086 if (r) 2087 goto error_free; 2088 2089 return r; 2090 2091 error_free: 2092 amdgpu_job_free(job); 2093 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2094 return r; 2095 } 2096 2097 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2098 uint32_t src_data, 2099 struct dma_resv *resv, 2100 struct dma_fence **fence) 2101 { 2102 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2103 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2104 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2105 2106 struct drm_mm_node *mm_node; 2107 unsigned long num_pages; 2108 unsigned int num_loops, num_dw; 2109 2110 struct amdgpu_job *job; 2111 int r; 2112 2113 if (!adev->mman.buffer_funcs_enabled) { 2114 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2115 return -EINVAL; 2116 } 2117 2118 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2119 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2120 if (r) 2121 return r; 2122 } 2123 2124 num_pages = bo->tbo.mem.num_pages; 2125 mm_node = bo->tbo.mem.mm_node; 2126 num_loops = 0; 2127 while (num_pages) { 2128 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2129 2130 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); 2131 num_pages -= mm_node->size; 2132 ++mm_node; 2133 } 2134 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2135 2136 /* for IB padding */ 2137 num_dw += 64; 2138 2139 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2140 &job); 2141 if (r) 2142 return r; 2143 2144 if (resv) { 2145 r = amdgpu_sync_resv(adev, &job->sync, resv, 2146 AMDGPU_SYNC_ALWAYS, 2147 AMDGPU_FENCE_OWNER_UNDEFINED); 2148 if (r) { 2149 DRM_ERROR("sync failed (%d).\n", r); 2150 goto error_free; 2151 } 2152 } 2153 2154 num_pages = bo->tbo.mem.num_pages; 2155 mm_node = bo->tbo.mem.mm_node; 2156 2157 while (num_pages) { 2158 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2159 uint64_t dst_addr; 2160 2161 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); 2162 while (byte_count) { 2163 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, 2164 max_bytes); 2165 2166 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 2167 dst_addr, cur_size_in_bytes); 2168 2169 dst_addr += cur_size_in_bytes; 2170 byte_count -= cur_size_in_bytes; 2171 } 2172 2173 num_pages -= mm_node->size; 2174 ++mm_node; 2175 } 2176 2177 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2178 WARN_ON(job->ibs[0].length_dw > num_dw); 2179 r = amdgpu_job_submit(job, &adev->mman.entity, 2180 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2181 if (r) 2182 goto error_free; 2183 2184 return 0; 2185 2186 error_free: 2187 amdgpu_job_free(job); 2188 return r; 2189 } 2190 2191 #if defined(CONFIG_DEBUG_FS) 2192 2193 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2194 { 2195 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2196 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2197 TTM_PL_VRAM); 2198 struct drm_printer p = drm_seq_file_printer(m); 2199 2200 man->func->debug(man, &p); 2201 return 0; 2202 } 2203 2204 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2205 { 2206 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2207 2208 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2209 } 2210 2211 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2212 { 2213 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2214 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2215 TTM_PL_TT); 2216 struct drm_printer p = drm_seq_file_printer(m); 2217 2218 man->func->debug(man, &p); 2219 return 0; 2220 } 2221 2222 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2223 { 2224 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2225 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2226 AMDGPU_PL_GDS); 2227 struct drm_printer p = drm_seq_file_printer(m); 2228 2229 man->func->debug(man, &p); 2230 return 0; 2231 } 2232 2233 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2234 { 2235 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2236 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2237 AMDGPU_PL_GWS); 2238 struct drm_printer p = drm_seq_file_printer(m); 2239 2240 man->func->debug(man, &p); 2241 return 0; 2242 } 2243 2244 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2245 { 2246 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2247 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2248 AMDGPU_PL_OA); 2249 struct drm_printer p = drm_seq_file_printer(m); 2250 2251 man->func->debug(man, &p); 2252 return 0; 2253 } 2254 2255 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2256 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2257 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2258 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2259 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2260 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2261 2262 /* 2263 * amdgpu_ttm_vram_read - Linear read access to VRAM 2264 * 2265 * Accesses VRAM via MMIO for debugging purposes. 2266 */ 2267 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2268 size_t size, loff_t *pos) 2269 { 2270 struct amdgpu_device *adev = file_inode(f)->i_private; 2271 ssize_t result = 0; 2272 2273 if (size & 0x3 || *pos & 0x3) 2274 return -EINVAL; 2275 2276 if (*pos >= adev->gmc.mc_vram_size) 2277 return -ENXIO; 2278 2279 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2280 while (size) { 2281 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2282 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2283 2284 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2285 if (copy_to_user(buf, value, bytes)) 2286 return -EFAULT; 2287 2288 result += bytes; 2289 buf += bytes; 2290 *pos += bytes; 2291 size -= bytes; 2292 } 2293 2294 return result; 2295 } 2296 2297 /* 2298 * amdgpu_ttm_vram_write - Linear write access to VRAM 2299 * 2300 * Accesses VRAM via MMIO for debugging purposes. 2301 */ 2302 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2303 size_t size, loff_t *pos) 2304 { 2305 struct amdgpu_device *adev = file_inode(f)->i_private; 2306 ssize_t result = 0; 2307 int r; 2308 2309 if (size & 0x3 || *pos & 0x3) 2310 return -EINVAL; 2311 2312 if (*pos >= adev->gmc.mc_vram_size) 2313 return -ENXIO; 2314 2315 while (size) { 2316 unsigned long flags; 2317 uint32_t value; 2318 2319 if (*pos >= adev->gmc.mc_vram_size) 2320 return result; 2321 2322 r = get_user(value, (uint32_t *)buf); 2323 if (r) 2324 return r; 2325 2326 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2327 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2328 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2329 WREG32_NO_KIQ(mmMM_DATA, value); 2330 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2331 2332 result += 4; 2333 buf += 4; 2334 *pos += 4; 2335 size -= 4; 2336 } 2337 2338 return result; 2339 } 2340 2341 static const struct file_operations amdgpu_ttm_vram_fops = { 2342 .owner = THIS_MODULE, 2343 .read = amdgpu_ttm_vram_read, 2344 .write = amdgpu_ttm_vram_write, 2345 .llseek = default_llseek, 2346 }; 2347 2348 /* 2349 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2350 * 2351 * This function is used to read memory that has been mapped to the 2352 * GPU and the known addresses are not physical addresses but instead 2353 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2354 */ 2355 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2356 size_t size, loff_t *pos) 2357 { 2358 struct amdgpu_device *adev = file_inode(f)->i_private; 2359 struct iommu_domain *dom; 2360 ssize_t result = 0; 2361 int r; 2362 2363 /* retrieve the IOMMU domain if any for this device */ 2364 dom = iommu_get_domain_for_dev(adev->dev); 2365 2366 while (size) { 2367 phys_addr_t addr = *pos & PAGE_MASK; 2368 loff_t off = *pos & ~PAGE_MASK; 2369 size_t bytes = PAGE_SIZE - off; 2370 unsigned long pfn; 2371 struct page *p; 2372 void *ptr; 2373 2374 bytes = bytes < size ? bytes : size; 2375 2376 /* Translate the bus address to a physical address. If 2377 * the domain is NULL it means there is no IOMMU active 2378 * and the address translation is the identity 2379 */ 2380 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2381 2382 pfn = addr >> PAGE_SHIFT; 2383 if (!pfn_valid(pfn)) 2384 return -EPERM; 2385 2386 p = pfn_to_page(pfn); 2387 if (p->mapping != adev->mman.bdev.dev_mapping) 2388 return -EPERM; 2389 2390 ptr = kmap(p); 2391 r = copy_to_user(buf, ptr + off, bytes); 2392 kunmap(p); 2393 if (r) 2394 return -EFAULT; 2395 2396 size -= bytes; 2397 *pos += bytes; 2398 result += bytes; 2399 } 2400 2401 return result; 2402 } 2403 2404 /* 2405 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2406 * 2407 * This function is used to write memory that has been mapped to the 2408 * GPU and the known addresses are not physical addresses but instead 2409 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2410 */ 2411 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2412 size_t size, loff_t *pos) 2413 { 2414 struct amdgpu_device *adev = file_inode(f)->i_private; 2415 struct iommu_domain *dom; 2416 ssize_t result = 0; 2417 int r; 2418 2419 dom = iommu_get_domain_for_dev(adev->dev); 2420 2421 while (size) { 2422 phys_addr_t addr = *pos & PAGE_MASK; 2423 loff_t off = *pos & ~PAGE_MASK; 2424 size_t bytes = PAGE_SIZE - off; 2425 unsigned long pfn; 2426 struct page *p; 2427 void *ptr; 2428 2429 bytes = bytes < size ? bytes : size; 2430 2431 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2432 2433 pfn = addr >> PAGE_SHIFT; 2434 if (!pfn_valid(pfn)) 2435 return -EPERM; 2436 2437 p = pfn_to_page(pfn); 2438 if (p->mapping != adev->mman.bdev.dev_mapping) 2439 return -EPERM; 2440 2441 ptr = kmap(p); 2442 r = copy_from_user(ptr + off, buf, bytes); 2443 kunmap(p); 2444 if (r) 2445 return -EFAULT; 2446 2447 size -= bytes; 2448 *pos += bytes; 2449 result += bytes; 2450 } 2451 2452 return result; 2453 } 2454 2455 static const struct file_operations amdgpu_ttm_iomem_fops = { 2456 .owner = THIS_MODULE, 2457 .read = amdgpu_iomem_read, 2458 .write = amdgpu_iomem_write, 2459 .llseek = default_llseek 2460 }; 2461 2462 #endif 2463 2464 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2465 { 2466 #if defined(CONFIG_DEBUG_FS) 2467 struct drm_minor *minor = adev_to_drm(adev)->primary; 2468 struct dentry *root = minor->debugfs_root; 2469 2470 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2471 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2472 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2473 &amdgpu_ttm_iomem_fops); 2474 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2475 &amdgpu_mm_vram_table_fops); 2476 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2477 &amdgpu_mm_tt_table_fops); 2478 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2479 &amdgpu_mm_gds_table_fops); 2480 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2481 &amdgpu_mm_gws_table_fops); 2482 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2483 &amdgpu_mm_oa_table_fops); 2484 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2485 &amdgpu_ttm_page_pool_fops); 2486 #endif 2487 } 2488