1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 45 #include <drm/ttm/ttm_bo_api.h> 46 #include <drm/ttm/ttm_bo_driver.h> 47 #include <drm/ttm/ttm_placement.h> 48 49 #include <drm/amdgpu_drm.h> 50 51 #include "amdgpu.h" 52 #include "amdgpu_object.h" 53 #include "amdgpu_trace.h" 54 #include "amdgpu_amdkfd.h" 55 #include "amdgpu_sdma.h" 56 #include "amdgpu_ras.h" 57 #include "amdgpu_atomfirmware.h" 58 #include "amdgpu_res_cursor.h" 59 #include "bif/bif_4_1_d.h" 60 61 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 62 63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 64 struct ttm_tt *ttm, 65 struct ttm_resource *bo_mem); 66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 67 struct ttm_tt *ttm); 68 69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 70 unsigned int type, 71 uint64_t size_in_page) 72 { 73 return ttm_range_man_init(&adev->mman.bdev, type, 74 false, size_in_page); 75 } 76 77 /** 78 * amdgpu_evict_flags - Compute placement flags 79 * 80 * @bo: The buffer object to evict 81 * @placement: Possible destination(s) for evicted BO 82 * 83 * Fill in placement data when ttm_bo_evict() is called 84 */ 85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 86 struct ttm_placement *placement) 87 { 88 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 89 struct amdgpu_bo *abo; 90 static const struct ttm_place placements = { 91 .fpfn = 0, 92 .lpfn = 0, 93 .mem_type = TTM_PL_SYSTEM, 94 .flags = 0 95 }; 96 97 /* Don't handle scatter gather BOs */ 98 if (bo->type == ttm_bo_type_sg) { 99 placement->num_placement = 0; 100 placement->num_busy_placement = 0; 101 return; 102 } 103 104 /* Object isn't an AMDGPU object so ignore */ 105 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 106 placement->placement = &placements; 107 placement->busy_placement = &placements; 108 placement->num_placement = 1; 109 placement->num_busy_placement = 1; 110 return; 111 } 112 113 abo = ttm_to_amdgpu_bo(bo); 114 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 115 struct dma_fence *fence; 116 struct dma_resv *resv = &bo->base._resv; 117 118 rcu_read_lock(); 119 fence = rcu_dereference(resv->fence_excl); 120 if (fence && !fence->ops->signaled) 121 dma_fence_enable_sw_signaling(fence); 122 123 placement->num_placement = 0; 124 placement->num_busy_placement = 0; 125 rcu_read_unlock(); 126 return; 127 } 128 switch (bo->mem.mem_type) { 129 case AMDGPU_PL_GDS: 130 case AMDGPU_PL_GWS: 131 case AMDGPU_PL_OA: 132 placement->num_placement = 0; 133 placement->num_busy_placement = 0; 134 return; 135 136 case TTM_PL_VRAM: 137 if (!adev->mman.buffer_funcs_enabled) { 138 /* Move to system memory */ 139 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 140 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 141 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 142 amdgpu_bo_in_cpu_visible_vram(abo)) { 143 144 /* Try evicting to the CPU inaccessible part of VRAM 145 * first, but only set GTT as busy placement, so this 146 * BO will be evicted to GTT rather than causing other 147 * BOs to be evicted from VRAM 148 */ 149 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 150 AMDGPU_GEM_DOMAIN_GTT); 151 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 152 abo->placements[0].lpfn = 0; 153 abo->placement.busy_placement = &abo->placements[1]; 154 abo->placement.num_busy_placement = 1; 155 } else { 156 /* Move to GTT memory */ 157 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 158 } 159 break; 160 case TTM_PL_TT: 161 case AMDGPU_PL_PREEMPT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 /** 170 * amdgpu_ttm_map_buffer - Map memory into the GART windows 171 * @bo: buffer object to map 172 * @mem: memory object to map 173 * @mm_cur: range to map 174 * @num_pages: number of pages to map 175 * @window: which GART window to use 176 * @ring: DMA ring to use for the copy 177 * @tmz: if we should setup a TMZ enabled mapping 178 * @addr: resulting address inside the MC address space 179 * 180 * Setup one of the GART windows to access a specific piece of memory or return 181 * the physical address for local memory. 182 */ 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 184 struct ttm_resource *mem, 185 struct amdgpu_res_cursor *mm_cur, 186 unsigned num_pages, unsigned window, 187 struct amdgpu_ring *ring, bool tmz, 188 uint64_t *addr) 189 { 190 struct amdgpu_device *adev = ring->adev; 191 struct amdgpu_job *job; 192 unsigned num_dw, num_bytes; 193 struct dma_fence *fence; 194 uint64_t src_addr, dst_addr; 195 void *cpu_addr; 196 uint64_t flags; 197 unsigned int i; 198 int r; 199 200 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 201 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 202 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); 203 204 /* Map only what can't be accessed directly */ 205 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 206 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 207 mm_cur->start; 208 return 0; 209 } 210 211 *addr = adev->gmc.gart_start; 212 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 213 AMDGPU_GPU_PAGE_SIZE; 214 *addr += mm_cur->start & ~PAGE_MASK; 215 216 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 217 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 218 219 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 220 AMDGPU_IB_POOL_DELAYED, &job); 221 if (r) 222 return r; 223 224 src_addr = num_dw * 4; 225 src_addr += job->ibs[0].gpu_addr; 226 227 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 228 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 229 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 230 dst_addr, num_bytes, false); 231 232 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 233 WARN_ON(job->ibs[0].length_dw > num_dw); 234 235 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 236 if (tmz) 237 flags |= AMDGPU_PTE_TMZ; 238 239 cpu_addr = &job->ibs[0].ptr[num_dw]; 240 241 if (mem->mem_type == TTM_PL_TT) { 242 dma_addr_t *dma_addr; 243 244 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 245 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 246 cpu_addr); 247 if (r) 248 goto error_free; 249 } else { 250 dma_addr_t dma_address; 251 252 dma_address = mm_cur->start; 253 dma_address += adev->vm_manager.vram_base_offset; 254 255 for (i = 0; i < num_pages; ++i) { 256 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 257 &dma_address, flags, cpu_addr); 258 if (r) 259 goto error_free; 260 261 dma_address += PAGE_SIZE; 262 } 263 } 264 265 r = amdgpu_job_submit(job, &adev->mman.entity, 266 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 267 if (r) 268 goto error_free; 269 270 dma_fence_put(fence); 271 272 return r; 273 274 error_free: 275 amdgpu_job_free(job); 276 return r; 277 } 278 279 /** 280 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 281 * @adev: amdgpu device 282 * @src: buffer/address where to read from 283 * @dst: buffer/address where to write to 284 * @size: number of bytes to copy 285 * @tmz: if a secure copy should be used 286 * @resv: resv object to sync to 287 * @f: Returns the last fence if multiple jobs are submitted. 288 * 289 * The function copies @size bytes from {src->mem + src->offset} to 290 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 291 * move and different for a BO to BO copy. 292 * 293 */ 294 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 295 const struct amdgpu_copy_mem *src, 296 const struct amdgpu_copy_mem *dst, 297 uint64_t size, bool tmz, 298 struct dma_resv *resv, 299 struct dma_fence **f) 300 { 301 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 302 AMDGPU_GPU_PAGE_SIZE); 303 304 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 305 struct amdgpu_res_cursor src_mm, dst_mm; 306 struct dma_fence *fence = NULL; 307 int r = 0; 308 309 if (!adev->mman.buffer_funcs_enabled) { 310 DRM_ERROR("Trying to move memory with ring turned off.\n"); 311 return -EINVAL; 312 } 313 314 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 315 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 316 317 mutex_lock(&adev->mman.gtt_window_lock); 318 while (src_mm.remaining) { 319 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 320 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 321 struct dma_fence *next; 322 uint32_t cur_size; 323 uint64_t from, to; 324 325 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 326 * begins at an offset, then adjust the size accordingly 327 */ 328 cur_size = max(src_page_offset, dst_page_offset); 329 cur_size = min(min3(src_mm.size, dst_mm.size, size), 330 (uint64_t)(GTT_MAX_BYTES - cur_size)); 331 332 /* Map src to window 0 and dst to window 1. */ 333 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 334 PFN_UP(cur_size + src_page_offset), 335 0, ring, tmz, &from); 336 if (r) 337 goto error; 338 339 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 340 PFN_UP(cur_size + dst_page_offset), 341 1, ring, tmz, &to); 342 if (r) 343 goto error; 344 345 r = amdgpu_copy_buffer(ring, from, to, cur_size, 346 resv, &next, false, true, tmz); 347 if (r) 348 goto error; 349 350 dma_fence_put(fence); 351 fence = next; 352 353 amdgpu_res_next(&src_mm, cur_size); 354 amdgpu_res_next(&dst_mm, cur_size); 355 } 356 error: 357 mutex_unlock(&adev->mman.gtt_window_lock); 358 if (f) 359 *f = dma_fence_get(fence); 360 dma_fence_put(fence); 361 return r; 362 } 363 364 /* 365 * amdgpu_move_blit - Copy an entire buffer to another buffer 366 * 367 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 368 * help move buffers to and from VRAM. 369 */ 370 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 371 bool evict, 372 struct ttm_resource *new_mem, 373 struct ttm_resource *old_mem) 374 { 375 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 376 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 377 struct amdgpu_copy_mem src, dst; 378 struct dma_fence *fence = NULL; 379 int r; 380 381 src.bo = bo; 382 dst.bo = bo; 383 src.mem = old_mem; 384 dst.mem = new_mem; 385 src.offset = 0; 386 dst.offset = 0; 387 388 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 389 new_mem->num_pages << PAGE_SHIFT, 390 amdgpu_bo_encrypted(abo), 391 bo->base.resv, &fence); 392 if (r) 393 goto error; 394 395 /* clear the space being freed */ 396 if (old_mem->mem_type == TTM_PL_VRAM && 397 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 398 struct dma_fence *wipe_fence = NULL; 399 400 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 401 NULL, &wipe_fence); 402 if (r) { 403 goto error; 404 } else if (wipe_fence) { 405 dma_fence_put(fence); 406 fence = wipe_fence; 407 } 408 } 409 410 /* Always block for VM page tables before committing the new location */ 411 if (bo->type == ttm_bo_type_kernel) 412 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 413 else 414 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 415 dma_fence_put(fence); 416 return r; 417 418 error: 419 if (fence) 420 dma_fence_wait(fence, false); 421 dma_fence_put(fence); 422 return r; 423 } 424 425 /* 426 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 427 * 428 * Called by amdgpu_bo_move() 429 */ 430 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 431 struct ttm_resource *mem) 432 { 433 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 434 struct amdgpu_res_cursor cursor; 435 436 if (mem->mem_type == TTM_PL_SYSTEM || 437 mem->mem_type == TTM_PL_TT) 438 return true; 439 if (mem->mem_type != TTM_PL_VRAM) 440 return false; 441 442 amdgpu_res_first(mem, 0, mem_size, &cursor); 443 444 /* ttm_resource_ioremap only supports contiguous memory */ 445 if (cursor.size != mem_size) 446 return false; 447 448 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 449 } 450 451 /* 452 * amdgpu_bo_move - Move a buffer object to a new memory location 453 * 454 * Called by ttm_bo_handle_move_mem() 455 */ 456 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 457 struct ttm_operation_ctx *ctx, 458 struct ttm_resource *new_mem, 459 struct ttm_place *hop) 460 { 461 struct amdgpu_device *adev; 462 struct amdgpu_bo *abo; 463 struct ttm_resource *old_mem = &bo->mem; 464 int r; 465 466 if (new_mem->mem_type == TTM_PL_TT || 467 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 468 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 469 if (r) 470 return r; 471 } 472 473 /* Can't move a pinned BO */ 474 abo = ttm_to_amdgpu_bo(bo); 475 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 476 return -EINVAL; 477 478 adev = amdgpu_ttm_adev(bo->bdev); 479 480 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 481 ttm_bo_move_null(bo, new_mem); 482 goto out; 483 } 484 if (old_mem->mem_type == TTM_PL_SYSTEM && 485 (new_mem->mem_type == TTM_PL_TT || 486 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 487 ttm_bo_move_null(bo, new_mem); 488 goto out; 489 } 490 if ((old_mem->mem_type == TTM_PL_TT || 491 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 492 new_mem->mem_type == TTM_PL_SYSTEM) { 493 r = ttm_bo_wait_ctx(bo, ctx); 494 if (r) 495 return r; 496 497 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 498 ttm_resource_free(bo, &bo->mem); 499 ttm_bo_assign_mem(bo, new_mem); 500 goto out; 501 } 502 503 if (old_mem->mem_type == AMDGPU_PL_GDS || 504 old_mem->mem_type == AMDGPU_PL_GWS || 505 old_mem->mem_type == AMDGPU_PL_OA || 506 new_mem->mem_type == AMDGPU_PL_GDS || 507 new_mem->mem_type == AMDGPU_PL_GWS || 508 new_mem->mem_type == AMDGPU_PL_OA) { 509 /* Nothing to save here */ 510 ttm_bo_move_null(bo, new_mem); 511 goto out; 512 } 513 514 if (adev->mman.buffer_funcs_enabled) { 515 if (((old_mem->mem_type == TTM_PL_SYSTEM && 516 new_mem->mem_type == TTM_PL_VRAM) || 517 (old_mem->mem_type == TTM_PL_VRAM && 518 new_mem->mem_type == TTM_PL_SYSTEM))) { 519 hop->fpfn = 0; 520 hop->lpfn = 0; 521 hop->mem_type = TTM_PL_TT; 522 hop->flags = 0; 523 return -EMULTIHOP; 524 } 525 526 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 527 } else { 528 r = -ENODEV; 529 } 530 531 if (r) { 532 /* Check that all memory is CPU accessible */ 533 if (!amdgpu_mem_visible(adev, old_mem) || 534 !amdgpu_mem_visible(adev, new_mem)) { 535 pr_err("Move buffer fallback to memcpy unavailable\n"); 536 return r; 537 } 538 539 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 540 if (r) 541 return r; 542 } 543 544 if (bo->type == ttm_bo_type_device && 545 new_mem->mem_type == TTM_PL_VRAM && 546 old_mem->mem_type != TTM_PL_VRAM) { 547 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 548 * accesses the BO after it's moved. 549 */ 550 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 551 } 552 553 out: 554 /* update statistics */ 555 atomic64_add(bo->base.size, &adev->num_bytes_moved); 556 amdgpu_bo_move_notify(bo, evict, new_mem); 557 return 0; 558 } 559 560 /* 561 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 562 * 563 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 564 */ 565 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 566 struct ttm_resource *mem) 567 { 568 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 569 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 570 571 switch (mem->mem_type) { 572 case TTM_PL_SYSTEM: 573 /* system memory */ 574 return 0; 575 case TTM_PL_TT: 576 case AMDGPU_PL_PREEMPT: 577 break; 578 case TTM_PL_VRAM: 579 mem->bus.offset = mem->start << PAGE_SHIFT; 580 /* check if it's visible */ 581 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 582 return -EINVAL; 583 584 if (adev->mman.aper_base_kaddr && 585 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 586 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 587 mem->bus.offset; 588 589 mem->bus.offset += adev->gmc.aper_base; 590 mem->bus.is_iomem = true; 591 if (adev->gmc.xgmi.connected_to_cpu) 592 mem->bus.caching = ttm_cached; 593 else 594 mem->bus.caching = ttm_write_combined; 595 break; 596 default: 597 return -EINVAL; 598 } 599 return 0; 600 } 601 602 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 603 unsigned long page_offset) 604 { 605 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 606 struct amdgpu_res_cursor cursor; 607 608 amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor); 609 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 610 } 611 612 /** 613 * amdgpu_ttm_domain_start - Returns GPU start address 614 * @adev: amdgpu device object 615 * @type: type of the memory 616 * 617 * Returns: 618 * GPU start address of a memory domain 619 */ 620 621 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 622 { 623 switch (type) { 624 case TTM_PL_TT: 625 return adev->gmc.gart_start; 626 case TTM_PL_VRAM: 627 return adev->gmc.vram_start; 628 } 629 630 return 0; 631 } 632 633 /* 634 * TTM backend functions. 635 */ 636 struct amdgpu_ttm_tt { 637 struct ttm_tt ttm; 638 struct drm_gem_object *gobj; 639 u64 offset; 640 uint64_t userptr; 641 struct task_struct *usertask; 642 uint32_t userflags; 643 bool bound; 644 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 645 struct hmm_range *range; 646 #endif 647 }; 648 649 #ifdef CONFIG_DRM_AMDGPU_USERPTR 650 /* 651 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 652 * memory and start HMM tracking CPU page table update 653 * 654 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 655 * once afterwards to stop HMM tracking 656 */ 657 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 658 { 659 struct ttm_tt *ttm = bo->tbo.ttm; 660 struct amdgpu_ttm_tt *gtt = (void *)ttm; 661 unsigned long start = gtt->userptr; 662 struct vm_area_struct *vma; 663 struct mm_struct *mm; 664 bool readonly; 665 int r = 0; 666 667 mm = bo->notifier.mm; 668 if (unlikely(!mm)) { 669 DRM_DEBUG_DRIVER("BO is not registered?\n"); 670 return -EFAULT; 671 } 672 673 /* Another get_user_pages is running at the same time?? */ 674 if (WARN_ON(gtt->range)) 675 return -EFAULT; 676 677 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 678 return -ESRCH; 679 680 mmap_read_lock(mm); 681 vma = find_vma(mm, start); 682 mmap_read_unlock(mm); 683 if (unlikely(!vma || start < vma->vm_start)) { 684 r = -EFAULT; 685 goto out_putmm; 686 } 687 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 688 vma->vm_file)) { 689 r = -EPERM; 690 goto out_putmm; 691 } 692 693 readonly = amdgpu_ttm_tt_is_readonly(ttm); 694 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 695 ttm->num_pages, >t->range, readonly, 696 false); 697 out_putmm: 698 mmput(mm); 699 700 return r; 701 } 702 703 /* 704 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 705 * Check if the pages backing this ttm range have been invalidated 706 * 707 * Returns: true if pages are still valid 708 */ 709 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 710 { 711 struct amdgpu_ttm_tt *gtt = (void *)ttm; 712 bool r = false; 713 714 if (!gtt || !gtt->userptr) 715 return false; 716 717 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 718 gtt->userptr, ttm->num_pages); 719 720 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 721 "No user pages to check\n"); 722 723 if (gtt->range) { 724 /* 725 * FIXME: Must always hold notifier_lock for this, and must 726 * not ignore the return code. 727 */ 728 r = amdgpu_hmm_range_get_pages_done(gtt->range); 729 gtt->range = NULL; 730 } 731 732 return !r; 733 } 734 #endif 735 736 /* 737 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 738 * 739 * Called by amdgpu_cs_list_validate(). This creates the page list 740 * that backs user memory and will ultimately be mapped into the device 741 * address space. 742 */ 743 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 744 { 745 unsigned long i; 746 747 for (i = 0; i < ttm->num_pages; ++i) 748 ttm->pages[i] = pages ? pages[i] : NULL; 749 } 750 751 /* 752 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 753 * 754 * Called by amdgpu_ttm_backend_bind() 755 **/ 756 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 757 struct ttm_tt *ttm) 758 { 759 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 760 struct amdgpu_ttm_tt *gtt = (void *)ttm; 761 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 762 enum dma_data_direction direction = write ? 763 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 764 int r; 765 766 /* Allocate an SG array and squash pages into it */ 767 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 768 (u64)ttm->num_pages << PAGE_SHIFT, 769 GFP_KERNEL); 770 if (r) 771 goto release_sg; 772 773 /* Map SG to device */ 774 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 775 if (r) 776 goto release_sg; 777 778 /* convert SG to linear array of pages and dma addresses */ 779 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 780 ttm->num_pages); 781 782 return 0; 783 784 release_sg: 785 kfree(ttm->sg); 786 ttm->sg = NULL; 787 return r; 788 } 789 790 /* 791 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 792 */ 793 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 794 struct ttm_tt *ttm) 795 { 796 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 797 struct amdgpu_ttm_tt *gtt = (void *)ttm; 798 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 799 enum dma_data_direction direction = write ? 800 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 801 802 /* double check that we don't free the table twice */ 803 if (!ttm->sg || !ttm->sg->sgl) 804 return; 805 806 /* unmap the pages mapped to the device */ 807 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 808 sg_free_table(ttm->sg); 809 810 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 811 if (gtt->range) { 812 unsigned long i; 813 814 for (i = 0; i < ttm->num_pages; i++) { 815 if (ttm->pages[i] != 816 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 817 break; 818 } 819 820 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 821 } 822 #endif 823 } 824 825 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 826 struct ttm_buffer_object *tbo, 827 uint64_t flags) 828 { 829 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 830 struct ttm_tt *ttm = tbo->ttm; 831 struct amdgpu_ttm_tt *gtt = (void *)ttm; 832 int r; 833 834 if (amdgpu_bo_encrypted(abo)) 835 flags |= AMDGPU_PTE_TMZ; 836 837 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 838 uint64_t page_idx = 1; 839 840 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 841 ttm->pages, gtt->ttm.dma_address, flags); 842 if (r) 843 goto gart_bind_fail; 844 845 /* The memory type of the first page defaults to UC. Now 846 * modify the memory type to NC from the second page of 847 * the BO onward. 848 */ 849 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 850 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 851 852 r = amdgpu_gart_bind(adev, 853 gtt->offset + (page_idx << PAGE_SHIFT), 854 ttm->num_pages - page_idx, 855 &ttm->pages[page_idx], 856 &(gtt->ttm.dma_address[page_idx]), flags); 857 } else { 858 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 859 ttm->pages, gtt->ttm.dma_address, flags); 860 } 861 862 gart_bind_fail: 863 if (r) 864 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 865 ttm->num_pages, gtt->offset); 866 867 return r; 868 } 869 870 /* 871 * amdgpu_ttm_backend_bind - Bind GTT memory 872 * 873 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 874 * This handles binding GTT memory to the device address space. 875 */ 876 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 877 struct ttm_tt *ttm, 878 struct ttm_resource *bo_mem) 879 { 880 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 881 struct amdgpu_ttm_tt *gtt = (void*)ttm; 882 uint64_t flags; 883 int r = 0; 884 885 if (!bo_mem) 886 return -EINVAL; 887 888 if (gtt->bound) 889 return 0; 890 891 if (gtt->userptr) { 892 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 893 if (r) { 894 DRM_ERROR("failed to pin userptr\n"); 895 return r; 896 } 897 } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 898 if (!ttm->sg) { 899 struct dma_buf_attachment *attach; 900 struct sg_table *sgt; 901 902 attach = gtt->gobj->import_attach; 903 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 904 if (IS_ERR(sgt)) 905 return PTR_ERR(sgt); 906 907 ttm->sg = sgt; 908 } 909 910 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 911 ttm->num_pages); 912 } 913 914 if (!ttm->num_pages) { 915 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 916 ttm->num_pages, bo_mem, ttm); 917 } 918 919 if (bo_mem->mem_type == AMDGPU_PL_GDS || 920 bo_mem->mem_type == AMDGPU_PL_GWS || 921 bo_mem->mem_type == AMDGPU_PL_OA) 922 return -EINVAL; 923 924 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 925 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 926 return 0; 927 } 928 929 /* compute PTE flags relevant to this BO memory */ 930 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 931 932 /* bind pages into GART page tables */ 933 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 934 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 935 ttm->pages, gtt->ttm.dma_address, flags); 936 937 if (r) 938 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 939 ttm->num_pages, gtt->offset); 940 gtt->bound = true; 941 return r; 942 } 943 944 /* 945 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 946 * through AGP or GART aperture. 947 * 948 * If bo is accessible through AGP aperture, then use AGP aperture 949 * to access bo; otherwise allocate logical space in GART aperture 950 * and map bo to GART aperture. 951 */ 952 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 953 { 954 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 955 struct ttm_operation_ctx ctx = { false, false }; 956 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 957 struct ttm_resource tmp; 958 struct ttm_placement placement; 959 struct ttm_place placements; 960 uint64_t addr, flags; 961 int r; 962 963 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 964 return 0; 965 966 addr = amdgpu_gmc_agp_addr(bo); 967 if (addr != AMDGPU_BO_INVALID_OFFSET) { 968 bo->mem.start = addr >> PAGE_SHIFT; 969 } else { 970 971 /* allocate GART space */ 972 placement.num_placement = 1; 973 placement.placement = &placements; 974 placement.num_busy_placement = 1; 975 placement.busy_placement = &placements; 976 placements.fpfn = 0; 977 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 978 placements.mem_type = TTM_PL_TT; 979 placements.flags = bo->mem.placement; 980 981 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 982 if (unlikely(r)) 983 return r; 984 985 /* compute PTE flags for this buffer object */ 986 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 987 988 /* Bind pages */ 989 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 990 r = amdgpu_ttm_gart_bind(adev, bo, flags); 991 if (unlikely(r)) { 992 ttm_resource_free(bo, &tmp); 993 return r; 994 } 995 996 amdgpu_gart_invalidate_tlb(adev); 997 ttm_resource_free(bo, &bo->mem); 998 bo->mem = tmp; 999 } 1000 1001 return 0; 1002 } 1003 1004 /* 1005 * amdgpu_ttm_recover_gart - Rebind GTT pages 1006 * 1007 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1008 * rebind GTT pages during a GPU reset. 1009 */ 1010 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1011 { 1012 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1013 uint64_t flags; 1014 int r; 1015 1016 if (!tbo->ttm) 1017 return 0; 1018 1019 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1020 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1021 1022 return r; 1023 } 1024 1025 /* 1026 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1027 * 1028 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1029 * ttm_tt_destroy(). 1030 */ 1031 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1032 struct ttm_tt *ttm) 1033 { 1034 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1035 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1036 int r; 1037 1038 /* if the pages have userptr pinning then clear that first */ 1039 if (gtt->userptr) { 1040 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1041 } else if (ttm->sg && gtt->gobj->import_attach) { 1042 struct dma_buf_attachment *attach; 1043 1044 attach = gtt->gobj->import_attach; 1045 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1046 ttm->sg = NULL; 1047 } 1048 1049 if (!gtt->bound) 1050 return; 1051 1052 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1053 return; 1054 1055 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1056 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1057 if (r) 1058 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1059 gtt->ttm.num_pages, gtt->offset); 1060 gtt->bound = false; 1061 } 1062 1063 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1064 struct ttm_tt *ttm) 1065 { 1066 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1067 1068 amdgpu_ttm_backend_unbind(bdev, ttm); 1069 ttm_tt_destroy_common(bdev, ttm); 1070 if (gtt->usertask) 1071 put_task_struct(gtt->usertask); 1072 1073 ttm_tt_fini(>t->ttm); 1074 kfree(gtt); 1075 } 1076 1077 /** 1078 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1079 * 1080 * @bo: The buffer object to create a GTT ttm_tt object around 1081 * @page_flags: Page flags to be added to the ttm_tt object 1082 * 1083 * Called by ttm_tt_create(). 1084 */ 1085 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1086 uint32_t page_flags) 1087 { 1088 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1089 struct amdgpu_ttm_tt *gtt; 1090 enum ttm_caching caching; 1091 1092 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1093 if (gtt == NULL) { 1094 return NULL; 1095 } 1096 gtt->gobj = &bo->base; 1097 1098 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1099 caching = ttm_write_combined; 1100 else 1101 caching = ttm_cached; 1102 1103 /* allocate space for the uninitialized page entries */ 1104 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1105 kfree(gtt); 1106 return NULL; 1107 } 1108 return >t->ttm; 1109 } 1110 1111 /* 1112 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1113 * 1114 * Map the pages of a ttm_tt object to an address space visible 1115 * to the underlying device. 1116 */ 1117 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1118 struct ttm_tt *ttm, 1119 struct ttm_operation_ctx *ctx) 1120 { 1121 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1122 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1123 1124 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1125 if (gtt && gtt->userptr) { 1126 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1127 if (!ttm->sg) 1128 return -ENOMEM; 1129 1130 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1131 return 0; 1132 } 1133 1134 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1135 return 0; 1136 1137 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1138 } 1139 1140 /* 1141 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1142 * 1143 * Unmaps pages of a ttm_tt object from the device address space and 1144 * unpopulates the page array backing it. 1145 */ 1146 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1147 struct ttm_tt *ttm) 1148 { 1149 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1150 struct amdgpu_device *adev; 1151 1152 if (gtt && gtt->userptr) { 1153 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1154 kfree(ttm->sg); 1155 ttm->sg = NULL; 1156 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1157 return; 1158 } 1159 1160 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1161 return; 1162 1163 adev = amdgpu_ttm_adev(bdev); 1164 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1165 } 1166 1167 /** 1168 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1169 * task 1170 * 1171 * @bo: The ttm_buffer_object to bind this userptr to 1172 * @addr: The address in the current tasks VM space to use 1173 * @flags: Requirements of userptr object. 1174 * 1175 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1176 * to current task 1177 */ 1178 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1179 uint64_t addr, uint32_t flags) 1180 { 1181 struct amdgpu_ttm_tt *gtt; 1182 1183 if (!bo->ttm) { 1184 /* TODO: We want a separate TTM object type for userptrs */ 1185 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1186 if (bo->ttm == NULL) 1187 return -ENOMEM; 1188 } 1189 1190 gtt = (void *)bo->ttm; 1191 gtt->userptr = addr; 1192 gtt->userflags = flags; 1193 1194 if (gtt->usertask) 1195 put_task_struct(gtt->usertask); 1196 gtt->usertask = current->group_leader; 1197 get_task_struct(gtt->usertask); 1198 1199 return 0; 1200 } 1201 1202 /* 1203 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1204 */ 1205 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1206 { 1207 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1208 1209 if (gtt == NULL) 1210 return NULL; 1211 1212 if (gtt->usertask == NULL) 1213 return NULL; 1214 1215 return gtt->usertask->mm; 1216 } 1217 1218 /* 1219 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1220 * address range for the current task. 1221 * 1222 */ 1223 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1224 unsigned long end) 1225 { 1226 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1227 unsigned long size; 1228 1229 if (gtt == NULL || !gtt->userptr) 1230 return false; 1231 1232 /* Return false if no part of the ttm_tt object lies within 1233 * the range 1234 */ 1235 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1236 if (gtt->userptr > end || gtt->userptr + size <= start) 1237 return false; 1238 1239 return true; 1240 } 1241 1242 /* 1243 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1244 */ 1245 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1246 { 1247 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1248 1249 if (gtt == NULL || !gtt->userptr) 1250 return false; 1251 1252 return true; 1253 } 1254 1255 /* 1256 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1257 */ 1258 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1259 { 1260 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1261 1262 if (gtt == NULL) 1263 return false; 1264 1265 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1266 } 1267 1268 /** 1269 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1270 * 1271 * @ttm: The ttm_tt object to compute the flags for 1272 * @mem: The memory registry backing this ttm_tt object 1273 * 1274 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1275 */ 1276 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1277 { 1278 uint64_t flags = 0; 1279 1280 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1281 flags |= AMDGPU_PTE_VALID; 1282 1283 if (mem && (mem->mem_type == TTM_PL_TT || 1284 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1285 flags |= AMDGPU_PTE_SYSTEM; 1286 1287 if (ttm->caching == ttm_cached) 1288 flags |= AMDGPU_PTE_SNOOPED; 1289 } 1290 1291 if (mem && mem->mem_type == TTM_PL_VRAM && 1292 mem->bus.caching == ttm_cached) 1293 flags |= AMDGPU_PTE_SNOOPED; 1294 1295 return flags; 1296 } 1297 1298 /** 1299 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1300 * 1301 * @adev: amdgpu_device pointer 1302 * @ttm: The ttm_tt object to compute the flags for 1303 * @mem: The memory registry backing this ttm_tt object 1304 * 1305 * Figure out the flags to use for a VM PTE (Page Table Entry). 1306 */ 1307 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1308 struct ttm_resource *mem) 1309 { 1310 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1311 1312 flags |= adev->gart.gart_pte_flags; 1313 flags |= AMDGPU_PTE_READABLE; 1314 1315 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1316 flags |= AMDGPU_PTE_WRITEABLE; 1317 1318 return flags; 1319 } 1320 1321 /* 1322 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1323 * object. 1324 * 1325 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1326 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1327 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1328 * used to clean out a memory space. 1329 */ 1330 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1331 const struct ttm_place *place) 1332 { 1333 unsigned long num_pages = bo->mem.num_pages; 1334 struct amdgpu_res_cursor cursor; 1335 struct dma_resv_list *flist; 1336 struct dma_fence *f; 1337 int i; 1338 1339 if (bo->type == ttm_bo_type_kernel && 1340 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1341 return false; 1342 1343 /* If bo is a KFD BO, check if the bo belongs to the current process. 1344 * If true, then return false as any KFD process needs all its BOs to 1345 * be resident to run successfully 1346 */ 1347 flist = dma_resv_get_list(bo->base.resv); 1348 if (flist) { 1349 for (i = 0; i < flist->shared_count; ++i) { 1350 f = rcu_dereference_protected(flist->shared[i], 1351 dma_resv_held(bo->base.resv)); 1352 if (amdkfd_fence_check_mm(f, current->mm)) 1353 return false; 1354 } 1355 } 1356 1357 switch (bo->mem.mem_type) { 1358 case AMDGPU_PL_PREEMPT: 1359 /* Preemptible BOs don't own system resources managed by the 1360 * driver (pages, VRAM, GART space). They point to resources 1361 * owned by someone else (e.g. pageable memory in user mode 1362 * or a DMABuf). They are used in a preemptible context so we 1363 * can guarantee no deadlocks and good QoS in case of MMU 1364 * notifiers or DMABuf move notifiers from the resource owner. 1365 */ 1366 return false; 1367 case TTM_PL_TT: 1368 if (amdgpu_bo_is_amdgpu_bo(bo) && 1369 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1370 return false; 1371 return true; 1372 1373 case TTM_PL_VRAM: 1374 /* Check each drm MM node individually */ 1375 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT, 1376 &cursor); 1377 while (cursor.remaining) { 1378 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1379 && !(place->lpfn && 1380 place->lpfn <= PFN_DOWN(cursor.start))) 1381 return true; 1382 1383 amdgpu_res_next(&cursor, cursor.size); 1384 } 1385 return false; 1386 1387 default: 1388 break; 1389 } 1390 1391 return ttm_bo_eviction_valuable(bo, place); 1392 } 1393 1394 /** 1395 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1396 * 1397 * @bo: The buffer object to read/write 1398 * @offset: Offset into buffer object 1399 * @buf: Secondary buffer to write/read from 1400 * @len: Length in bytes of access 1401 * @write: true if writing 1402 * 1403 * This is used to access VRAM that backs a buffer object via MMIO 1404 * access for debugging purposes. 1405 */ 1406 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1407 unsigned long offset, void *buf, int len, 1408 int write) 1409 { 1410 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1411 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1412 struct amdgpu_res_cursor cursor; 1413 unsigned long flags; 1414 uint32_t value = 0; 1415 int ret = 0; 1416 1417 if (bo->mem.mem_type != TTM_PL_VRAM) 1418 return -EIO; 1419 1420 amdgpu_res_first(&bo->mem, offset, len, &cursor); 1421 while (cursor.remaining) { 1422 uint64_t aligned_pos = cursor.start & ~(uint64_t)3; 1423 uint64_t bytes = 4 - (cursor.start & 3); 1424 uint32_t shift = (cursor.start & 3) * 8; 1425 uint32_t mask = 0xffffffff << shift; 1426 1427 if (cursor.size < bytes) { 1428 mask &= 0xffffffff >> (bytes - cursor.size) * 8; 1429 bytes = cursor.size; 1430 } 1431 1432 if (mask != 0xffffffff) { 1433 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1434 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1435 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1436 value = RREG32_NO_KIQ(mmMM_DATA); 1437 if (write) { 1438 value &= ~mask; 1439 value |= (*(uint32_t *)buf << shift) & mask; 1440 WREG32_NO_KIQ(mmMM_DATA, value); 1441 } 1442 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1443 if (!write) { 1444 value = (value & mask) >> shift; 1445 memcpy(buf, &value, bytes); 1446 } 1447 } else { 1448 bytes = cursor.size & ~0x3ULL; 1449 amdgpu_device_vram_access(adev, cursor.start, 1450 (uint32_t *)buf, bytes, 1451 write); 1452 } 1453 1454 ret += bytes; 1455 buf = (uint8_t *)buf + bytes; 1456 amdgpu_res_next(&cursor, bytes); 1457 } 1458 1459 return ret; 1460 } 1461 1462 static void 1463 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1464 { 1465 amdgpu_bo_move_notify(bo, false, NULL); 1466 } 1467 1468 static struct ttm_device_funcs amdgpu_bo_driver = { 1469 .ttm_tt_create = &amdgpu_ttm_tt_create, 1470 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1471 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1472 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1473 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1474 .evict_flags = &amdgpu_evict_flags, 1475 .move = &amdgpu_bo_move, 1476 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1477 .release_notify = &amdgpu_bo_release_notify, 1478 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1479 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1480 .access_memory = &amdgpu_ttm_access_memory, 1481 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1482 }; 1483 1484 /* 1485 * Firmware Reservation functions 1486 */ 1487 /** 1488 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1489 * 1490 * @adev: amdgpu_device pointer 1491 * 1492 * free fw reserved vram if it has been reserved. 1493 */ 1494 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1495 { 1496 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1497 NULL, &adev->mman.fw_vram_usage_va); 1498 } 1499 1500 /** 1501 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1502 * 1503 * @adev: amdgpu_device pointer 1504 * 1505 * create bo vram reservation from fw. 1506 */ 1507 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1508 { 1509 uint64_t vram_size = adev->gmc.visible_vram_size; 1510 1511 adev->mman.fw_vram_usage_va = NULL; 1512 adev->mman.fw_vram_usage_reserved_bo = NULL; 1513 1514 if (adev->mman.fw_vram_usage_size == 0 || 1515 adev->mman.fw_vram_usage_size > vram_size) 1516 return 0; 1517 1518 return amdgpu_bo_create_kernel_at(adev, 1519 adev->mman.fw_vram_usage_start_offset, 1520 adev->mman.fw_vram_usage_size, 1521 AMDGPU_GEM_DOMAIN_VRAM, 1522 &adev->mman.fw_vram_usage_reserved_bo, 1523 &adev->mman.fw_vram_usage_va); 1524 } 1525 1526 /* 1527 * Memoy training reservation functions 1528 */ 1529 1530 /** 1531 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1532 * 1533 * @adev: amdgpu_device pointer 1534 * 1535 * free memory training reserved vram if it has been reserved. 1536 */ 1537 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1538 { 1539 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1540 1541 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1542 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1543 ctx->c2p_bo = NULL; 1544 1545 return 0; 1546 } 1547 1548 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1549 { 1550 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1551 1552 memset(ctx, 0, sizeof(*ctx)); 1553 1554 ctx->c2p_train_data_offset = 1555 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1556 ctx->p2c_train_data_offset = 1557 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1558 ctx->train_data_size = 1559 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1560 1561 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1562 ctx->train_data_size, 1563 ctx->p2c_train_data_offset, 1564 ctx->c2p_train_data_offset); 1565 } 1566 1567 /* 1568 * reserve TMR memory at the top of VRAM which holds 1569 * IP Discovery data and is protected by PSP. 1570 */ 1571 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1572 { 1573 int ret; 1574 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1575 bool mem_train_support = false; 1576 1577 if (!amdgpu_sriov_vf(adev)) { 1578 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1579 mem_train_support = true; 1580 else 1581 DRM_DEBUG("memory training does not support!\n"); 1582 } 1583 1584 /* 1585 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1586 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1587 * 1588 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1589 * discovery data and G6 memory training data respectively 1590 */ 1591 adev->mman.discovery_tmr_size = 1592 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1593 if (!adev->mman.discovery_tmr_size) 1594 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1595 1596 if (mem_train_support) { 1597 /* reserve vram for mem train according to TMR location */ 1598 amdgpu_ttm_training_data_block_init(adev); 1599 ret = amdgpu_bo_create_kernel_at(adev, 1600 ctx->c2p_train_data_offset, 1601 ctx->train_data_size, 1602 AMDGPU_GEM_DOMAIN_VRAM, 1603 &ctx->c2p_bo, 1604 NULL); 1605 if (ret) { 1606 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1607 amdgpu_ttm_training_reserve_vram_fini(adev); 1608 return ret; 1609 } 1610 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1611 } 1612 1613 ret = amdgpu_bo_create_kernel_at(adev, 1614 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1615 adev->mman.discovery_tmr_size, 1616 AMDGPU_GEM_DOMAIN_VRAM, 1617 &adev->mman.discovery_memory, 1618 NULL); 1619 if (ret) { 1620 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1621 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1622 return ret; 1623 } 1624 1625 return 0; 1626 } 1627 1628 /* 1629 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1630 * gtt/vram related fields. 1631 * 1632 * This initializes all of the memory space pools that the TTM layer 1633 * will need such as the GTT space (system memory mapped to the device), 1634 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1635 * can be mapped per VMID. 1636 */ 1637 int amdgpu_ttm_init(struct amdgpu_device *adev) 1638 { 1639 uint64_t gtt_size; 1640 int r; 1641 u64 vis_vram_limit; 1642 1643 mutex_init(&adev->mman.gtt_window_lock); 1644 1645 /* No others user of address space so set it to 0 */ 1646 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1647 adev_to_drm(adev)->anon_inode->i_mapping, 1648 adev_to_drm(adev)->vma_offset_manager, 1649 adev->need_swiotlb, 1650 dma_addressing_limited(adev->dev)); 1651 if (r) { 1652 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1653 return r; 1654 } 1655 adev->mman.initialized = true; 1656 1657 /* Initialize VRAM pool with all of VRAM divided into pages */ 1658 r = amdgpu_vram_mgr_init(adev); 1659 if (r) { 1660 DRM_ERROR("Failed initializing VRAM heap.\n"); 1661 return r; 1662 } 1663 1664 /* Reduce size of CPU-visible VRAM if requested */ 1665 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1666 if (amdgpu_vis_vram_limit > 0 && 1667 vis_vram_limit <= adev->gmc.visible_vram_size) 1668 adev->gmc.visible_vram_size = vis_vram_limit; 1669 1670 /* Change the size here instead of the init above so only lpfn is affected */ 1671 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1672 #ifdef CONFIG_64BIT 1673 #ifdef CONFIG_X86 1674 if (adev->gmc.xgmi.connected_to_cpu) 1675 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1676 adev->gmc.visible_vram_size); 1677 1678 else 1679 #endif 1680 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1681 adev->gmc.visible_vram_size); 1682 #endif 1683 1684 /* 1685 *The reserved vram for firmware must be pinned to the specified 1686 *place on the VRAM, so reserve it early. 1687 */ 1688 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1689 if (r) { 1690 return r; 1691 } 1692 1693 /* 1694 * only NAVI10 and onwards ASIC support for IP discovery. 1695 * If IP discovery enabled, a block of memory should be 1696 * reserved for IP discovey. 1697 */ 1698 if (adev->mman.discovery_bin) { 1699 r = amdgpu_ttm_reserve_tmr(adev); 1700 if (r) 1701 return r; 1702 } 1703 1704 /* allocate memory as required for VGA 1705 * This is used for VGA emulation and pre-OS scanout buffers to 1706 * avoid display artifacts while transitioning between pre-OS 1707 * and driver. */ 1708 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1709 AMDGPU_GEM_DOMAIN_VRAM, 1710 &adev->mman.stolen_vga_memory, 1711 NULL); 1712 if (r) 1713 return r; 1714 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1715 adev->mman.stolen_extended_size, 1716 AMDGPU_GEM_DOMAIN_VRAM, 1717 &adev->mman.stolen_extended_memory, 1718 NULL); 1719 if (r) 1720 return r; 1721 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1722 adev->mman.stolen_reserved_size, 1723 AMDGPU_GEM_DOMAIN_VRAM, 1724 &adev->mman.stolen_reserved_memory, 1725 NULL); 1726 if (r) 1727 return r; 1728 1729 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1730 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1731 1732 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1733 * or whatever the user passed on module init */ 1734 if (amdgpu_gtt_size == -1) { 1735 struct sysinfo si; 1736 1737 si_meminfo(&si); 1738 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1739 adev->gmc.mc_vram_size), 1740 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1741 } 1742 else 1743 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1744 1745 /* Initialize GTT memory pool */ 1746 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1747 if (r) { 1748 DRM_ERROR("Failed initializing GTT heap.\n"); 1749 return r; 1750 } 1751 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1752 (unsigned)(gtt_size / (1024 * 1024))); 1753 1754 /* Initialize preemptible memory pool */ 1755 r = amdgpu_preempt_mgr_init(adev); 1756 if (r) { 1757 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1758 return r; 1759 } 1760 1761 /* Initialize various on-chip memory pools */ 1762 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1763 if (r) { 1764 DRM_ERROR("Failed initializing GDS heap.\n"); 1765 return r; 1766 } 1767 1768 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1769 if (r) { 1770 DRM_ERROR("Failed initializing gws heap.\n"); 1771 return r; 1772 } 1773 1774 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1775 if (r) { 1776 DRM_ERROR("Failed initializing oa heap.\n"); 1777 return r; 1778 } 1779 1780 return 0; 1781 } 1782 1783 /* 1784 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1785 */ 1786 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1787 { 1788 if (!adev->mman.initialized) 1789 return; 1790 1791 amdgpu_ttm_training_reserve_vram_fini(adev); 1792 /* return the stolen vga memory back to VRAM */ 1793 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1794 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1795 /* return the IP Discovery TMR memory back to VRAM */ 1796 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1797 if (adev->mman.stolen_reserved_size) 1798 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1799 NULL, NULL); 1800 amdgpu_ttm_fw_reserve_vram_fini(adev); 1801 1802 amdgpu_vram_mgr_fini(adev); 1803 amdgpu_gtt_mgr_fini(adev); 1804 amdgpu_preempt_mgr_fini(adev); 1805 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1806 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1807 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1808 ttm_device_fini(&adev->mman.bdev); 1809 adev->mman.initialized = false; 1810 DRM_INFO("amdgpu: ttm finalized\n"); 1811 } 1812 1813 /** 1814 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1815 * 1816 * @adev: amdgpu_device pointer 1817 * @enable: true when we can use buffer functions. 1818 * 1819 * Enable/disable use of buffer functions during suspend/resume. This should 1820 * only be called at bootup or when userspace isn't running. 1821 */ 1822 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1823 { 1824 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1825 uint64_t size; 1826 int r; 1827 1828 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1829 adev->mman.buffer_funcs_enabled == enable) 1830 return; 1831 1832 if (enable) { 1833 struct amdgpu_ring *ring; 1834 struct drm_gpu_scheduler *sched; 1835 1836 ring = adev->mman.buffer_funcs_ring; 1837 sched = &ring->sched; 1838 r = drm_sched_entity_init(&adev->mman.entity, 1839 DRM_SCHED_PRIORITY_KERNEL, &sched, 1840 1, NULL); 1841 if (r) { 1842 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1843 r); 1844 return; 1845 } 1846 } else { 1847 drm_sched_entity_destroy(&adev->mman.entity); 1848 dma_fence_put(man->move); 1849 man->move = NULL; 1850 } 1851 1852 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1853 if (enable) 1854 size = adev->gmc.real_vram_size; 1855 else 1856 size = adev->gmc.visible_vram_size; 1857 man->size = size >> PAGE_SHIFT; 1858 adev->mman.buffer_funcs_enabled = enable; 1859 } 1860 1861 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1862 uint64_t dst_offset, uint32_t byte_count, 1863 struct dma_resv *resv, 1864 struct dma_fence **fence, bool direct_submit, 1865 bool vm_needs_flush, bool tmz) 1866 { 1867 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1868 AMDGPU_IB_POOL_DELAYED; 1869 struct amdgpu_device *adev = ring->adev; 1870 struct amdgpu_job *job; 1871 1872 uint32_t max_bytes; 1873 unsigned num_loops, num_dw; 1874 unsigned i; 1875 int r; 1876 1877 if (direct_submit && !ring->sched.ready) { 1878 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1879 return -EINVAL; 1880 } 1881 1882 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1883 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1884 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1885 1886 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1887 if (r) 1888 return r; 1889 1890 if (vm_needs_flush) { 1891 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1892 adev->gmc.pdb0_bo : adev->gart.bo); 1893 job->vm_needs_flush = true; 1894 } 1895 if (resv) { 1896 r = amdgpu_sync_resv(adev, &job->sync, resv, 1897 AMDGPU_SYNC_ALWAYS, 1898 AMDGPU_FENCE_OWNER_UNDEFINED); 1899 if (r) { 1900 DRM_ERROR("sync failed (%d).\n", r); 1901 goto error_free; 1902 } 1903 } 1904 1905 for (i = 0; i < num_loops; i++) { 1906 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1907 1908 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1909 dst_offset, cur_size_in_bytes, tmz); 1910 1911 src_offset += cur_size_in_bytes; 1912 dst_offset += cur_size_in_bytes; 1913 byte_count -= cur_size_in_bytes; 1914 } 1915 1916 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1917 WARN_ON(job->ibs[0].length_dw > num_dw); 1918 if (direct_submit) 1919 r = amdgpu_job_submit_direct(job, ring, fence); 1920 else 1921 r = amdgpu_job_submit(job, &adev->mman.entity, 1922 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1923 if (r) 1924 goto error_free; 1925 1926 return r; 1927 1928 error_free: 1929 amdgpu_job_free(job); 1930 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1931 return r; 1932 } 1933 1934 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1935 uint32_t src_data, 1936 struct dma_resv *resv, 1937 struct dma_fence **fence) 1938 { 1939 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1940 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1941 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1942 1943 struct amdgpu_res_cursor cursor; 1944 unsigned int num_loops, num_dw; 1945 uint64_t num_bytes; 1946 1947 struct amdgpu_job *job; 1948 int r; 1949 1950 if (!adev->mman.buffer_funcs_enabled) { 1951 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1952 return -EINVAL; 1953 } 1954 1955 if (bo->tbo.mem.mem_type == AMDGPU_PL_PREEMPT) { 1956 DRM_ERROR("Trying to clear preemptible memory.\n"); 1957 return -EINVAL; 1958 } 1959 1960 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 1961 r = amdgpu_ttm_alloc_gart(&bo->tbo); 1962 if (r) 1963 return r; 1964 } 1965 1966 num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT; 1967 num_loops = 0; 1968 1969 amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); 1970 while (cursor.remaining) { 1971 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 1972 amdgpu_res_next(&cursor, cursor.size); 1973 } 1974 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1975 1976 /* for IB padding */ 1977 num_dw += 64; 1978 1979 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1980 &job); 1981 if (r) 1982 return r; 1983 1984 if (resv) { 1985 r = amdgpu_sync_resv(adev, &job->sync, resv, 1986 AMDGPU_SYNC_ALWAYS, 1987 AMDGPU_FENCE_OWNER_UNDEFINED); 1988 if (r) { 1989 DRM_ERROR("sync failed (%d).\n", r); 1990 goto error_free; 1991 } 1992 } 1993 1994 amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); 1995 while (cursor.remaining) { 1996 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 1997 uint64_t dst_addr = cursor.start; 1998 1999 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 2000 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2001 cur_size); 2002 2003 amdgpu_res_next(&cursor, cur_size); 2004 } 2005 2006 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2007 WARN_ON(job->ibs[0].length_dw > num_dw); 2008 r = amdgpu_job_submit(job, &adev->mman.entity, 2009 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2010 if (r) 2011 goto error_free; 2012 2013 return 0; 2014 2015 error_free: 2016 amdgpu_job_free(job); 2017 return r; 2018 } 2019 2020 #if defined(CONFIG_DEBUG_FS) 2021 2022 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2023 { 2024 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2025 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2026 TTM_PL_VRAM); 2027 struct drm_printer p = drm_seq_file_printer(m); 2028 2029 man->func->debug(man, &p); 2030 return 0; 2031 } 2032 2033 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2034 { 2035 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2036 2037 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2038 } 2039 2040 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2041 { 2042 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2043 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2044 TTM_PL_TT); 2045 struct drm_printer p = drm_seq_file_printer(m); 2046 2047 man->func->debug(man, &p); 2048 return 0; 2049 } 2050 2051 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2052 { 2053 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2054 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2055 AMDGPU_PL_GDS); 2056 struct drm_printer p = drm_seq_file_printer(m); 2057 2058 man->func->debug(man, &p); 2059 return 0; 2060 } 2061 2062 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2063 { 2064 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2065 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2066 AMDGPU_PL_GWS); 2067 struct drm_printer p = drm_seq_file_printer(m); 2068 2069 man->func->debug(man, &p); 2070 return 0; 2071 } 2072 2073 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2074 { 2075 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2076 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2077 AMDGPU_PL_OA); 2078 struct drm_printer p = drm_seq_file_printer(m); 2079 2080 man->func->debug(man, &p); 2081 return 0; 2082 } 2083 2084 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2085 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2086 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2087 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2088 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2089 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2090 2091 /* 2092 * amdgpu_ttm_vram_read - Linear read access to VRAM 2093 * 2094 * Accesses VRAM via MMIO for debugging purposes. 2095 */ 2096 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2097 size_t size, loff_t *pos) 2098 { 2099 struct amdgpu_device *adev = file_inode(f)->i_private; 2100 ssize_t result = 0; 2101 2102 if (size & 0x3 || *pos & 0x3) 2103 return -EINVAL; 2104 2105 if (*pos >= adev->gmc.mc_vram_size) 2106 return -ENXIO; 2107 2108 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2109 while (size) { 2110 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2111 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2112 2113 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2114 if (copy_to_user(buf, value, bytes)) 2115 return -EFAULT; 2116 2117 result += bytes; 2118 buf += bytes; 2119 *pos += bytes; 2120 size -= bytes; 2121 } 2122 2123 return result; 2124 } 2125 2126 /* 2127 * amdgpu_ttm_vram_write - Linear write access to VRAM 2128 * 2129 * Accesses VRAM via MMIO for debugging purposes. 2130 */ 2131 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2132 size_t size, loff_t *pos) 2133 { 2134 struct amdgpu_device *adev = file_inode(f)->i_private; 2135 ssize_t result = 0; 2136 int r; 2137 2138 if (size & 0x3 || *pos & 0x3) 2139 return -EINVAL; 2140 2141 if (*pos >= adev->gmc.mc_vram_size) 2142 return -ENXIO; 2143 2144 while (size) { 2145 unsigned long flags; 2146 uint32_t value; 2147 2148 if (*pos >= adev->gmc.mc_vram_size) 2149 return result; 2150 2151 r = get_user(value, (uint32_t *)buf); 2152 if (r) 2153 return r; 2154 2155 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2156 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2157 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2158 WREG32_NO_KIQ(mmMM_DATA, value); 2159 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2160 2161 result += 4; 2162 buf += 4; 2163 *pos += 4; 2164 size -= 4; 2165 } 2166 2167 return result; 2168 } 2169 2170 static const struct file_operations amdgpu_ttm_vram_fops = { 2171 .owner = THIS_MODULE, 2172 .read = amdgpu_ttm_vram_read, 2173 .write = amdgpu_ttm_vram_write, 2174 .llseek = default_llseek, 2175 }; 2176 2177 /* 2178 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2179 * 2180 * This function is used to read memory that has been mapped to the 2181 * GPU and the known addresses are not physical addresses but instead 2182 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2183 */ 2184 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2185 size_t size, loff_t *pos) 2186 { 2187 struct amdgpu_device *adev = file_inode(f)->i_private; 2188 struct iommu_domain *dom; 2189 ssize_t result = 0; 2190 int r; 2191 2192 /* retrieve the IOMMU domain if any for this device */ 2193 dom = iommu_get_domain_for_dev(adev->dev); 2194 2195 while (size) { 2196 phys_addr_t addr = *pos & PAGE_MASK; 2197 loff_t off = *pos & ~PAGE_MASK; 2198 size_t bytes = PAGE_SIZE - off; 2199 unsigned long pfn; 2200 struct page *p; 2201 void *ptr; 2202 2203 bytes = bytes < size ? bytes : size; 2204 2205 /* Translate the bus address to a physical address. If 2206 * the domain is NULL it means there is no IOMMU active 2207 * and the address translation is the identity 2208 */ 2209 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2210 2211 pfn = addr >> PAGE_SHIFT; 2212 if (!pfn_valid(pfn)) 2213 return -EPERM; 2214 2215 p = pfn_to_page(pfn); 2216 if (p->mapping != adev->mman.bdev.dev_mapping) 2217 return -EPERM; 2218 2219 ptr = kmap(p); 2220 r = copy_to_user(buf, ptr + off, bytes); 2221 kunmap(p); 2222 if (r) 2223 return -EFAULT; 2224 2225 size -= bytes; 2226 *pos += bytes; 2227 result += bytes; 2228 } 2229 2230 return result; 2231 } 2232 2233 /* 2234 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2235 * 2236 * This function is used to write memory that has been mapped to the 2237 * GPU and the known addresses are not physical addresses but instead 2238 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2239 */ 2240 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2241 size_t size, loff_t *pos) 2242 { 2243 struct amdgpu_device *adev = file_inode(f)->i_private; 2244 struct iommu_domain *dom; 2245 ssize_t result = 0; 2246 int r; 2247 2248 dom = iommu_get_domain_for_dev(adev->dev); 2249 2250 while (size) { 2251 phys_addr_t addr = *pos & PAGE_MASK; 2252 loff_t off = *pos & ~PAGE_MASK; 2253 size_t bytes = PAGE_SIZE - off; 2254 unsigned long pfn; 2255 struct page *p; 2256 void *ptr; 2257 2258 bytes = bytes < size ? bytes : size; 2259 2260 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2261 2262 pfn = addr >> PAGE_SHIFT; 2263 if (!pfn_valid(pfn)) 2264 return -EPERM; 2265 2266 p = pfn_to_page(pfn); 2267 if (p->mapping != adev->mman.bdev.dev_mapping) 2268 return -EPERM; 2269 2270 ptr = kmap(p); 2271 r = copy_from_user(ptr + off, buf, bytes); 2272 kunmap(p); 2273 if (r) 2274 return -EFAULT; 2275 2276 size -= bytes; 2277 *pos += bytes; 2278 result += bytes; 2279 } 2280 2281 return result; 2282 } 2283 2284 static const struct file_operations amdgpu_ttm_iomem_fops = { 2285 .owner = THIS_MODULE, 2286 .read = amdgpu_iomem_read, 2287 .write = amdgpu_iomem_write, 2288 .llseek = default_llseek 2289 }; 2290 2291 #endif 2292 2293 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2294 { 2295 #if defined(CONFIG_DEBUG_FS) 2296 struct drm_minor *minor = adev_to_drm(adev)->primary; 2297 struct dentry *root = minor->debugfs_root; 2298 2299 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2300 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2301 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2302 &amdgpu_ttm_iomem_fops); 2303 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2304 &amdgpu_mm_vram_table_fops); 2305 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2306 &amdgpu_mm_tt_table_fops); 2307 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2308 &amdgpu_mm_gds_table_fops); 2309 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2310 &amdgpu_mm_gws_table_fops); 2311 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2312 &amdgpu_mm_oa_table_fops); 2313 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2314 &amdgpu_ttm_page_pool_fops); 2315 #endif 2316 } 2317