1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 #include <linux/module.h> 45 46 #include <drm/drm_drv.h> 47 #include <drm/ttm/ttm_bo.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_range_manager.h> 50 #include <drm/ttm/ttm_tt.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_drv.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "amdgpu_hmm.h" 62 #include "amdgpu_atomfirmware.h" 63 #include "amdgpu_res_cursor.h" 64 #include "bif/bif_4_1_d.h" 65 66 MODULE_IMPORT_NS(DMA_BUF); 67 68 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 69 70 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 71 struct ttm_tt *ttm, 72 struct ttm_resource *bo_mem); 73 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 74 struct ttm_tt *ttm); 75 76 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 77 unsigned int type, 78 uint64_t size_in_page) 79 { 80 return ttm_range_man_init(&adev->mman.bdev, type, 81 false, size_in_page); 82 } 83 84 /** 85 * amdgpu_evict_flags - Compute placement flags 86 * 87 * @bo: The buffer object to evict 88 * @placement: Possible destination(s) for evicted BO 89 * 90 * Fill in placement data when ttm_bo_evict() is called 91 */ 92 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 93 struct ttm_placement *placement) 94 { 95 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 96 struct amdgpu_bo *abo; 97 static const struct ttm_place placements = { 98 .fpfn = 0, 99 .lpfn = 0, 100 .mem_type = TTM_PL_SYSTEM, 101 .flags = 0 102 }; 103 104 /* Don't handle scatter gather BOs */ 105 if (bo->type == ttm_bo_type_sg) { 106 placement->num_placement = 0; 107 placement->num_busy_placement = 0; 108 return; 109 } 110 111 /* Object isn't an AMDGPU object so ignore */ 112 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 113 placement->placement = &placements; 114 placement->busy_placement = &placements; 115 placement->num_placement = 1; 116 placement->num_busy_placement = 1; 117 return; 118 } 119 120 abo = ttm_to_amdgpu_bo(bo); 121 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 122 placement->num_placement = 0; 123 placement->num_busy_placement = 0; 124 return; 125 } 126 127 switch (bo->resource->mem_type) { 128 case AMDGPU_PL_GDS: 129 case AMDGPU_PL_GWS: 130 case AMDGPU_PL_OA: 131 placement->num_placement = 0; 132 placement->num_busy_placement = 0; 133 return; 134 135 case TTM_PL_VRAM: 136 if (!adev->mman.buffer_funcs_enabled) { 137 /* Move to system memory */ 138 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 139 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 140 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 141 amdgpu_bo_in_cpu_visible_vram(abo)) { 142 143 /* Try evicting to the CPU inaccessible part of VRAM 144 * first, but only set GTT as busy placement, so this 145 * BO will be evicted to GTT rather than causing other 146 * BOs to be evicted from VRAM 147 */ 148 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 149 AMDGPU_GEM_DOMAIN_GTT | 150 AMDGPU_GEM_DOMAIN_CPU); 151 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 152 abo->placements[0].lpfn = 0; 153 abo->placement.busy_placement = &abo->placements[1]; 154 abo->placement.num_busy_placement = 1; 155 } else { 156 /* Move to GTT memory */ 157 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 158 AMDGPU_GEM_DOMAIN_CPU); 159 } 160 break; 161 case TTM_PL_TT: 162 case AMDGPU_PL_PREEMPT: 163 default: 164 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 165 break; 166 } 167 *placement = abo->placement; 168 } 169 170 /** 171 * amdgpu_ttm_map_buffer - Map memory into the GART windows 172 * @bo: buffer object to map 173 * @mem: memory object to map 174 * @mm_cur: range to map 175 * @window: which GART window to use 176 * @ring: DMA ring to use for the copy 177 * @tmz: if we should setup a TMZ enabled mapping 178 * @size: in number of bytes to map, out number of bytes mapped 179 * @addr: resulting address inside the MC address space 180 * 181 * Setup one of the GART windows to access a specific piece of memory or return 182 * the physical address for local memory. 183 */ 184 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 185 struct ttm_resource *mem, 186 struct amdgpu_res_cursor *mm_cur, 187 unsigned window, struct amdgpu_ring *ring, 188 bool tmz, uint64_t *size, uint64_t *addr) 189 { 190 struct amdgpu_device *adev = ring->adev; 191 unsigned offset, num_pages, num_dw, num_bytes; 192 uint64_t src_addr, dst_addr; 193 struct amdgpu_job *job; 194 void *cpu_addr; 195 uint64_t flags; 196 unsigned int i; 197 int r; 198 199 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 200 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 201 202 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT)) 203 return -EINVAL; 204 205 /* Map only what can't be accessed directly */ 206 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 207 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 208 mm_cur->start; 209 return 0; 210 } 211 212 213 /* 214 * If start begins at an offset inside the page, then adjust the size 215 * and addr accordingly 216 */ 217 offset = mm_cur->start & ~PAGE_MASK; 218 219 num_pages = PFN_UP(*size + offset); 220 num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE); 221 222 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 223 224 *addr = adev->gmc.gart_start; 225 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 226 AMDGPU_GPU_PAGE_SIZE; 227 *addr += offset; 228 229 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 230 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 231 232 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity, 233 AMDGPU_FENCE_OWNER_UNDEFINED, 234 num_dw * 4 + num_bytes, 235 AMDGPU_IB_POOL_DELAYED, &job); 236 if (r) 237 return r; 238 239 src_addr = num_dw * 4; 240 src_addr += job->ibs[0].gpu_addr; 241 242 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 243 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 244 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 245 dst_addr, num_bytes, false); 246 247 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 248 WARN_ON(job->ibs[0].length_dw > num_dw); 249 250 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 251 if (tmz) 252 flags |= AMDGPU_PTE_TMZ; 253 254 cpu_addr = &job->ibs[0].ptr[num_dw]; 255 256 if (mem->mem_type == TTM_PL_TT) { 257 dma_addr_t *dma_addr; 258 259 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 260 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 261 } else { 262 dma_addr_t dma_address; 263 264 dma_address = mm_cur->start; 265 dma_address += adev->vm_manager.vram_base_offset; 266 267 for (i = 0; i < num_pages; ++i) { 268 amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address, 269 flags, cpu_addr); 270 dma_address += PAGE_SIZE; 271 } 272 } 273 274 dma_fence_put(amdgpu_job_submit(job)); 275 return 0; 276 } 277 278 /** 279 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 280 * @adev: amdgpu device 281 * @src: buffer/address where to read from 282 * @dst: buffer/address where to write to 283 * @size: number of bytes to copy 284 * @tmz: if a secure copy should be used 285 * @resv: resv object to sync to 286 * @f: Returns the last fence if multiple jobs are submitted. 287 * 288 * The function copies @size bytes from {src->mem + src->offset} to 289 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 290 * move and different for a BO to BO copy. 291 * 292 */ 293 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 294 const struct amdgpu_copy_mem *src, 295 const struct amdgpu_copy_mem *dst, 296 uint64_t size, bool tmz, 297 struct dma_resv *resv, 298 struct dma_fence **f) 299 { 300 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 301 struct amdgpu_res_cursor src_mm, dst_mm; 302 struct dma_fence *fence = NULL; 303 int r = 0; 304 305 if (!adev->mman.buffer_funcs_enabled) { 306 DRM_ERROR("Trying to move memory with ring turned off.\n"); 307 return -EINVAL; 308 } 309 310 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 311 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 312 313 mutex_lock(&adev->mman.gtt_window_lock); 314 while (src_mm.remaining) { 315 uint64_t from, to, cur_size; 316 struct dma_fence *next; 317 318 /* Never copy more than 256MiB at once to avoid a timeout */ 319 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 320 321 /* Map src to window 0 and dst to window 1. */ 322 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 323 0, ring, tmz, &cur_size, &from); 324 if (r) 325 goto error; 326 327 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 328 1, ring, tmz, &cur_size, &to); 329 if (r) 330 goto error; 331 332 r = amdgpu_copy_buffer(ring, from, to, cur_size, 333 resv, &next, false, true, tmz); 334 if (r) 335 goto error; 336 337 dma_fence_put(fence); 338 fence = next; 339 340 amdgpu_res_next(&src_mm, cur_size); 341 amdgpu_res_next(&dst_mm, cur_size); 342 } 343 error: 344 mutex_unlock(&adev->mman.gtt_window_lock); 345 if (f) 346 *f = dma_fence_get(fence); 347 dma_fence_put(fence); 348 return r; 349 } 350 351 /* 352 * amdgpu_move_blit - Copy an entire buffer to another buffer 353 * 354 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 355 * help move buffers to and from VRAM. 356 */ 357 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 358 bool evict, 359 struct ttm_resource *new_mem, 360 struct ttm_resource *old_mem) 361 { 362 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 363 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 364 struct amdgpu_copy_mem src, dst; 365 struct dma_fence *fence = NULL; 366 int r; 367 368 src.bo = bo; 369 dst.bo = bo; 370 src.mem = old_mem; 371 dst.mem = new_mem; 372 src.offset = 0; 373 dst.offset = 0; 374 375 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 376 new_mem->size, 377 amdgpu_bo_encrypted(abo), 378 bo->base.resv, &fence); 379 if (r) 380 goto error; 381 382 /* clear the space being freed */ 383 if (old_mem->mem_type == TTM_PL_VRAM && 384 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 385 struct dma_fence *wipe_fence = NULL; 386 387 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence); 388 if (r) { 389 goto error; 390 } else if (wipe_fence) { 391 dma_fence_put(fence); 392 fence = wipe_fence; 393 } 394 } 395 396 /* Always block for VM page tables before committing the new location */ 397 if (bo->type == ttm_bo_type_kernel) 398 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 399 else 400 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 401 dma_fence_put(fence); 402 return r; 403 404 error: 405 if (fence) 406 dma_fence_wait(fence, false); 407 dma_fence_put(fence); 408 return r; 409 } 410 411 /* 412 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 413 * 414 * Called by amdgpu_bo_move() 415 */ 416 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 417 struct ttm_resource *mem) 418 { 419 u64 mem_size = (u64)mem->size; 420 struct amdgpu_res_cursor cursor; 421 u64 end; 422 423 if (mem->mem_type == TTM_PL_SYSTEM || 424 mem->mem_type == TTM_PL_TT) 425 return true; 426 if (mem->mem_type != TTM_PL_VRAM) 427 return false; 428 429 amdgpu_res_first(mem, 0, mem_size, &cursor); 430 end = cursor.start + cursor.size; 431 while (cursor.remaining) { 432 amdgpu_res_next(&cursor, cursor.size); 433 434 if (!cursor.remaining) 435 break; 436 437 /* ttm_resource_ioremap only supports contiguous memory */ 438 if (end != cursor.start) 439 return false; 440 441 end = cursor.start + cursor.size; 442 } 443 444 return end <= adev->gmc.visible_vram_size; 445 } 446 447 /* 448 * amdgpu_bo_move - Move a buffer object to a new memory location 449 * 450 * Called by ttm_bo_handle_move_mem() 451 */ 452 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 453 struct ttm_operation_ctx *ctx, 454 struct ttm_resource *new_mem, 455 struct ttm_place *hop) 456 { 457 struct amdgpu_device *adev; 458 struct amdgpu_bo *abo; 459 struct ttm_resource *old_mem = bo->resource; 460 int r; 461 462 if (new_mem->mem_type == TTM_PL_TT || 463 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 464 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 465 if (r) 466 return r; 467 } 468 469 abo = ttm_to_amdgpu_bo(bo); 470 adev = amdgpu_ttm_adev(bo->bdev); 471 472 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 473 bo->ttm == NULL)) { 474 ttm_bo_move_null(bo, new_mem); 475 goto out; 476 } 477 if (old_mem->mem_type == TTM_PL_SYSTEM && 478 (new_mem->mem_type == TTM_PL_TT || 479 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 480 ttm_bo_move_null(bo, new_mem); 481 goto out; 482 } 483 if ((old_mem->mem_type == TTM_PL_TT || 484 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 485 new_mem->mem_type == TTM_PL_SYSTEM) { 486 r = ttm_bo_wait_ctx(bo, ctx); 487 if (r) 488 return r; 489 490 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 491 ttm_resource_free(bo, &bo->resource); 492 ttm_bo_assign_mem(bo, new_mem); 493 goto out; 494 } 495 496 if (old_mem->mem_type == AMDGPU_PL_GDS || 497 old_mem->mem_type == AMDGPU_PL_GWS || 498 old_mem->mem_type == AMDGPU_PL_OA || 499 new_mem->mem_type == AMDGPU_PL_GDS || 500 new_mem->mem_type == AMDGPU_PL_GWS || 501 new_mem->mem_type == AMDGPU_PL_OA) { 502 /* Nothing to save here */ 503 ttm_bo_move_null(bo, new_mem); 504 goto out; 505 } 506 507 if (bo->type == ttm_bo_type_device && 508 new_mem->mem_type == TTM_PL_VRAM && 509 old_mem->mem_type != TTM_PL_VRAM) { 510 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 511 * accesses the BO after it's moved. 512 */ 513 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 514 } 515 516 if (adev->mman.buffer_funcs_enabled) { 517 if (((old_mem->mem_type == TTM_PL_SYSTEM && 518 new_mem->mem_type == TTM_PL_VRAM) || 519 (old_mem->mem_type == TTM_PL_VRAM && 520 new_mem->mem_type == TTM_PL_SYSTEM))) { 521 hop->fpfn = 0; 522 hop->lpfn = 0; 523 hop->mem_type = TTM_PL_TT; 524 hop->flags = TTM_PL_FLAG_TEMPORARY; 525 return -EMULTIHOP; 526 } 527 528 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 529 } else { 530 r = -ENODEV; 531 } 532 533 if (r) { 534 /* Check that all memory is CPU accessible */ 535 if (!amdgpu_mem_visible(adev, old_mem) || 536 !amdgpu_mem_visible(adev, new_mem)) { 537 pr_err("Move buffer fallback to memcpy unavailable\n"); 538 return r; 539 } 540 541 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 542 if (r) 543 return r; 544 } 545 546 out: 547 /* update statistics */ 548 atomic64_add(bo->base.size, &adev->num_bytes_moved); 549 amdgpu_bo_move_notify(bo, evict, new_mem); 550 return 0; 551 } 552 553 /* 554 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 555 * 556 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 557 */ 558 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 559 struct ttm_resource *mem) 560 { 561 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 562 size_t bus_size = (size_t)mem->size; 563 564 switch (mem->mem_type) { 565 case TTM_PL_SYSTEM: 566 /* system memory */ 567 return 0; 568 case TTM_PL_TT: 569 case AMDGPU_PL_PREEMPT: 570 break; 571 case TTM_PL_VRAM: 572 mem->bus.offset = mem->start << PAGE_SHIFT; 573 /* check if it's visible */ 574 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 575 return -EINVAL; 576 577 if (adev->mman.aper_base_kaddr && 578 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 579 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 580 mem->bus.offset; 581 582 mem->bus.offset += adev->gmc.aper_base; 583 mem->bus.is_iomem = true; 584 break; 585 default: 586 return -EINVAL; 587 } 588 return 0; 589 } 590 591 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 592 unsigned long page_offset) 593 { 594 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 595 struct amdgpu_res_cursor cursor; 596 597 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 598 &cursor); 599 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 600 } 601 602 /** 603 * amdgpu_ttm_domain_start - Returns GPU start address 604 * @adev: amdgpu device object 605 * @type: type of the memory 606 * 607 * Returns: 608 * GPU start address of a memory domain 609 */ 610 611 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 612 { 613 switch (type) { 614 case TTM_PL_TT: 615 return adev->gmc.gart_start; 616 case TTM_PL_VRAM: 617 return adev->gmc.vram_start; 618 } 619 620 return 0; 621 } 622 623 /* 624 * TTM backend functions. 625 */ 626 struct amdgpu_ttm_tt { 627 struct ttm_tt ttm; 628 struct drm_gem_object *gobj; 629 u64 offset; 630 uint64_t userptr; 631 struct task_struct *usertask; 632 uint32_t userflags; 633 bool bound; 634 }; 635 636 #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) 637 638 #ifdef CONFIG_DRM_AMDGPU_USERPTR 639 /* 640 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 641 * memory and start HMM tracking CPU page table update 642 * 643 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 644 * once afterwards to stop HMM tracking 645 */ 646 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, 647 struct hmm_range **range) 648 { 649 struct ttm_tt *ttm = bo->tbo.ttm; 650 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 651 unsigned long start = gtt->userptr; 652 struct vm_area_struct *vma; 653 struct mm_struct *mm; 654 bool readonly; 655 int r = 0; 656 657 /* Make sure get_user_pages_done() can cleanup gracefully */ 658 *range = NULL; 659 660 mm = bo->notifier.mm; 661 if (unlikely(!mm)) { 662 DRM_DEBUG_DRIVER("BO is not registered?\n"); 663 return -EFAULT; 664 } 665 666 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 667 return -ESRCH; 668 669 mmap_read_lock(mm); 670 vma = vma_lookup(mm, start); 671 if (unlikely(!vma)) { 672 r = -EFAULT; 673 goto out_unlock; 674 } 675 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 676 vma->vm_file)) { 677 r = -EPERM; 678 goto out_unlock; 679 } 680 681 readonly = amdgpu_ttm_tt_is_readonly(ttm); 682 r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages, 683 readonly, NULL, pages, range); 684 out_unlock: 685 mmap_read_unlock(mm); 686 if (r) 687 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 688 689 mmput(mm); 690 691 return r; 692 } 693 694 /* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations 695 */ 696 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 697 struct hmm_range *range) 698 { 699 struct amdgpu_ttm_tt *gtt = (void *)ttm; 700 701 if (gtt && gtt->userptr && range) 702 amdgpu_hmm_range_get_pages_done(range); 703 } 704 705 /* 706 * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change 707 * Check if the pages backing this ttm range have been invalidated 708 * 709 * Returns: true if pages are still valid 710 */ 711 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 712 struct hmm_range *range) 713 { 714 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 715 716 if (!gtt || !gtt->userptr || !range) 717 return false; 718 719 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 720 gtt->userptr, ttm->num_pages); 721 722 WARN_ONCE(!range->hmm_pfns, "No user pages to check\n"); 723 724 return !amdgpu_hmm_range_get_pages_done(range); 725 } 726 #endif 727 728 /* 729 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 730 * 731 * Called by amdgpu_cs_list_validate(). This creates the page list 732 * that backs user memory and will ultimately be mapped into the device 733 * address space. 734 */ 735 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 736 { 737 unsigned long i; 738 739 for (i = 0; i < ttm->num_pages; ++i) 740 ttm->pages[i] = pages ? pages[i] : NULL; 741 } 742 743 /* 744 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 745 * 746 * Called by amdgpu_ttm_backend_bind() 747 **/ 748 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 749 struct ttm_tt *ttm) 750 { 751 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 752 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 753 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 754 enum dma_data_direction direction = write ? 755 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 756 int r; 757 758 /* Allocate an SG array and squash pages into it */ 759 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 760 (u64)ttm->num_pages << PAGE_SHIFT, 761 GFP_KERNEL); 762 if (r) 763 goto release_sg; 764 765 /* Map SG to device */ 766 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 767 if (r) 768 goto release_sg; 769 770 /* convert SG to linear array of pages and dma addresses */ 771 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 772 ttm->num_pages); 773 774 return 0; 775 776 release_sg: 777 kfree(ttm->sg); 778 ttm->sg = NULL; 779 return r; 780 } 781 782 /* 783 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 784 */ 785 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 786 struct ttm_tt *ttm) 787 { 788 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 789 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 790 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 791 enum dma_data_direction direction = write ? 792 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 793 794 /* double check that we don't free the table twice */ 795 if (!ttm->sg || !ttm->sg->sgl) 796 return; 797 798 /* unmap the pages mapped to the device */ 799 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 800 sg_free_table(ttm->sg); 801 } 802 803 /* 804 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ... 805 * MQDn+CtrlStackn where n is the number of XCCs per partition. 806 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD 807 * and uses memory type default, UC. The rest of pages_per_xcc are 808 * Ctrl stack and modify their memory type to NC. 809 */ 810 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, 811 struct ttm_tt *ttm, uint64_t flags) 812 { 813 struct amdgpu_ttm_tt *gtt = (void *)ttm; 814 uint64_t total_pages = ttm->num_pages; 815 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); 816 uint64_t page_idx, pages_per_xcc = total_pages / num_xcc; 817 int i; 818 uint64_t ctrl_flags = (flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 819 AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 820 821 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { 822 /* MQD page: use default flags */ 823 amdgpu_gart_bind(adev, 824 gtt->offset + (page_idx << PAGE_SHIFT), 825 1, >t->ttm.dma_address[page_idx], flags); 826 /* 827 * Ctrl pages - modify the memory type to NC (ctrl_flags) from 828 * the second page of the BO onward. 829 */ 830 amdgpu_gart_bind(adev, 831 gtt->offset + ((page_idx + 1) << PAGE_SHIFT), 832 pages_per_xcc - 1, 833 >t->ttm.dma_address[page_idx + 1], 834 ctrl_flags); 835 } 836 } 837 838 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 839 struct ttm_buffer_object *tbo, 840 uint64_t flags) 841 { 842 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 843 struct ttm_tt *ttm = tbo->ttm; 844 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 845 846 if (amdgpu_bo_encrypted(abo)) 847 flags |= AMDGPU_PTE_TMZ; 848 849 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 850 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags); 851 } else { 852 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 853 gtt->ttm.dma_address, flags); 854 } 855 } 856 857 /* 858 * amdgpu_ttm_backend_bind - Bind GTT memory 859 * 860 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 861 * This handles binding GTT memory to the device address space. 862 */ 863 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 864 struct ttm_tt *ttm, 865 struct ttm_resource *bo_mem) 866 { 867 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 868 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 869 uint64_t flags; 870 int r; 871 872 if (!bo_mem) 873 return -EINVAL; 874 875 if (gtt->bound) 876 return 0; 877 878 if (gtt->userptr) { 879 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 880 if (r) { 881 DRM_ERROR("failed to pin userptr\n"); 882 return r; 883 } 884 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 885 if (!ttm->sg) { 886 struct dma_buf_attachment *attach; 887 struct sg_table *sgt; 888 889 attach = gtt->gobj->import_attach; 890 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 891 if (IS_ERR(sgt)) 892 return PTR_ERR(sgt); 893 894 ttm->sg = sgt; 895 } 896 897 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 898 ttm->num_pages); 899 } 900 901 if (!ttm->num_pages) { 902 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 903 ttm->num_pages, bo_mem, ttm); 904 } 905 906 if (bo_mem->mem_type != TTM_PL_TT || 907 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 908 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 909 return 0; 910 } 911 912 /* compute PTE flags relevant to this BO memory */ 913 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 914 915 /* bind pages into GART page tables */ 916 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 917 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 918 gtt->ttm.dma_address, flags); 919 gtt->bound = true; 920 return 0; 921 } 922 923 /* 924 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 925 * through AGP or GART aperture. 926 * 927 * If bo is accessible through AGP aperture, then use AGP aperture 928 * to access bo; otherwise allocate logical space in GART aperture 929 * and map bo to GART aperture. 930 */ 931 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 932 { 933 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 934 struct ttm_operation_ctx ctx = { false, false }; 935 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 936 struct ttm_placement placement; 937 struct ttm_place placements; 938 struct ttm_resource *tmp; 939 uint64_t addr, flags; 940 int r; 941 942 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 943 return 0; 944 945 addr = amdgpu_gmc_agp_addr(bo); 946 if (addr != AMDGPU_BO_INVALID_OFFSET) { 947 bo->resource->start = addr >> PAGE_SHIFT; 948 return 0; 949 } 950 951 /* allocate GART space */ 952 placement.num_placement = 1; 953 placement.placement = &placements; 954 placement.num_busy_placement = 1; 955 placement.busy_placement = &placements; 956 placements.fpfn = 0; 957 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 958 placements.mem_type = TTM_PL_TT; 959 placements.flags = bo->resource->placement; 960 961 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 962 if (unlikely(r)) 963 return r; 964 965 /* compute PTE flags for this buffer object */ 966 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 967 968 /* Bind pages */ 969 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 970 amdgpu_ttm_gart_bind(adev, bo, flags); 971 amdgpu_gart_invalidate_tlb(adev); 972 ttm_resource_free(bo, &bo->resource); 973 ttm_bo_assign_mem(bo, tmp); 974 975 return 0; 976 } 977 978 /* 979 * amdgpu_ttm_recover_gart - Rebind GTT pages 980 * 981 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 982 * rebind GTT pages during a GPU reset. 983 */ 984 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 985 { 986 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 987 uint64_t flags; 988 989 if (!tbo->ttm) 990 return; 991 992 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 993 amdgpu_ttm_gart_bind(adev, tbo, flags); 994 } 995 996 /* 997 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 998 * 999 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1000 * ttm_tt_destroy(). 1001 */ 1002 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1003 struct ttm_tt *ttm) 1004 { 1005 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1006 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1007 1008 /* if the pages have userptr pinning then clear that first */ 1009 if (gtt->userptr) { 1010 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1011 } else if (ttm->sg && gtt->gobj->import_attach) { 1012 struct dma_buf_attachment *attach; 1013 1014 attach = gtt->gobj->import_attach; 1015 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1016 ttm->sg = NULL; 1017 } 1018 1019 if (!gtt->bound) 1020 return; 1021 1022 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1023 return; 1024 1025 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1026 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1027 gtt->bound = false; 1028 } 1029 1030 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1031 struct ttm_tt *ttm) 1032 { 1033 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1034 1035 if (gtt->usertask) 1036 put_task_struct(gtt->usertask); 1037 1038 ttm_tt_fini(>t->ttm); 1039 kfree(gtt); 1040 } 1041 1042 /** 1043 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1044 * 1045 * @bo: The buffer object to create a GTT ttm_tt object around 1046 * @page_flags: Page flags to be added to the ttm_tt object 1047 * 1048 * Called by ttm_tt_create(). 1049 */ 1050 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1051 uint32_t page_flags) 1052 { 1053 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1054 struct amdgpu_ttm_tt *gtt; 1055 enum ttm_caching caching; 1056 1057 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1058 if (gtt == NULL) { 1059 return NULL; 1060 } 1061 gtt->gobj = &bo->base; 1062 1063 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1064 caching = ttm_write_combined; 1065 else 1066 caching = ttm_cached; 1067 1068 /* allocate space for the uninitialized page entries */ 1069 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1070 kfree(gtt); 1071 return NULL; 1072 } 1073 return >t->ttm; 1074 } 1075 1076 /* 1077 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1078 * 1079 * Map the pages of a ttm_tt object to an address space visible 1080 * to the underlying device. 1081 */ 1082 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1083 struct ttm_tt *ttm, 1084 struct ttm_operation_ctx *ctx) 1085 { 1086 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1087 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1088 pgoff_t i; 1089 int ret; 1090 1091 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1092 if (gtt->userptr) { 1093 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1094 if (!ttm->sg) 1095 return -ENOMEM; 1096 return 0; 1097 } 1098 1099 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1100 return 0; 1101 1102 ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1103 if (ret) 1104 return ret; 1105 1106 for (i = 0; i < ttm->num_pages; ++i) 1107 ttm->pages[i]->mapping = bdev->dev_mapping; 1108 1109 return 0; 1110 } 1111 1112 /* 1113 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1114 * 1115 * Unmaps pages of a ttm_tt object from the device address space and 1116 * unpopulates the page array backing it. 1117 */ 1118 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1119 struct ttm_tt *ttm) 1120 { 1121 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1122 struct amdgpu_device *adev; 1123 pgoff_t i; 1124 1125 amdgpu_ttm_backend_unbind(bdev, ttm); 1126 1127 if (gtt->userptr) { 1128 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1129 kfree(ttm->sg); 1130 ttm->sg = NULL; 1131 return; 1132 } 1133 1134 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1135 return; 1136 1137 for (i = 0; i < ttm->num_pages; ++i) 1138 ttm->pages[i]->mapping = NULL; 1139 1140 adev = amdgpu_ttm_adev(bdev); 1141 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1142 } 1143 1144 /** 1145 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current 1146 * task 1147 * 1148 * @tbo: The ttm_buffer_object that contains the userptr 1149 * @user_addr: The returned value 1150 */ 1151 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 1152 uint64_t *user_addr) 1153 { 1154 struct amdgpu_ttm_tt *gtt; 1155 1156 if (!tbo->ttm) 1157 return -EINVAL; 1158 1159 gtt = (void *)tbo->ttm; 1160 *user_addr = gtt->userptr; 1161 return 0; 1162 } 1163 1164 /** 1165 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1166 * task 1167 * 1168 * @bo: The ttm_buffer_object to bind this userptr to 1169 * @addr: The address in the current tasks VM space to use 1170 * @flags: Requirements of userptr object. 1171 * 1172 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to 1173 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to 1174 * initialize GPU VM for a KFD process. 1175 */ 1176 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1177 uint64_t addr, uint32_t flags) 1178 { 1179 struct amdgpu_ttm_tt *gtt; 1180 1181 if (!bo->ttm) { 1182 /* TODO: We want a separate TTM object type for userptrs */ 1183 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1184 if (bo->ttm == NULL) 1185 return -ENOMEM; 1186 } 1187 1188 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1189 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1190 1191 gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 1192 gtt->userptr = addr; 1193 gtt->userflags = flags; 1194 1195 if (gtt->usertask) 1196 put_task_struct(gtt->usertask); 1197 gtt->usertask = current->group_leader; 1198 get_task_struct(gtt->usertask); 1199 1200 return 0; 1201 } 1202 1203 /* 1204 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1205 */ 1206 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1207 { 1208 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1209 1210 if (gtt == NULL) 1211 return NULL; 1212 1213 if (gtt->usertask == NULL) 1214 return NULL; 1215 1216 return gtt->usertask->mm; 1217 } 1218 1219 /* 1220 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1221 * address range for the current task. 1222 * 1223 */ 1224 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1225 unsigned long end, unsigned long *userptr) 1226 { 1227 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1228 unsigned long size; 1229 1230 if (gtt == NULL || !gtt->userptr) 1231 return false; 1232 1233 /* Return false if no part of the ttm_tt object lies within 1234 * the range 1235 */ 1236 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1237 if (gtt->userptr > end || gtt->userptr + size <= start) 1238 return false; 1239 1240 if (userptr) 1241 *userptr = gtt->userptr; 1242 return true; 1243 } 1244 1245 /* 1246 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1247 */ 1248 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1249 { 1250 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1251 1252 if (gtt == NULL || !gtt->userptr) 1253 return false; 1254 1255 return true; 1256 } 1257 1258 /* 1259 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1260 */ 1261 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1262 { 1263 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1264 1265 if (gtt == NULL) 1266 return false; 1267 1268 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1269 } 1270 1271 /** 1272 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1273 * 1274 * @ttm: The ttm_tt object to compute the flags for 1275 * @mem: The memory registry backing this ttm_tt object 1276 * 1277 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1278 */ 1279 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1280 { 1281 uint64_t flags = 0; 1282 1283 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1284 flags |= AMDGPU_PTE_VALID; 1285 1286 if (mem && (mem->mem_type == TTM_PL_TT || 1287 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1288 flags |= AMDGPU_PTE_SYSTEM; 1289 1290 if (ttm->caching == ttm_cached) 1291 flags |= AMDGPU_PTE_SNOOPED; 1292 } 1293 1294 if (mem && mem->mem_type == TTM_PL_VRAM && 1295 mem->bus.caching == ttm_cached) 1296 flags |= AMDGPU_PTE_SNOOPED; 1297 1298 return flags; 1299 } 1300 1301 /** 1302 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1303 * 1304 * @adev: amdgpu_device pointer 1305 * @ttm: The ttm_tt object to compute the flags for 1306 * @mem: The memory registry backing this ttm_tt object 1307 * 1308 * Figure out the flags to use for a VM PTE (Page Table Entry). 1309 */ 1310 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1311 struct ttm_resource *mem) 1312 { 1313 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1314 1315 flags |= adev->gart.gart_pte_flags; 1316 flags |= AMDGPU_PTE_READABLE; 1317 1318 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1319 flags |= AMDGPU_PTE_WRITEABLE; 1320 1321 return flags; 1322 } 1323 1324 /* 1325 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1326 * object. 1327 * 1328 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1329 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1330 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1331 * used to clean out a memory space. 1332 */ 1333 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1334 const struct ttm_place *place) 1335 { 1336 struct dma_resv_iter resv_cursor; 1337 struct dma_fence *f; 1338 1339 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1340 return ttm_bo_eviction_valuable(bo, place); 1341 1342 /* Swapout? */ 1343 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1344 return true; 1345 1346 if (bo->type == ttm_bo_type_kernel && 1347 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1348 return false; 1349 1350 /* If bo is a KFD BO, check if the bo belongs to the current process. 1351 * If true, then return false as any KFD process needs all its BOs to 1352 * be resident to run successfully 1353 */ 1354 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, 1355 DMA_RESV_USAGE_BOOKKEEP, f) { 1356 if (amdkfd_fence_check_mm(f, current->mm)) 1357 return false; 1358 } 1359 1360 /* Preemptible BOs don't own system resources managed by the 1361 * driver (pages, VRAM, GART space). They point to resources 1362 * owned by someone else (e.g. pageable memory in user mode 1363 * or a DMABuf). They are used in a preemptible context so we 1364 * can guarantee no deadlocks and good QoS in case of MMU 1365 * notifiers or DMABuf move notifiers from the resource owner. 1366 */ 1367 if (bo->resource->mem_type == AMDGPU_PL_PREEMPT) 1368 return false; 1369 1370 if (bo->resource->mem_type == TTM_PL_TT && 1371 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1372 return false; 1373 1374 return ttm_bo_eviction_valuable(bo, place); 1375 } 1376 1377 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1378 void *buf, size_t size, bool write) 1379 { 1380 while (size) { 1381 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1382 uint64_t bytes = 4 - (pos & 0x3); 1383 uint32_t shift = (pos & 0x3) * 8; 1384 uint32_t mask = 0xffffffff << shift; 1385 uint32_t value = 0; 1386 1387 if (size < bytes) { 1388 mask &= 0xffffffff >> (bytes - size) * 8; 1389 bytes = size; 1390 } 1391 1392 if (mask != 0xffffffff) { 1393 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1394 if (write) { 1395 value &= ~mask; 1396 value |= (*(uint32_t *)buf << shift) & mask; 1397 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1398 } else { 1399 value = (value & mask) >> shift; 1400 memcpy(buf, &value, bytes); 1401 } 1402 } else { 1403 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1404 } 1405 1406 pos += bytes; 1407 buf += bytes; 1408 size -= bytes; 1409 } 1410 } 1411 1412 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1413 unsigned long offset, void *buf, 1414 int len, int write) 1415 { 1416 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1417 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1418 struct amdgpu_res_cursor src_mm; 1419 struct amdgpu_job *job; 1420 struct dma_fence *fence; 1421 uint64_t src_addr, dst_addr; 1422 unsigned int num_dw; 1423 int r, idx; 1424 1425 if (len != PAGE_SIZE) 1426 return -EINVAL; 1427 1428 if (!adev->mman.sdma_access_ptr) 1429 return -EACCES; 1430 1431 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1432 return -ENODEV; 1433 1434 if (write) 1435 memcpy(adev->mman.sdma_access_ptr, buf, len); 1436 1437 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1438 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity, 1439 AMDGPU_FENCE_OWNER_UNDEFINED, 1440 num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1441 &job); 1442 if (r) 1443 goto out; 1444 1445 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1446 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + 1447 src_mm.start; 1448 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1449 if (write) 1450 swap(src_addr, dst_addr); 1451 1452 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, 1453 PAGE_SIZE, false); 1454 1455 amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); 1456 WARN_ON(job->ibs[0].length_dw > num_dw); 1457 1458 fence = amdgpu_job_submit(job); 1459 1460 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1461 r = -ETIMEDOUT; 1462 dma_fence_put(fence); 1463 1464 if (!(r || write)) 1465 memcpy(buf, adev->mman.sdma_access_ptr, len); 1466 out: 1467 drm_dev_exit(idx); 1468 return r; 1469 } 1470 1471 /** 1472 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1473 * 1474 * @bo: The buffer object to read/write 1475 * @offset: Offset into buffer object 1476 * @buf: Secondary buffer to write/read from 1477 * @len: Length in bytes of access 1478 * @write: true if writing 1479 * 1480 * This is used to access VRAM that backs a buffer object via MMIO 1481 * access for debugging purposes. 1482 */ 1483 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1484 unsigned long offset, void *buf, int len, 1485 int write) 1486 { 1487 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1488 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1489 struct amdgpu_res_cursor cursor; 1490 int ret = 0; 1491 1492 if (bo->resource->mem_type != TTM_PL_VRAM) 1493 return -EIO; 1494 1495 if (amdgpu_device_has_timeouts_enabled(adev) && 1496 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1497 return len; 1498 1499 amdgpu_res_first(bo->resource, offset, len, &cursor); 1500 while (cursor.remaining) { 1501 size_t count, size = cursor.size; 1502 loff_t pos = cursor.start; 1503 1504 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1505 size -= count; 1506 if (size) { 1507 /* using MM to access rest vram and handle un-aligned address */ 1508 pos += count; 1509 buf += count; 1510 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1511 } 1512 1513 ret += cursor.size; 1514 buf += cursor.size; 1515 amdgpu_res_next(&cursor, cursor.size); 1516 } 1517 1518 return ret; 1519 } 1520 1521 static void 1522 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1523 { 1524 amdgpu_bo_move_notify(bo, false, NULL); 1525 } 1526 1527 static struct ttm_device_funcs amdgpu_bo_driver = { 1528 .ttm_tt_create = &amdgpu_ttm_tt_create, 1529 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1530 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1531 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1532 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1533 .evict_flags = &amdgpu_evict_flags, 1534 .move = &amdgpu_bo_move, 1535 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1536 .release_notify = &amdgpu_bo_release_notify, 1537 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1538 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1539 .access_memory = &amdgpu_ttm_access_memory, 1540 }; 1541 1542 /* 1543 * Firmware Reservation functions 1544 */ 1545 /** 1546 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1547 * 1548 * @adev: amdgpu_device pointer 1549 * 1550 * free fw reserved vram if it has been reserved. 1551 */ 1552 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1553 { 1554 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1555 NULL, &adev->mman.fw_vram_usage_va); 1556 } 1557 1558 /* 1559 * Driver Reservation functions 1560 */ 1561 /** 1562 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram 1563 * 1564 * @adev: amdgpu_device pointer 1565 * 1566 * free drv reserved vram if it has been reserved. 1567 */ 1568 static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev) 1569 { 1570 amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo, 1571 NULL, 1572 &adev->mman.drv_vram_usage_va); 1573 } 1574 1575 /** 1576 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1577 * 1578 * @adev: amdgpu_device pointer 1579 * 1580 * create bo vram reservation from fw. 1581 */ 1582 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1583 { 1584 uint64_t vram_size = adev->gmc.visible_vram_size; 1585 1586 adev->mman.fw_vram_usage_va = NULL; 1587 adev->mman.fw_vram_usage_reserved_bo = NULL; 1588 1589 if (adev->mman.fw_vram_usage_size == 0 || 1590 adev->mman.fw_vram_usage_size > vram_size) 1591 return 0; 1592 1593 return amdgpu_bo_create_kernel_at(adev, 1594 adev->mman.fw_vram_usage_start_offset, 1595 adev->mman.fw_vram_usage_size, 1596 &adev->mman.fw_vram_usage_reserved_bo, 1597 &adev->mman.fw_vram_usage_va); 1598 } 1599 1600 /** 1601 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver 1602 * 1603 * @adev: amdgpu_device pointer 1604 * 1605 * create bo vram reservation from drv. 1606 */ 1607 static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev) 1608 { 1609 u64 vram_size = adev->gmc.visible_vram_size; 1610 1611 adev->mman.drv_vram_usage_va = NULL; 1612 adev->mman.drv_vram_usage_reserved_bo = NULL; 1613 1614 if (adev->mman.drv_vram_usage_size == 0 || 1615 adev->mman.drv_vram_usage_size > vram_size) 1616 return 0; 1617 1618 return amdgpu_bo_create_kernel_at(adev, 1619 adev->mman.drv_vram_usage_start_offset, 1620 adev->mman.drv_vram_usage_size, 1621 &adev->mman.drv_vram_usage_reserved_bo, 1622 &adev->mman.drv_vram_usage_va); 1623 } 1624 1625 /* 1626 * Memoy training reservation functions 1627 */ 1628 1629 /** 1630 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1631 * 1632 * @adev: amdgpu_device pointer 1633 * 1634 * free memory training reserved vram if it has been reserved. 1635 */ 1636 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1637 { 1638 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1639 1640 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1641 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1642 ctx->c2p_bo = NULL; 1643 1644 return 0; 1645 } 1646 1647 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1648 { 1649 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1650 1651 memset(ctx, 0, sizeof(*ctx)); 1652 1653 ctx->c2p_train_data_offset = 1654 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1655 ctx->p2c_train_data_offset = 1656 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1657 ctx->train_data_size = 1658 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1659 1660 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1661 ctx->train_data_size, 1662 ctx->p2c_train_data_offset, 1663 ctx->c2p_train_data_offset); 1664 } 1665 1666 /* 1667 * reserve TMR memory at the top of VRAM which holds 1668 * IP Discovery data and is protected by PSP. 1669 */ 1670 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1671 { 1672 int ret; 1673 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1674 bool mem_train_support = false; 1675 1676 if (!amdgpu_sriov_vf(adev)) { 1677 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1678 mem_train_support = true; 1679 else 1680 DRM_DEBUG("memory training does not support!\n"); 1681 } 1682 1683 /* 1684 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1685 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1686 * 1687 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1688 * discovery data and G6 memory training data respectively 1689 */ 1690 adev->mman.discovery_tmr_size = 1691 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1692 if (!adev->mman.discovery_tmr_size) 1693 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1694 1695 if (mem_train_support) { 1696 /* reserve vram for mem train according to TMR location */ 1697 amdgpu_ttm_training_data_block_init(adev); 1698 ret = amdgpu_bo_create_kernel_at(adev, 1699 ctx->c2p_train_data_offset, 1700 ctx->train_data_size, 1701 &ctx->c2p_bo, 1702 NULL); 1703 if (ret) { 1704 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1705 amdgpu_ttm_training_reserve_vram_fini(adev); 1706 return ret; 1707 } 1708 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1709 } 1710 1711 ret = amdgpu_bo_create_kernel_at(adev, 1712 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1713 adev->mman.discovery_tmr_size, 1714 &adev->mman.discovery_memory, 1715 NULL); 1716 if (ret) { 1717 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1718 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1719 return ret; 1720 } 1721 1722 return 0; 1723 } 1724 1725 /* 1726 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1727 * gtt/vram related fields. 1728 * 1729 * This initializes all of the memory space pools that the TTM layer 1730 * will need such as the GTT space (system memory mapped to the device), 1731 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1732 * can be mapped per VMID. 1733 */ 1734 int amdgpu_ttm_init(struct amdgpu_device *adev) 1735 { 1736 uint64_t gtt_size; 1737 int r; 1738 1739 mutex_init(&adev->mman.gtt_window_lock); 1740 1741 /* No others user of address space so set it to 0 */ 1742 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1743 adev_to_drm(adev)->anon_inode->i_mapping, 1744 adev_to_drm(adev)->vma_offset_manager, 1745 adev->need_swiotlb, 1746 dma_addressing_limited(adev->dev)); 1747 if (r) { 1748 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1749 return r; 1750 } 1751 adev->mman.initialized = true; 1752 1753 /* Initialize VRAM pool with all of VRAM divided into pages */ 1754 r = amdgpu_vram_mgr_init(adev); 1755 if (r) { 1756 DRM_ERROR("Failed initializing VRAM heap.\n"); 1757 return r; 1758 } 1759 1760 /* Change the size here instead of the init above so only lpfn is affected */ 1761 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1762 #ifdef CONFIG_64BIT 1763 #ifdef CONFIG_X86 1764 if (adev->gmc.xgmi.connected_to_cpu) 1765 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1766 adev->gmc.visible_vram_size); 1767 1768 else 1769 #endif 1770 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1771 adev->gmc.visible_vram_size); 1772 #endif 1773 1774 /* 1775 *The reserved vram for firmware must be pinned to the specified 1776 *place on the VRAM, so reserve it early. 1777 */ 1778 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1779 if (r) { 1780 return r; 1781 } 1782 1783 /* 1784 *The reserved vram for driver must be pinned to the specified 1785 *place on the VRAM, so reserve it early. 1786 */ 1787 r = amdgpu_ttm_drv_reserve_vram_init(adev); 1788 if (r) 1789 return r; 1790 1791 /* 1792 * only NAVI10 and onwards ASIC support for IP discovery. 1793 * If IP discovery enabled, a block of memory should be 1794 * reserved for IP discovey. 1795 */ 1796 if (adev->mman.discovery_bin) { 1797 r = amdgpu_ttm_reserve_tmr(adev); 1798 if (r) 1799 return r; 1800 } 1801 1802 /* allocate memory as required for VGA 1803 * This is used for VGA emulation and pre-OS scanout buffers to 1804 * avoid display artifacts while transitioning between pre-OS 1805 * and driver. */ 1806 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1807 &adev->mman.stolen_vga_memory, 1808 NULL); 1809 if (r) 1810 return r; 1811 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1812 adev->mman.stolen_extended_size, 1813 &adev->mman.stolen_extended_memory, 1814 NULL); 1815 if (r) 1816 return r; 1817 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1818 adev->mman.stolen_reserved_size, 1819 &adev->mman.stolen_reserved_memory, 1820 NULL); 1821 if (r) 1822 return r; 1823 1824 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1825 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1826 1827 /* Compute GTT size, either based on TTM limit 1828 * or whatever the user passed on module init. 1829 */ 1830 if (amdgpu_gtt_size == -1) 1831 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT; 1832 else 1833 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1834 1835 /* Initialize GTT memory pool */ 1836 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1837 if (r) { 1838 DRM_ERROR("Failed initializing GTT heap.\n"); 1839 return r; 1840 } 1841 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1842 (unsigned)(gtt_size / (1024 * 1024))); 1843 1844 /* Initialize preemptible memory pool */ 1845 r = amdgpu_preempt_mgr_init(adev); 1846 if (r) { 1847 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1848 return r; 1849 } 1850 1851 /* Initialize various on-chip memory pools */ 1852 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1853 if (r) { 1854 DRM_ERROR("Failed initializing GDS heap.\n"); 1855 return r; 1856 } 1857 1858 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1859 if (r) { 1860 DRM_ERROR("Failed initializing gws heap.\n"); 1861 return r; 1862 } 1863 1864 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1865 if (r) { 1866 DRM_ERROR("Failed initializing oa heap.\n"); 1867 return r; 1868 } 1869 1870 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1871 AMDGPU_GEM_DOMAIN_GTT, 1872 &adev->mman.sdma_access_bo, NULL, 1873 &adev->mman.sdma_access_ptr)) 1874 DRM_WARN("Debug VRAM access will use slowpath MM access\n"); 1875 1876 return 0; 1877 } 1878 1879 /* 1880 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1881 */ 1882 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1883 { 1884 int idx; 1885 if (!adev->mman.initialized) 1886 return; 1887 1888 amdgpu_ttm_training_reserve_vram_fini(adev); 1889 /* return the stolen vga memory back to VRAM */ 1890 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1891 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1892 /* return the IP Discovery TMR memory back to VRAM */ 1893 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1894 if (adev->mman.stolen_reserved_size) 1895 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1896 NULL, NULL); 1897 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 1898 &adev->mman.sdma_access_ptr); 1899 amdgpu_ttm_fw_reserve_vram_fini(adev); 1900 amdgpu_ttm_drv_reserve_vram_fini(adev); 1901 1902 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1903 1904 if (adev->mman.aper_base_kaddr) 1905 iounmap(adev->mman.aper_base_kaddr); 1906 adev->mman.aper_base_kaddr = NULL; 1907 1908 drm_dev_exit(idx); 1909 } 1910 1911 amdgpu_vram_mgr_fini(adev); 1912 amdgpu_gtt_mgr_fini(adev); 1913 amdgpu_preempt_mgr_fini(adev); 1914 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1915 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1916 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1917 ttm_device_fini(&adev->mman.bdev); 1918 adev->mman.initialized = false; 1919 DRM_INFO("amdgpu: ttm finalized\n"); 1920 } 1921 1922 /** 1923 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1924 * 1925 * @adev: amdgpu_device pointer 1926 * @enable: true when we can use buffer functions. 1927 * 1928 * Enable/disable use of buffer functions during suspend/resume. This should 1929 * only be called at bootup or when userspace isn't running. 1930 */ 1931 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1932 { 1933 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1934 uint64_t size; 1935 int r; 1936 1937 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1938 adev->mman.buffer_funcs_enabled == enable) 1939 return; 1940 1941 if (enable) { 1942 struct amdgpu_ring *ring; 1943 struct drm_gpu_scheduler *sched; 1944 1945 ring = adev->mman.buffer_funcs_ring; 1946 sched = &ring->sched; 1947 r = drm_sched_entity_init(&adev->mman.entity, 1948 DRM_SCHED_PRIORITY_KERNEL, &sched, 1949 1, NULL); 1950 if (r) { 1951 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1952 r); 1953 return; 1954 } 1955 } else { 1956 drm_sched_entity_destroy(&adev->mman.entity); 1957 dma_fence_put(man->move); 1958 man->move = NULL; 1959 } 1960 1961 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1962 if (enable) 1963 size = adev->gmc.real_vram_size; 1964 else 1965 size = adev->gmc.visible_vram_size; 1966 man->size = size; 1967 adev->mman.buffer_funcs_enabled = enable; 1968 } 1969 1970 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, 1971 bool direct_submit, 1972 unsigned int num_dw, 1973 struct dma_resv *resv, 1974 bool vm_needs_flush, 1975 struct amdgpu_job **job) 1976 { 1977 enum amdgpu_ib_pool_type pool = direct_submit ? 1978 AMDGPU_IB_POOL_DIRECT : 1979 AMDGPU_IB_POOL_DELAYED; 1980 int r; 1981 1982 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity, 1983 AMDGPU_FENCE_OWNER_UNDEFINED, 1984 num_dw * 4, pool, job); 1985 if (r) 1986 return r; 1987 1988 if (vm_needs_flush) { 1989 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1990 adev->gmc.pdb0_bo : 1991 adev->gart.bo); 1992 (*job)->vm_needs_flush = true; 1993 } 1994 if (!resv) 1995 return 0; 1996 1997 return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, 1998 DMA_RESV_USAGE_BOOKKEEP); 1999 } 2000 2001 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2002 uint64_t dst_offset, uint32_t byte_count, 2003 struct dma_resv *resv, 2004 struct dma_fence **fence, bool direct_submit, 2005 bool vm_needs_flush, bool tmz) 2006 { 2007 struct amdgpu_device *adev = ring->adev; 2008 unsigned num_loops, num_dw; 2009 struct amdgpu_job *job; 2010 uint32_t max_bytes; 2011 unsigned i; 2012 int r; 2013 2014 if (!direct_submit && !ring->sched.ready) { 2015 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2016 return -EINVAL; 2017 } 2018 2019 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2020 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2021 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2022 r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, 2023 resv, vm_needs_flush, &job); 2024 if (r) 2025 return r; 2026 2027 for (i = 0; i < num_loops; i++) { 2028 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2029 2030 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2031 dst_offset, cur_size_in_bytes, tmz); 2032 2033 src_offset += cur_size_in_bytes; 2034 dst_offset += cur_size_in_bytes; 2035 byte_count -= cur_size_in_bytes; 2036 } 2037 2038 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2039 WARN_ON(job->ibs[0].length_dw > num_dw); 2040 if (direct_submit) 2041 r = amdgpu_job_submit_direct(job, ring, fence); 2042 else 2043 *fence = amdgpu_job_submit(job); 2044 if (r) 2045 goto error_free; 2046 2047 return r; 2048 2049 error_free: 2050 amdgpu_job_free(job); 2051 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2052 return r; 2053 } 2054 2055 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, 2056 uint64_t dst_addr, uint32_t byte_count, 2057 struct dma_resv *resv, 2058 struct dma_fence **fence, 2059 bool vm_needs_flush) 2060 { 2061 struct amdgpu_device *adev = ring->adev; 2062 unsigned int num_loops, num_dw; 2063 struct amdgpu_job *job; 2064 uint32_t max_bytes; 2065 unsigned int i; 2066 int r; 2067 2068 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2069 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); 2070 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); 2071 r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, 2072 &job); 2073 if (r) 2074 return r; 2075 2076 for (i = 0; i < num_loops; i++) { 2077 uint32_t cur_size = min(byte_count, max_bytes); 2078 2079 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2080 cur_size); 2081 2082 dst_addr += cur_size; 2083 byte_count -= cur_size; 2084 } 2085 2086 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2087 WARN_ON(job->ibs[0].length_dw > num_dw); 2088 *fence = amdgpu_job_submit(job); 2089 return 0; 2090 } 2091 2092 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2093 uint32_t src_data, 2094 struct dma_resv *resv, 2095 struct dma_fence **f) 2096 { 2097 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2098 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2099 struct dma_fence *fence = NULL; 2100 struct amdgpu_res_cursor dst; 2101 int r; 2102 2103 if (!adev->mman.buffer_funcs_enabled) { 2104 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2105 return -EINVAL; 2106 } 2107 2108 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); 2109 2110 mutex_lock(&adev->mman.gtt_window_lock); 2111 while (dst.remaining) { 2112 struct dma_fence *next; 2113 uint64_t cur_size, to; 2114 2115 /* Never fill more than 256MiB at once to avoid timeouts */ 2116 cur_size = min(dst.size, 256ULL << 20); 2117 2118 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst, 2119 1, ring, false, &cur_size, &to); 2120 if (r) 2121 goto error; 2122 2123 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, 2124 &next, true); 2125 if (r) 2126 goto error; 2127 2128 dma_fence_put(fence); 2129 fence = next; 2130 2131 amdgpu_res_next(&dst, cur_size); 2132 } 2133 error: 2134 mutex_unlock(&adev->mman.gtt_window_lock); 2135 if (f) 2136 *f = dma_fence_get(fence); 2137 dma_fence_put(fence); 2138 return r; 2139 } 2140 2141 /** 2142 * amdgpu_ttm_evict_resources - evict memory buffers 2143 * @adev: amdgpu device object 2144 * @mem_type: evicted BO's memory type 2145 * 2146 * Evicts all @mem_type buffers on the lru list of the memory type. 2147 * 2148 * Returns: 2149 * 0 for success or a negative error code on failure. 2150 */ 2151 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2152 { 2153 struct ttm_resource_manager *man; 2154 2155 switch (mem_type) { 2156 case TTM_PL_VRAM: 2157 case TTM_PL_TT: 2158 case AMDGPU_PL_GWS: 2159 case AMDGPU_PL_GDS: 2160 case AMDGPU_PL_OA: 2161 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2162 break; 2163 default: 2164 DRM_ERROR("Trying to evict invalid memory type\n"); 2165 return -EINVAL; 2166 } 2167 2168 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2169 } 2170 2171 #if defined(CONFIG_DEBUG_FS) 2172 2173 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2174 { 2175 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2176 2177 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2178 } 2179 2180 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2181 2182 /* 2183 * amdgpu_ttm_vram_read - Linear read access to VRAM 2184 * 2185 * Accesses VRAM via MMIO for debugging purposes. 2186 */ 2187 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2188 size_t size, loff_t *pos) 2189 { 2190 struct amdgpu_device *adev = file_inode(f)->i_private; 2191 ssize_t result = 0; 2192 2193 if (size & 0x3 || *pos & 0x3) 2194 return -EINVAL; 2195 2196 if (*pos >= adev->gmc.mc_vram_size) 2197 return -ENXIO; 2198 2199 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2200 while (size) { 2201 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2202 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2203 2204 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2205 if (copy_to_user(buf, value, bytes)) 2206 return -EFAULT; 2207 2208 result += bytes; 2209 buf += bytes; 2210 *pos += bytes; 2211 size -= bytes; 2212 } 2213 2214 return result; 2215 } 2216 2217 /* 2218 * amdgpu_ttm_vram_write - Linear write access to VRAM 2219 * 2220 * Accesses VRAM via MMIO for debugging purposes. 2221 */ 2222 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2223 size_t size, loff_t *pos) 2224 { 2225 struct amdgpu_device *adev = file_inode(f)->i_private; 2226 ssize_t result = 0; 2227 int r; 2228 2229 if (size & 0x3 || *pos & 0x3) 2230 return -EINVAL; 2231 2232 if (*pos >= adev->gmc.mc_vram_size) 2233 return -ENXIO; 2234 2235 while (size) { 2236 uint32_t value; 2237 2238 if (*pos >= adev->gmc.mc_vram_size) 2239 return result; 2240 2241 r = get_user(value, (uint32_t *)buf); 2242 if (r) 2243 return r; 2244 2245 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2246 2247 result += 4; 2248 buf += 4; 2249 *pos += 4; 2250 size -= 4; 2251 } 2252 2253 return result; 2254 } 2255 2256 static const struct file_operations amdgpu_ttm_vram_fops = { 2257 .owner = THIS_MODULE, 2258 .read = amdgpu_ttm_vram_read, 2259 .write = amdgpu_ttm_vram_write, 2260 .llseek = default_llseek, 2261 }; 2262 2263 /* 2264 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2265 * 2266 * This function is used to read memory that has been mapped to the 2267 * GPU and the known addresses are not physical addresses but instead 2268 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2269 */ 2270 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2271 size_t size, loff_t *pos) 2272 { 2273 struct amdgpu_device *adev = file_inode(f)->i_private; 2274 struct iommu_domain *dom; 2275 ssize_t result = 0; 2276 int r; 2277 2278 /* retrieve the IOMMU domain if any for this device */ 2279 dom = iommu_get_domain_for_dev(adev->dev); 2280 2281 while (size) { 2282 phys_addr_t addr = *pos & PAGE_MASK; 2283 loff_t off = *pos & ~PAGE_MASK; 2284 size_t bytes = PAGE_SIZE - off; 2285 unsigned long pfn; 2286 struct page *p; 2287 void *ptr; 2288 2289 bytes = bytes < size ? bytes : size; 2290 2291 /* Translate the bus address to a physical address. If 2292 * the domain is NULL it means there is no IOMMU active 2293 * and the address translation is the identity 2294 */ 2295 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2296 2297 pfn = addr >> PAGE_SHIFT; 2298 if (!pfn_valid(pfn)) 2299 return -EPERM; 2300 2301 p = pfn_to_page(pfn); 2302 if (p->mapping != adev->mman.bdev.dev_mapping) 2303 return -EPERM; 2304 2305 ptr = kmap_local_page(p); 2306 r = copy_to_user(buf, ptr + off, bytes); 2307 kunmap_local(ptr); 2308 if (r) 2309 return -EFAULT; 2310 2311 size -= bytes; 2312 *pos += bytes; 2313 result += bytes; 2314 } 2315 2316 return result; 2317 } 2318 2319 /* 2320 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2321 * 2322 * This function is used to write memory that has been mapped to the 2323 * GPU and the known addresses are not physical addresses but instead 2324 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2325 */ 2326 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2327 size_t size, loff_t *pos) 2328 { 2329 struct amdgpu_device *adev = file_inode(f)->i_private; 2330 struct iommu_domain *dom; 2331 ssize_t result = 0; 2332 int r; 2333 2334 dom = iommu_get_domain_for_dev(adev->dev); 2335 2336 while (size) { 2337 phys_addr_t addr = *pos & PAGE_MASK; 2338 loff_t off = *pos & ~PAGE_MASK; 2339 size_t bytes = PAGE_SIZE - off; 2340 unsigned long pfn; 2341 struct page *p; 2342 void *ptr; 2343 2344 bytes = bytes < size ? bytes : size; 2345 2346 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2347 2348 pfn = addr >> PAGE_SHIFT; 2349 if (!pfn_valid(pfn)) 2350 return -EPERM; 2351 2352 p = pfn_to_page(pfn); 2353 if (p->mapping != adev->mman.bdev.dev_mapping) 2354 return -EPERM; 2355 2356 ptr = kmap_local_page(p); 2357 r = copy_from_user(ptr + off, buf, bytes); 2358 kunmap_local(ptr); 2359 if (r) 2360 return -EFAULT; 2361 2362 size -= bytes; 2363 *pos += bytes; 2364 result += bytes; 2365 } 2366 2367 return result; 2368 } 2369 2370 static const struct file_operations amdgpu_ttm_iomem_fops = { 2371 .owner = THIS_MODULE, 2372 .read = amdgpu_iomem_read, 2373 .write = amdgpu_iomem_write, 2374 .llseek = default_llseek 2375 }; 2376 2377 #endif 2378 2379 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2380 { 2381 #if defined(CONFIG_DEBUG_FS) 2382 struct drm_minor *minor = adev_to_drm(adev)->primary; 2383 struct dentry *root = minor->debugfs_root; 2384 2385 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2386 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2387 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2388 &amdgpu_ttm_iomem_fops); 2389 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2390 &amdgpu_ttm_page_pool_fops); 2391 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2392 TTM_PL_VRAM), 2393 root, "amdgpu_vram_mm"); 2394 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2395 TTM_PL_TT), 2396 root, "amdgpu_gtt_mm"); 2397 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2398 AMDGPU_PL_GDS), 2399 root, "amdgpu_gds_mm"); 2400 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2401 AMDGPU_PL_GWS), 2402 root, "amdgpu_gws_mm"); 2403 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2404 AMDGPU_PL_OA), 2405 root, "amdgpu_oa_mm"); 2406 2407 #endif 2408 } 2409