1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 52 #include <drm/drm_debugfs.h> 53 #include <drm/amdgpu_drm.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "bif/bif_4_1_d.h" 62 63 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 64 65 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 66 unsigned int type, 67 uint64_t size) 68 { 69 return ttm_range_man_init(&adev->mman.bdev, type, 70 TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED, 71 false, size >> PAGE_SHIFT); 72 } 73 74 /** 75 * amdgpu_evict_flags - Compute placement flags 76 * 77 * @bo: The buffer object to evict 78 * @placement: Possible destination(s) for evicted BO 79 * 80 * Fill in placement data when ttm_bo_evict() is called 81 */ 82 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 83 struct ttm_placement *placement) 84 { 85 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 86 struct amdgpu_bo *abo; 87 static const struct ttm_place placements = { 88 .fpfn = 0, 89 .lpfn = 0, 90 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 91 }; 92 93 /* Don't handle scatter gather BOs */ 94 if (bo->type == ttm_bo_type_sg) { 95 placement->num_placement = 0; 96 placement->num_busy_placement = 0; 97 return; 98 } 99 100 /* Object isn't an AMDGPU object so ignore */ 101 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 102 placement->placement = &placements; 103 placement->busy_placement = &placements; 104 placement->num_placement = 1; 105 placement->num_busy_placement = 1; 106 return; 107 } 108 109 abo = ttm_to_amdgpu_bo(bo); 110 switch (bo->mem.mem_type) { 111 case AMDGPU_PL_GDS: 112 case AMDGPU_PL_GWS: 113 case AMDGPU_PL_OA: 114 placement->num_placement = 0; 115 placement->num_busy_placement = 0; 116 return; 117 118 case TTM_PL_VRAM: 119 if (!adev->mman.buffer_funcs_enabled) { 120 /* Move to system memory */ 121 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 122 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 123 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 124 amdgpu_bo_in_cpu_visible_vram(abo)) { 125 126 /* Try evicting to the CPU inaccessible part of VRAM 127 * first, but only set GTT as busy placement, so this 128 * BO will be evicted to GTT rather than causing other 129 * BOs to be evicted from VRAM 130 */ 131 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 132 AMDGPU_GEM_DOMAIN_GTT); 133 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 134 abo->placements[0].lpfn = 0; 135 abo->placement.busy_placement = &abo->placements[1]; 136 abo->placement.num_busy_placement = 1; 137 } else { 138 /* Move to GTT memory */ 139 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 140 } 141 break; 142 case TTM_PL_TT: 143 default: 144 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 145 break; 146 } 147 *placement = abo->placement; 148 } 149 150 /** 151 * amdgpu_verify_access - Verify access for a mmap call 152 * 153 * @bo: The buffer object to map 154 * @filp: The file pointer from the process performing the mmap 155 * 156 * This is called by ttm_bo_mmap() to verify whether a process 157 * has the right to mmap a BO to their process space. 158 */ 159 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 160 { 161 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 162 163 /* 164 * Don't verify access for KFD BOs. They don't have a GEM 165 * object associated with them. 166 */ 167 if (abo->kfd_bo) 168 return 0; 169 170 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 171 return -EPERM; 172 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 173 filp->private_data); 174 } 175 176 /** 177 * amdgpu_move_null - Register memory for a buffer object 178 * 179 * @bo: The bo to assign the memory to 180 * @new_mem: The memory to be assigned. 181 * 182 * Assign the memory from new_mem to the memory of the buffer object bo. 183 */ 184 static void amdgpu_move_null(struct ttm_buffer_object *bo, 185 struct ttm_resource *new_mem) 186 { 187 struct ttm_resource *old_mem = &bo->mem; 188 189 BUG_ON(old_mem->mm_node != NULL); 190 *old_mem = *new_mem; 191 new_mem->mm_node = NULL; 192 } 193 194 /** 195 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. 196 * 197 * @bo: The bo to assign the memory to. 198 * @mm_node: Memory manager node for drm allocator. 199 * @mem: The region where the bo resides. 200 * 201 */ 202 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 203 struct drm_mm_node *mm_node, 204 struct ttm_resource *mem) 205 { 206 uint64_t addr = 0; 207 208 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { 209 addr = mm_node->start << PAGE_SHIFT; 210 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev), 211 mem->mem_type); 212 } 213 return addr; 214 } 215 216 /** 217 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to 218 * @offset. It also modifies the offset to be within the drm_mm_node returned 219 * 220 * @mem: The region where the bo resides. 221 * @offset: The offset that drm_mm_node is used for finding. 222 * 223 */ 224 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem, 225 uint64_t *offset) 226 { 227 struct drm_mm_node *mm_node = mem->mm_node; 228 229 while (*offset >= (mm_node->size << PAGE_SHIFT)) { 230 *offset -= (mm_node->size << PAGE_SHIFT); 231 ++mm_node; 232 } 233 return mm_node; 234 } 235 236 /** 237 * amdgpu_ttm_map_buffer - Map memory into the GART windows 238 * @bo: buffer object to map 239 * @mem: memory object to map 240 * @mm_node: drm_mm node object to map 241 * @num_pages: number of pages to map 242 * @offset: offset into @mm_node where to start 243 * @window: which GART window to use 244 * @ring: DMA ring to use for the copy 245 * @tmz: if we should setup a TMZ enabled mapping 246 * @addr: resulting address inside the MC address space 247 * 248 * Setup one of the GART windows to access a specific piece of memory or return 249 * the physical address for local memory. 250 */ 251 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 252 struct ttm_resource *mem, 253 struct drm_mm_node *mm_node, 254 unsigned num_pages, uint64_t offset, 255 unsigned window, struct amdgpu_ring *ring, 256 bool tmz, uint64_t *addr) 257 { 258 struct amdgpu_device *adev = ring->adev; 259 struct amdgpu_job *job; 260 unsigned num_dw, num_bytes; 261 struct dma_fence *fence; 262 uint64_t src_addr, dst_addr; 263 void *cpu_addr; 264 uint64_t flags; 265 unsigned int i; 266 int r; 267 268 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 269 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 270 271 /* Map only what can't be accessed directly */ 272 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 273 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; 274 return 0; 275 } 276 277 *addr = adev->gmc.gart_start; 278 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 279 AMDGPU_GPU_PAGE_SIZE; 280 *addr += offset & ~PAGE_MASK; 281 282 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 283 num_bytes = num_pages * 8; 284 285 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 286 AMDGPU_IB_POOL_DELAYED, &job); 287 if (r) 288 return r; 289 290 src_addr = num_dw * 4; 291 src_addr += job->ibs[0].gpu_addr; 292 293 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 294 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 295 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 296 dst_addr, num_bytes, false); 297 298 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 299 WARN_ON(job->ibs[0].length_dw > num_dw); 300 301 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 302 if (tmz) 303 flags |= AMDGPU_PTE_TMZ; 304 305 cpu_addr = &job->ibs[0].ptr[num_dw]; 306 307 if (mem->mem_type == TTM_PL_TT) { 308 struct ttm_dma_tt *dma; 309 dma_addr_t *dma_address; 310 311 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm); 312 dma_address = &dma->dma_address[offset >> PAGE_SHIFT]; 313 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, 314 cpu_addr); 315 if (r) 316 goto error_free; 317 } else { 318 dma_addr_t dma_address; 319 320 dma_address = (mm_node->start << PAGE_SHIFT) + offset; 321 dma_address += adev->vm_manager.vram_base_offset; 322 323 for (i = 0; i < num_pages; ++i) { 324 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 325 &dma_address, flags, cpu_addr); 326 if (r) 327 goto error_free; 328 329 dma_address += PAGE_SIZE; 330 } 331 } 332 333 r = amdgpu_job_submit(job, &adev->mman.entity, 334 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 335 if (r) 336 goto error_free; 337 338 dma_fence_put(fence); 339 340 return r; 341 342 error_free: 343 amdgpu_job_free(job); 344 return r; 345 } 346 347 /** 348 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 349 * @adev: amdgpu device 350 * @src: buffer/address where to read from 351 * @dst: buffer/address where to write to 352 * @size: number of bytes to copy 353 * @tmz: if a secure copy should be used 354 * @resv: resv object to sync to 355 * @f: Returns the last fence if multiple jobs are submitted. 356 * 357 * The function copies @size bytes from {src->mem + src->offset} to 358 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 359 * move and different for a BO to BO copy. 360 * 361 */ 362 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 363 const struct amdgpu_copy_mem *src, 364 const struct amdgpu_copy_mem *dst, 365 uint64_t size, bool tmz, 366 struct dma_resv *resv, 367 struct dma_fence **f) 368 { 369 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 370 AMDGPU_GPU_PAGE_SIZE); 371 372 uint64_t src_node_size, dst_node_size, src_offset, dst_offset; 373 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 374 struct drm_mm_node *src_mm, *dst_mm; 375 struct dma_fence *fence = NULL; 376 int r = 0; 377 378 if (!adev->mman.buffer_funcs_enabled) { 379 DRM_ERROR("Trying to move memory with ring turned off.\n"); 380 return -EINVAL; 381 } 382 383 src_offset = src->offset; 384 if (src->mem->mm_node) { 385 src_mm = amdgpu_find_mm_node(src->mem, &src_offset); 386 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; 387 } else { 388 src_mm = NULL; 389 src_node_size = ULLONG_MAX; 390 } 391 392 dst_offset = dst->offset; 393 if (dst->mem->mm_node) { 394 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); 395 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; 396 } else { 397 dst_mm = NULL; 398 dst_node_size = ULLONG_MAX; 399 } 400 401 mutex_lock(&adev->mman.gtt_window_lock); 402 403 while (size) { 404 uint32_t src_page_offset = src_offset & ~PAGE_MASK; 405 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; 406 struct dma_fence *next; 407 uint32_t cur_size; 408 uint64_t from, to; 409 410 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 411 * begins at an offset, then adjust the size accordingly 412 */ 413 cur_size = max(src_page_offset, dst_page_offset); 414 cur_size = min(min3(src_node_size, dst_node_size, size), 415 (uint64_t)(GTT_MAX_BYTES - cur_size)); 416 417 /* Map src to window 0 and dst to window 1. */ 418 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, 419 PFN_UP(cur_size + src_page_offset), 420 src_offset, 0, ring, tmz, &from); 421 if (r) 422 goto error; 423 424 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, 425 PFN_UP(cur_size + dst_page_offset), 426 dst_offset, 1, ring, tmz, &to); 427 if (r) 428 goto error; 429 430 r = amdgpu_copy_buffer(ring, from, to, cur_size, 431 resv, &next, false, true, tmz); 432 if (r) 433 goto error; 434 435 dma_fence_put(fence); 436 fence = next; 437 438 size -= cur_size; 439 if (!size) 440 break; 441 442 src_node_size -= cur_size; 443 if (!src_node_size) { 444 ++src_mm; 445 src_node_size = src_mm->size << PAGE_SHIFT; 446 src_offset = 0; 447 } else { 448 src_offset += cur_size; 449 } 450 451 dst_node_size -= cur_size; 452 if (!dst_node_size) { 453 ++dst_mm; 454 dst_node_size = dst_mm->size << PAGE_SHIFT; 455 dst_offset = 0; 456 } else { 457 dst_offset += cur_size; 458 } 459 } 460 error: 461 mutex_unlock(&adev->mman.gtt_window_lock); 462 if (f) 463 *f = dma_fence_get(fence); 464 dma_fence_put(fence); 465 return r; 466 } 467 468 /** 469 * amdgpu_move_blit - Copy an entire buffer to another buffer 470 * 471 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 472 * help move buffers to and from VRAM. 473 */ 474 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 475 bool evict, bool no_wait_gpu, 476 struct ttm_resource *new_mem, 477 struct ttm_resource *old_mem) 478 { 479 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 480 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 481 struct amdgpu_copy_mem src, dst; 482 struct dma_fence *fence = NULL; 483 int r; 484 485 src.bo = bo; 486 dst.bo = bo; 487 src.mem = old_mem; 488 dst.mem = new_mem; 489 src.offset = 0; 490 dst.offset = 0; 491 492 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 493 new_mem->num_pages << PAGE_SHIFT, 494 amdgpu_bo_encrypted(abo), 495 bo->base.resv, &fence); 496 if (r) 497 goto error; 498 499 /* clear the space being freed */ 500 if (old_mem->mem_type == TTM_PL_VRAM && 501 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 502 struct dma_fence *wipe_fence = NULL; 503 504 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 505 NULL, &wipe_fence); 506 if (r) { 507 goto error; 508 } else if (wipe_fence) { 509 dma_fence_put(fence); 510 fence = wipe_fence; 511 } 512 } 513 514 /* Always block for VM page tables before committing the new location */ 515 if (bo->type == ttm_bo_type_kernel) 516 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem); 517 else 518 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 519 dma_fence_put(fence); 520 return r; 521 522 error: 523 if (fence) 524 dma_fence_wait(fence, false); 525 dma_fence_put(fence); 526 return r; 527 } 528 529 /** 530 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer 531 * 532 * Called by amdgpu_bo_move(). 533 */ 534 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 535 struct ttm_operation_ctx *ctx, 536 struct ttm_resource *new_mem) 537 { 538 struct ttm_resource *old_mem = &bo->mem; 539 struct ttm_resource tmp_mem; 540 struct ttm_place placements; 541 struct ttm_placement placement; 542 int r; 543 544 /* create space/pages for new_mem in GTT space */ 545 tmp_mem = *new_mem; 546 tmp_mem.mm_node = NULL; 547 placement.num_placement = 1; 548 placement.placement = &placements; 549 placement.num_busy_placement = 1; 550 placement.busy_placement = &placements; 551 placements.fpfn = 0; 552 placements.lpfn = 0; 553 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 554 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 555 if (unlikely(r)) { 556 pr_err("Failed to find GTT space for blit from VRAM\n"); 557 return r; 558 } 559 560 /* set caching flags */ 561 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 562 if (unlikely(r)) { 563 goto out_cleanup; 564 } 565 566 /* Bind the memory to the GTT space */ 567 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx); 568 if (unlikely(r)) { 569 goto out_cleanup; 570 } 571 572 /* blit VRAM to GTT */ 573 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem); 574 if (unlikely(r)) { 575 goto out_cleanup; 576 } 577 578 /* move BO (in tmp_mem) to new_mem */ 579 r = ttm_bo_move_ttm(bo, ctx, new_mem); 580 out_cleanup: 581 ttm_bo_mem_put(bo, &tmp_mem); 582 return r; 583 } 584 585 /** 586 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM 587 * 588 * Called by amdgpu_bo_move(). 589 */ 590 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 591 struct ttm_operation_ctx *ctx, 592 struct ttm_resource *new_mem) 593 { 594 struct ttm_resource *old_mem = &bo->mem; 595 struct ttm_resource tmp_mem; 596 struct ttm_placement placement; 597 struct ttm_place placements; 598 int r; 599 600 /* make space in GTT for old_mem buffer */ 601 tmp_mem = *new_mem; 602 tmp_mem.mm_node = NULL; 603 placement.num_placement = 1; 604 placement.placement = &placements; 605 placement.num_busy_placement = 1; 606 placement.busy_placement = &placements; 607 placements.fpfn = 0; 608 placements.lpfn = 0; 609 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 610 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 611 if (unlikely(r)) { 612 pr_err("Failed to find GTT space for blit to VRAM\n"); 613 return r; 614 } 615 616 /* move/bind old memory to GTT space */ 617 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); 618 if (unlikely(r)) { 619 goto out_cleanup; 620 } 621 622 /* copy to VRAM */ 623 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem); 624 if (unlikely(r)) { 625 goto out_cleanup; 626 } 627 out_cleanup: 628 ttm_bo_mem_put(bo, &tmp_mem); 629 return r; 630 } 631 632 /** 633 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 634 * 635 * Called by amdgpu_bo_move() 636 */ 637 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 638 struct ttm_resource *mem) 639 { 640 struct drm_mm_node *nodes = mem->mm_node; 641 642 if (mem->mem_type == TTM_PL_SYSTEM || 643 mem->mem_type == TTM_PL_TT) 644 return true; 645 if (mem->mem_type != TTM_PL_VRAM) 646 return false; 647 648 /* ttm_resource_ioremap only supports contiguous memory */ 649 if (nodes->size != mem->num_pages) 650 return false; 651 652 return ((nodes->start + nodes->size) << PAGE_SHIFT) 653 <= adev->gmc.visible_vram_size; 654 } 655 656 /** 657 * amdgpu_bo_move - Move a buffer object to a new memory location 658 * 659 * Called by ttm_bo_handle_move_mem() 660 */ 661 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 662 struct ttm_operation_ctx *ctx, 663 struct ttm_resource *new_mem) 664 { 665 struct amdgpu_device *adev; 666 struct amdgpu_bo *abo; 667 struct ttm_resource *old_mem = &bo->mem; 668 int r; 669 670 /* Can't move a pinned BO */ 671 abo = ttm_to_amdgpu_bo(bo); 672 if (WARN_ON_ONCE(abo->pin_count > 0)) 673 return -EINVAL; 674 675 adev = amdgpu_ttm_adev(bo->bdev); 676 677 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 678 amdgpu_move_null(bo, new_mem); 679 return 0; 680 } 681 if ((old_mem->mem_type == TTM_PL_TT && 682 new_mem->mem_type == TTM_PL_SYSTEM) || 683 (old_mem->mem_type == TTM_PL_SYSTEM && 684 new_mem->mem_type == TTM_PL_TT)) { 685 /* bind is enough */ 686 amdgpu_move_null(bo, new_mem); 687 return 0; 688 } 689 if (old_mem->mem_type == AMDGPU_PL_GDS || 690 old_mem->mem_type == AMDGPU_PL_GWS || 691 old_mem->mem_type == AMDGPU_PL_OA || 692 new_mem->mem_type == AMDGPU_PL_GDS || 693 new_mem->mem_type == AMDGPU_PL_GWS || 694 new_mem->mem_type == AMDGPU_PL_OA) { 695 /* Nothing to save here */ 696 amdgpu_move_null(bo, new_mem); 697 return 0; 698 } 699 700 if (!adev->mman.buffer_funcs_enabled) { 701 r = -ENODEV; 702 goto memcpy; 703 } 704 705 if (old_mem->mem_type == TTM_PL_VRAM && 706 new_mem->mem_type == TTM_PL_SYSTEM) { 707 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); 708 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 709 new_mem->mem_type == TTM_PL_VRAM) { 710 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); 711 } else { 712 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, 713 new_mem, old_mem); 714 } 715 716 if (r) { 717 memcpy: 718 /* Check that all memory is CPU accessible */ 719 if (!amdgpu_mem_visible(adev, old_mem) || 720 !amdgpu_mem_visible(adev, new_mem)) { 721 pr_err("Move buffer fallback to memcpy unavailable\n"); 722 return r; 723 } 724 725 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 726 if (r) 727 return r; 728 } 729 730 if (bo->type == ttm_bo_type_device && 731 new_mem->mem_type == TTM_PL_VRAM && 732 old_mem->mem_type != TTM_PL_VRAM) { 733 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 734 * accesses the BO after it's moved. 735 */ 736 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 737 } 738 739 /* update statistics */ 740 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 741 return 0; 742 } 743 744 /** 745 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 746 * 747 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 748 */ 749 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) 750 { 751 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 752 struct drm_mm_node *mm_node = mem->mm_node; 753 754 mem->bus.addr = NULL; 755 mem->bus.offset = 0; 756 mem->bus.size = mem->num_pages << PAGE_SHIFT; 757 mem->bus.base = 0; 758 mem->bus.is_iomem = false; 759 760 switch (mem->mem_type) { 761 case TTM_PL_SYSTEM: 762 /* system memory */ 763 return 0; 764 case TTM_PL_TT: 765 break; 766 case TTM_PL_VRAM: 767 mem->bus.offset = mem->start << PAGE_SHIFT; 768 /* check if it's visible */ 769 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size) 770 return -EINVAL; 771 /* Only physically contiguous buffers apply. In a contiguous 772 * buffer, size of the first mm_node would match the number of 773 * pages in ttm_resource. 774 */ 775 if (adev->mman.aper_base_kaddr && 776 (mm_node->size == mem->num_pages)) 777 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 778 mem->bus.offset; 779 780 mem->bus.base = adev->gmc.aper_base; 781 mem->bus.is_iomem = true; 782 break; 783 default: 784 return -EINVAL; 785 } 786 return 0; 787 } 788 789 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 790 unsigned long page_offset) 791 { 792 uint64_t offset = (page_offset << PAGE_SHIFT); 793 struct drm_mm_node *mm; 794 795 mm = amdgpu_find_mm_node(&bo->mem, &offset); 796 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + 797 (offset >> PAGE_SHIFT); 798 } 799 800 /** 801 * amdgpu_ttm_domain_start - Returns GPU start address 802 * @adev: amdgpu device object 803 * @type: type of the memory 804 * 805 * Returns: 806 * GPU start address of a memory domain 807 */ 808 809 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 810 { 811 switch (type) { 812 case TTM_PL_TT: 813 return adev->gmc.gart_start; 814 case TTM_PL_VRAM: 815 return adev->gmc.vram_start; 816 } 817 818 return 0; 819 } 820 821 /* 822 * TTM backend functions. 823 */ 824 struct amdgpu_ttm_tt { 825 struct ttm_dma_tt ttm; 826 struct drm_gem_object *gobj; 827 u64 offset; 828 uint64_t userptr; 829 struct task_struct *usertask; 830 uint32_t userflags; 831 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 832 struct hmm_range *range; 833 #endif 834 }; 835 836 #ifdef CONFIG_DRM_AMDGPU_USERPTR 837 /** 838 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 839 * memory and start HMM tracking CPU page table update 840 * 841 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 842 * once afterwards to stop HMM tracking 843 */ 844 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 845 { 846 struct ttm_tt *ttm = bo->tbo.ttm; 847 struct amdgpu_ttm_tt *gtt = (void *)ttm; 848 unsigned long start = gtt->userptr; 849 struct vm_area_struct *vma; 850 struct hmm_range *range; 851 unsigned long timeout; 852 struct mm_struct *mm; 853 unsigned long i; 854 int r = 0; 855 856 mm = bo->notifier.mm; 857 if (unlikely(!mm)) { 858 DRM_DEBUG_DRIVER("BO is not registered?\n"); 859 return -EFAULT; 860 } 861 862 /* Another get_user_pages is running at the same time?? */ 863 if (WARN_ON(gtt->range)) 864 return -EFAULT; 865 866 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 867 return -ESRCH; 868 869 range = kzalloc(sizeof(*range), GFP_KERNEL); 870 if (unlikely(!range)) { 871 r = -ENOMEM; 872 goto out; 873 } 874 range->notifier = &bo->notifier; 875 range->start = bo->notifier.interval_tree.start; 876 range->end = bo->notifier.interval_tree.last + 1; 877 range->default_flags = HMM_PFN_REQ_FAULT; 878 if (!amdgpu_ttm_tt_is_readonly(ttm)) 879 range->default_flags |= HMM_PFN_REQ_WRITE; 880 881 range->hmm_pfns = kvmalloc_array(ttm->num_pages, 882 sizeof(*range->hmm_pfns), GFP_KERNEL); 883 if (unlikely(!range->hmm_pfns)) { 884 r = -ENOMEM; 885 goto out_free_ranges; 886 } 887 888 mmap_read_lock(mm); 889 vma = find_vma(mm, start); 890 if (unlikely(!vma || start < vma->vm_start)) { 891 r = -EFAULT; 892 goto out_unlock; 893 } 894 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 895 vma->vm_file)) { 896 r = -EPERM; 897 goto out_unlock; 898 } 899 mmap_read_unlock(mm); 900 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 901 902 retry: 903 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 904 905 mmap_read_lock(mm); 906 r = hmm_range_fault(range); 907 mmap_read_unlock(mm); 908 if (unlikely(r)) { 909 /* 910 * FIXME: This timeout should encompass the retry from 911 * mmu_interval_read_retry() as well. 912 */ 913 if (r == -EBUSY && !time_after(jiffies, timeout)) 914 goto retry; 915 goto out_free_pfns; 916 } 917 918 /* 919 * Due to default_flags, all pages are HMM_PFN_VALID or 920 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside 921 * the notifier_lock, and mmu_interval_read_retry() must be done first. 922 */ 923 for (i = 0; i < ttm->num_pages; i++) 924 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); 925 926 gtt->range = range; 927 mmput(mm); 928 929 return 0; 930 931 out_unlock: 932 mmap_read_unlock(mm); 933 out_free_pfns: 934 kvfree(range->hmm_pfns); 935 out_free_ranges: 936 kfree(range); 937 out: 938 mmput(mm); 939 return r; 940 } 941 942 /** 943 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 944 * Check if the pages backing this ttm range have been invalidated 945 * 946 * Returns: true if pages are still valid 947 */ 948 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 949 { 950 struct amdgpu_ttm_tt *gtt = (void *)ttm; 951 bool r = false; 952 953 if (!gtt || !gtt->userptr) 954 return false; 955 956 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n", 957 gtt->userptr, ttm->num_pages); 958 959 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 960 "No user pages to check\n"); 961 962 if (gtt->range) { 963 /* 964 * FIXME: Must always hold notifier_lock for this, and must 965 * not ignore the return code. 966 */ 967 r = mmu_interval_read_retry(gtt->range->notifier, 968 gtt->range->notifier_seq); 969 kvfree(gtt->range->hmm_pfns); 970 kfree(gtt->range); 971 gtt->range = NULL; 972 } 973 974 return !r; 975 } 976 #endif 977 978 /** 979 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 980 * 981 * Called by amdgpu_cs_list_validate(). This creates the page list 982 * that backs user memory and will ultimately be mapped into the device 983 * address space. 984 */ 985 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 986 { 987 unsigned long i; 988 989 for (i = 0; i < ttm->num_pages; ++i) 990 ttm->pages[i] = pages ? pages[i] : NULL; 991 } 992 993 /** 994 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 995 * 996 * Called by amdgpu_ttm_backend_bind() 997 **/ 998 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 999 { 1000 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1001 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1002 int r; 1003 1004 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1005 enum dma_data_direction direction = write ? 1006 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1007 1008 /* Allocate an SG array and squash pages into it */ 1009 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 1010 ttm->num_pages << PAGE_SHIFT, 1011 GFP_KERNEL); 1012 if (r) 1013 goto release_sg; 1014 1015 /* Map SG to device */ 1016 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 1017 if (r) 1018 goto release_sg; 1019 1020 /* convert SG to linear array of pages and dma addresses */ 1021 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1022 gtt->ttm.dma_address, ttm->num_pages); 1023 1024 return 0; 1025 1026 release_sg: 1027 kfree(ttm->sg); 1028 return r; 1029 } 1030 1031 /** 1032 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 1033 */ 1034 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 1035 { 1036 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1037 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1038 1039 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1040 enum dma_data_direction direction = write ? 1041 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1042 1043 /* double check that we don't free the table twice */ 1044 if (!ttm->sg->sgl) 1045 return; 1046 1047 /* unmap the pages mapped to the device */ 1048 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 1049 sg_free_table(ttm->sg); 1050 1051 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 1052 if (gtt->range) { 1053 unsigned long i; 1054 1055 for (i = 0; i < ttm->num_pages; i++) { 1056 if (ttm->pages[i] != 1057 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 1058 break; 1059 } 1060 1061 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 1062 } 1063 #endif 1064 } 1065 1066 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 1067 struct ttm_buffer_object *tbo, 1068 uint64_t flags) 1069 { 1070 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 1071 struct ttm_tt *ttm = tbo->ttm; 1072 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1073 int r; 1074 1075 if (amdgpu_bo_encrypted(abo)) 1076 flags |= AMDGPU_PTE_TMZ; 1077 1078 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 1079 uint64_t page_idx = 1; 1080 1081 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 1082 ttm->pages, gtt->ttm.dma_address, flags); 1083 if (r) 1084 goto gart_bind_fail; 1085 1086 /* The memory type of the first page defaults to UC. Now 1087 * modify the memory type to NC from the second page of 1088 * the BO onward. 1089 */ 1090 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1091 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 1092 1093 r = amdgpu_gart_bind(adev, 1094 gtt->offset + (page_idx << PAGE_SHIFT), 1095 ttm->num_pages - page_idx, 1096 &ttm->pages[page_idx], 1097 &(gtt->ttm.dma_address[page_idx]), flags); 1098 } else { 1099 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1100 ttm->pages, gtt->ttm.dma_address, flags); 1101 } 1102 1103 gart_bind_fail: 1104 if (r) 1105 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1106 ttm->num_pages, gtt->offset); 1107 1108 return r; 1109 } 1110 1111 /** 1112 * amdgpu_ttm_backend_bind - Bind GTT memory 1113 * 1114 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 1115 * This handles binding GTT memory to the device address space. 1116 */ 1117 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 1118 struct ttm_resource *bo_mem) 1119 { 1120 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1121 struct amdgpu_ttm_tt *gtt = (void*)ttm; 1122 uint64_t flags; 1123 int r = 0; 1124 1125 if (gtt->userptr) { 1126 r = amdgpu_ttm_tt_pin_userptr(ttm); 1127 if (r) { 1128 DRM_ERROR("failed to pin userptr\n"); 1129 return r; 1130 } 1131 } 1132 if (!ttm->num_pages) { 1133 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 1134 ttm->num_pages, bo_mem, ttm); 1135 } 1136 1137 if (bo_mem->mem_type == AMDGPU_PL_GDS || 1138 bo_mem->mem_type == AMDGPU_PL_GWS || 1139 bo_mem->mem_type == AMDGPU_PL_OA) 1140 return -EINVAL; 1141 1142 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 1143 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 1144 return 0; 1145 } 1146 1147 /* compute PTE flags relevant to this BO memory */ 1148 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 1149 1150 /* bind pages into GART page tables */ 1151 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 1152 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1153 ttm->pages, gtt->ttm.dma_address, flags); 1154 1155 if (r) 1156 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1157 ttm->num_pages, gtt->offset); 1158 return r; 1159 } 1160 1161 /** 1162 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object 1163 */ 1164 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1165 { 1166 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1167 struct ttm_operation_ctx ctx = { false, false }; 1168 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; 1169 struct ttm_resource tmp; 1170 struct ttm_placement placement; 1171 struct ttm_place placements; 1172 uint64_t addr, flags; 1173 int r; 1174 1175 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1176 return 0; 1177 1178 addr = amdgpu_gmc_agp_addr(bo); 1179 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1180 bo->mem.start = addr >> PAGE_SHIFT; 1181 } else { 1182 1183 /* allocate GART space */ 1184 tmp = bo->mem; 1185 tmp.mm_node = NULL; 1186 placement.num_placement = 1; 1187 placement.placement = &placements; 1188 placement.num_busy_placement = 1; 1189 placement.busy_placement = &placements; 1190 placements.fpfn = 0; 1191 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1192 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | 1193 TTM_PL_FLAG_TT; 1194 1195 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1196 if (unlikely(r)) 1197 return r; 1198 1199 /* compute PTE flags for this buffer object */ 1200 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1201 1202 /* Bind pages */ 1203 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1204 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1205 if (unlikely(r)) { 1206 ttm_bo_mem_put(bo, &tmp); 1207 return r; 1208 } 1209 1210 ttm_bo_mem_put(bo, &bo->mem); 1211 bo->mem = tmp; 1212 } 1213 1214 return 0; 1215 } 1216 1217 /** 1218 * amdgpu_ttm_recover_gart - Rebind GTT pages 1219 * 1220 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1221 * rebind GTT pages during a GPU reset. 1222 */ 1223 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1224 { 1225 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1226 uint64_t flags; 1227 int r; 1228 1229 if (!tbo->ttm) 1230 return 0; 1231 1232 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1233 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1234 1235 return r; 1236 } 1237 1238 /** 1239 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1240 * 1241 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1242 * ttm_tt_destroy(). 1243 */ 1244 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 1245 { 1246 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1247 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1248 int r; 1249 1250 /* if the pages have userptr pinning then clear that first */ 1251 if (gtt->userptr) 1252 amdgpu_ttm_tt_unpin_userptr(ttm); 1253 1254 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1255 return 0; 1256 1257 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1258 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1259 if (r) 1260 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", 1261 gtt->ttm.ttm.num_pages, gtt->offset); 1262 return r; 1263 } 1264 1265 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 1266 { 1267 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1268 1269 if (gtt->usertask) 1270 put_task_struct(gtt->usertask); 1271 1272 ttm_dma_tt_fini(>t->ttm); 1273 kfree(gtt); 1274 } 1275 1276 static struct ttm_backend_func amdgpu_backend_func = { 1277 .bind = &amdgpu_ttm_backend_bind, 1278 .unbind = &amdgpu_ttm_backend_unbind, 1279 .destroy = &amdgpu_ttm_backend_destroy, 1280 }; 1281 1282 /** 1283 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1284 * 1285 * @bo: The buffer object to create a GTT ttm_tt object around 1286 * 1287 * Called by ttm_tt_create(). 1288 */ 1289 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1290 uint32_t page_flags) 1291 { 1292 struct amdgpu_ttm_tt *gtt; 1293 1294 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1295 if (gtt == NULL) { 1296 return NULL; 1297 } 1298 gtt->ttm.ttm.func = &amdgpu_backend_func; 1299 gtt->gobj = &bo->base; 1300 1301 /* allocate space for the uninitialized page entries */ 1302 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) { 1303 kfree(gtt); 1304 return NULL; 1305 } 1306 return >t->ttm.ttm; 1307 } 1308 1309 /** 1310 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1311 * 1312 * Map the pages of a ttm_tt object to an address space visible 1313 * to the underlying device. 1314 */ 1315 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, 1316 struct ttm_operation_ctx *ctx) 1317 { 1318 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1319 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1320 1321 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1322 if (gtt && gtt->userptr) { 1323 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1324 if (!ttm->sg) 1325 return -ENOMEM; 1326 1327 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1328 ttm->state = tt_unbound; 1329 return 0; 1330 } 1331 1332 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1333 if (!ttm->sg) { 1334 struct dma_buf_attachment *attach; 1335 struct sg_table *sgt; 1336 1337 attach = gtt->gobj->import_attach; 1338 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1339 if (IS_ERR(sgt)) 1340 return PTR_ERR(sgt); 1341 1342 ttm->sg = sgt; 1343 } 1344 1345 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1346 gtt->ttm.dma_address, 1347 ttm->num_pages); 1348 ttm->state = tt_unbound; 1349 return 0; 1350 } 1351 1352 #ifdef CONFIG_SWIOTLB 1353 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1354 return ttm_dma_populate(>t->ttm, adev->dev, ctx); 1355 } 1356 #endif 1357 1358 /* fall back to generic helper to populate the page array 1359 * and map them to the device */ 1360 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx); 1361 } 1362 1363 /** 1364 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1365 * 1366 * Unmaps pages of a ttm_tt object from the device address space and 1367 * unpopulates the page array backing it. 1368 */ 1369 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 1370 { 1371 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1372 struct amdgpu_device *adev; 1373 1374 if (gtt && gtt->userptr) { 1375 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1376 kfree(ttm->sg); 1377 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1378 return; 1379 } 1380 1381 if (ttm->sg && gtt->gobj->import_attach) { 1382 struct dma_buf_attachment *attach; 1383 1384 attach = gtt->gobj->import_attach; 1385 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1386 ttm->sg = NULL; 1387 return; 1388 } 1389 1390 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1391 return; 1392 1393 adev = amdgpu_ttm_adev(ttm->bdev); 1394 1395 #ifdef CONFIG_SWIOTLB 1396 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1397 ttm_dma_unpopulate(>t->ttm, adev->dev); 1398 return; 1399 } 1400 #endif 1401 1402 /* fall back to generic helper to unmap and unpopulate array */ 1403 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); 1404 } 1405 1406 /** 1407 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1408 * task 1409 * 1410 * @bo: The ttm_buffer_object to bind this userptr to 1411 * @addr: The address in the current tasks VM space to use 1412 * @flags: Requirements of userptr object. 1413 * 1414 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1415 * to current task 1416 */ 1417 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1418 uint64_t addr, uint32_t flags) 1419 { 1420 struct amdgpu_ttm_tt *gtt; 1421 1422 if (!bo->ttm) { 1423 /* TODO: We want a separate TTM object type for userptrs */ 1424 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1425 if (bo->ttm == NULL) 1426 return -ENOMEM; 1427 } 1428 1429 gtt = (void*)bo->ttm; 1430 gtt->userptr = addr; 1431 gtt->userflags = flags; 1432 1433 if (gtt->usertask) 1434 put_task_struct(gtt->usertask); 1435 gtt->usertask = current->group_leader; 1436 get_task_struct(gtt->usertask); 1437 1438 return 0; 1439 } 1440 1441 /** 1442 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1443 */ 1444 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1445 { 1446 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1447 1448 if (gtt == NULL) 1449 return NULL; 1450 1451 if (gtt->usertask == NULL) 1452 return NULL; 1453 1454 return gtt->usertask->mm; 1455 } 1456 1457 /** 1458 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1459 * address range for the current task. 1460 * 1461 */ 1462 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1463 unsigned long end) 1464 { 1465 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1466 unsigned long size; 1467 1468 if (gtt == NULL || !gtt->userptr) 1469 return false; 1470 1471 /* Return false if no part of the ttm_tt object lies within 1472 * the range 1473 */ 1474 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 1475 if (gtt->userptr > end || gtt->userptr + size <= start) 1476 return false; 1477 1478 return true; 1479 } 1480 1481 /** 1482 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1483 */ 1484 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1485 { 1486 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1487 1488 if (gtt == NULL || !gtt->userptr) 1489 return false; 1490 1491 return true; 1492 } 1493 1494 /** 1495 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1496 */ 1497 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1498 { 1499 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1500 1501 if (gtt == NULL) 1502 return false; 1503 1504 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1505 } 1506 1507 /** 1508 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1509 * 1510 * @ttm: The ttm_tt object to compute the flags for 1511 * @mem: The memory registry backing this ttm_tt object 1512 * 1513 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1514 */ 1515 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1516 { 1517 uint64_t flags = 0; 1518 1519 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1520 flags |= AMDGPU_PTE_VALID; 1521 1522 if (mem && mem->mem_type == TTM_PL_TT) { 1523 flags |= AMDGPU_PTE_SYSTEM; 1524 1525 if (ttm->caching_state == tt_cached) 1526 flags |= AMDGPU_PTE_SNOOPED; 1527 } 1528 1529 return flags; 1530 } 1531 1532 /** 1533 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1534 * 1535 * @ttm: The ttm_tt object to compute the flags for 1536 * @mem: The memory registry backing this ttm_tt object 1537 1538 * Figure out the flags to use for a VM PTE (Page Table Entry). 1539 */ 1540 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1541 struct ttm_resource *mem) 1542 { 1543 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1544 1545 flags |= adev->gart.gart_pte_flags; 1546 flags |= AMDGPU_PTE_READABLE; 1547 1548 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1549 flags |= AMDGPU_PTE_WRITEABLE; 1550 1551 return flags; 1552 } 1553 1554 /** 1555 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1556 * object. 1557 * 1558 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1559 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1560 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1561 * used to clean out a memory space. 1562 */ 1563 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1564 const struct ttm_place *place) 1565 { 1566 unsigned long num_pages = bo->mem.num_pages; 1567 struct drm_mm_node *node = bo->mem.mm_node; 1568 struct dma_resv_list *flist; 1569 struct dma_fence *f; 1570 int i; 1571 1572 if (bo->type == ttm_bo_type_kernel && 1573 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1574 return false; 1575 1576 /* If bo is a KFD BO, check if the bo belongs to the current process. 1577 * If true, then return false as any KFD process needs all its BOs to 1578 * be resident to run successfully 1579 */ 1580 flist = dma_resv_get_list(bo->base.resv); 1581 if (flist) { 1582 for (i = 0; i < flist->shared_count; ++i) { 1583 f = rcu_dereference_protected(flist->shared[i], 1584 dma_resv_held(bo->base.resv)); 1585 if (amdkfd_fence_check_mm(f, current->mm)) 1586 return false; 1587 } 1588 } 1589 1590 switch (bo->mem.mem_type) { 1591 case TTM_PL_TT: 1592 if (amdgpu_bo_is_amdgpu_bo(bo) && 1593 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1594 return false; 1595 return true; 1596 1597 case TTM_PL_VRAM: 1598 /* Check each drm MM node individually */ 1599 while (num_pages) { 1600 if (place->fpfn < (node->start + node->size) && 1601 !(place->lpfn && place->lpfn <= node->start)) 1602 return true; 1603 1604 num_pages -= node->size; 1605 ++node; 1606 } 1607 return false; 1608 1609 default: 1610 break; 1611 } 1612 1613 return ttm_bo_eviction_valuable(bo, place); 1614 } 1615 1616 /** 1617 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1618 * 1619 * @bo: The buffer object to read/write 1620 * @offset: Offset into buffer object 1621 * @buf: Secondary buffer to write/read from 1622 * @len: Length in bytes of access 1623 * @write: true if writing 1624 * 1625 * This is used to access VRAM that backs a buffer object via MMIO 1626 * access for debugging purposes. 1627 */ 1628 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1629 unsigned long offset, 1630 void *buf, int len, int write) 1631 { 1632 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1633 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1634 struct drm_mm_node *nodes; 1635 uint32_t value = 0; 1636 int ret = 0; 1637 uint64_t pos; 1638 unsigned long flags; 1639 1640 if (bo->mem.mem_type != TTM_PL_VRAM) 1641 return -EIO; 1642 1643 pos = offset; 1644 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); 1645 pos += (nodes->start << PAGE_SHIFT); 1646 1647 while (len && pos < adev->gmc.mc_vram_size) { 1648 uint64_t aligned_pos = pos & ~(uint64_t)3; 1649 uint64_t bytes = 4 - (pos & 3); 1650 uint32_t shift = (pos & 3) * 8; 1651 uint32_t mask = 0xffffffff << shift; 1652 1653 if (len < bytes) { 1654 mask &= 0xffffffff >> (bytes - len) * 8; 1655 bytes = len; 1656 } 1657 1658 if (mask != 0xffffffff) { 1659 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1660 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1661 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1662 if (!write || mask != 0xffffffff) 1663 value = RREG32_NO_KIQ(mmMM_DATA); 1664 if (write) { 1665 value &= ~mask; 1666 value |= (*(uint32_t *)buf << shift) & mask; 1667 WREG32_NO_KIQ(mmMM_DATA, value); 1668 } 1669 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1670 if (!write) { 1671 value = (value & mask) >> shift; 1672 memcpy(buf, &value, bytes); 1673 } 1674 } else { 1675 bytes = (nodes->start + nodes->size) << PAGE_SHIFT; 1676 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); 1677 1678 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, 1679 bytes, write); 1680 } 1681 1682 ret += bytes; 1683 buf = (uint8_t *)buf + bytes; 1684 pos += bytes; 1685 len -= bytes; 1686 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { 1687 ++nodes; 1688 pos = (nodes->start << PAGE_SHIFT); 1689 } 1690 } 1691 1692 return ret; 1693 } 1694 1695 static struct ttm_bo_driver amdgpu_bo_driver = { 1696 .ttm_tt_create = &amdgpu_ttm_tt_create, 1697 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1698 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1699 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1700 .evict_flags = &amdgpu_evict_flags, 1701 .move = &amdgpu_bo_move, 1702 .verify_access = &amdgpu_verify_access, 1703 .move_notify = &amdgpu_bo_move_notify, 1704 .release_notify = &amdgpu_bo_release_notify, 1705 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1706 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1707 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1708 .access_memory = &amdgpu_ttm_access_memory, 1709 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1710 }; 1711 1712 /* 1713 * Firmware Reservation functions 1714 */ 1715 /** 1716 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1717 * 1718 * @adev: amdgpu_device pointer 1719 * 1720 * free fw reserved vram if it has been reserved. 1721 */ 1722 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1723 { 1724 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, 1725 NULL, &adev->fw_vram_usage.va); 1726 } 1727 1728 /** 1729 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1730 * 1731 * @adev: amdgpu_device pointer 1732 * 1733 * create bo vram reservation from fw. 1734 */ 1735 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1736 { 1737 uint64_t vram_size = adev->gmc.visible_vram_size; 1738 1739 adev->fw_vram_usage.va = NULL; 1740 adev->fw_vram_usage.reserved_bo = NULL; 1741 1742 if (adev->fw_vram_usage.size == 0 || 1743 adev->fw_vram_usage.size > vram_size) 1744 return 0; 1745 1746 return amdgpu_bo_create_kernel_at(adev, 1747 adev->fw_vram_usage.start_offset, 1748 adev->fw_vram_usage.size, 1749 AMDGPU_GEM_DOMAIN_VRAM, 1750 &adev->fw_vram_usage.reserved_bo, 1751 &adev->fw_vram_usage.va); 1752 } 1753 1754 /* 1755 * Memoy training reservation functions 1756 */ 1757 1758 /** 1759 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1760 * 1761 * @adev: amdgpu_device pointer 1762 * 1763 * free memory training reserved vram if it has been reserved. 1764 */ 1765 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1766 { 1767 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1768 1769 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1770 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1771 ctx->c2p_bo = NULL; 1772 1773 return 0; 1774 } 1775 1776 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size) 1777 { 1778 if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) ) 1779 vram_size -= SZ_1M; 1780 1781 return ALIGN(vram_size, SZ_1M); 1782 } 1783 1784 /** 1785 * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training 1786 * 1787 * @adev: amdgpu_device pointer 1788 * 1789 * create bo vram reservation from memory training. 1790 */ 1791 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev) 1792 { 1793 int ret; 1794 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1795 1796 memset(ctx, 0, sizeof(*ctx)); 1797 if (!adev->fw_vram_usage.mem_train_support) { 1798 DRM_DEBUG("memory training does not support!\n"); 1799 return 0; 1800 } 1801 1802 ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size); 1803 ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1804 ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1805 1806 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1807 ctx->train_data_size, 1808 ctx->p2c_train_data_offset, 1809 ctx->c2p_train_data_offset); 1810 1811 ret = amdgpu_bo_create_kernel_at(adev, 1812 ctx->c2p_train_data_offset, 1813 ctx->train_data_size, 1814 AMDGPU_GEM_DOMAIN_VRAM, 1815 &ctx->c2p_bo, 1816 NULL); 1817 if (ret) { 1818 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1819 amdgpu_ttm_training_reserve_vram_fini(adev); 1820 return ret; 1821 } 1822 1823 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1824 return 0; 1825 } 1826 1827 /** 1828 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1829 * gtt/vram related fields. 1830 * 1831 * This initializes all of the memory space pools that the TTM layer 1832 * will need such as the GTT space (system memory mapped to the device), 1833 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1834 * can be mapped per VMID. 1835 */ 1836 int amdgpu_ttm_init(struct amdgpu_device *adev) 1837 { 1838 uint64_t gtt_size; 1839 int r; 1840 u64 vis_vram_limit; 1841 void *stolen_vga_buf; 1842 1843 mutex_init(&adev->mman.gtt_window_lock); 1844 1845 /* No others user of address space so set it to 0 */ 1846 r = ttm_bo_device_init(&adev->mman.bdev, 1847 &amdgpu_bo_driver, 1848 adev->ddev->anon_inode->i_mapping, 1849 adev->ddev->vma_offset_manager, 1850 dma_addressing_limited(adev->dev)); 1851 if (r) { 1852 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1853 return r; 1854 } 1855 adev->mman.initialized = true; 1856 1857 /* We opt to avoid OOM on system pages allocations */ 1858 adev->mman.bdev.no_retry = true; 1859 1860 /* Initialize VRAM pool with all of VRAM divided into pages */ 1861 r = amdgpu_vram_mgr_init(adev); 1862 if (r) { 1863 DRM_ERROR("Failed initializing VRAM heap.\n"); 1864 return r; 1865 } 1866 1867 /* Reduce size of CPU-visible VRAM if requested */ 1868 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1869 if (amdgpu_vis_vram_limit > 0 && 1870 vis_vram_limit <= adev->gmc.visible_vram_size) 1871 adev->gmc.visible_vram_size = vis_vram_limit; 1872 1873 /* Change the size here instead of the init above so only lpfn is affected */ 1874 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1875 #ifdef CONFIG_64BIT 1876 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1877 adev->gmc.visible_vram_size); 1878 #endif 1879 1880 /* 1881 *The reserved vram for firmware must be pinned to the specified 1882 *place on the VRAM, so reserve it early. 1883 */ 1884 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1885 if (r) { 1886 return r; 1887 } 1888 1889 /* 1890 *The reserved vram for memory training must be pinned to the specified 1891 *place on the VRAM, so reserve it early. 1892 */ 1893 if (!amdgpu_sriov_vf(adev)) { 1894 r = amdgpu_ttm_training_reserve_vram_init(adev); 1895 if (r) 1896 return r; 1897 } 1898 1899 /* allocate memory as required for VGA 1900 * This is used for VGA emulation and pre-OS scanout buffers to 1901 * avoid display artifacts while transitioning between pre-OS 1902 * and driver. */ 1903 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, 1904 AMDGPU_GEM_DOMAIN_VRAM, 1905 &adev->stolen_vga_memory, 1906 NULL, &stolen_vga_buf); 1907 if (r) 1908 return r; 1909 1910 /* 1911 * reserve TMR memory at the top of VRAM which holds 1912 * IP Discovery data and is protected by PSP. 1913 */ 1914 if (adev->discovery_tmr_size > 0) { 1915 r = amdgpu_bo_create_kernel_at(adev, 1916 adev->gmc.real_vram_size - adev->discovery_tmr_size, 1917 adev->discovery_tmr_size, 1918 AMDGPU_GEM_DOMAIN_VRAM, 1919 &adev->discovery_memory, 1920 NULL); 1921 if (r) 1922 return r; 1923 } 1924 1925 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1926 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1927 1928 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1929 * or whatever the user passed on module init */ 1930 if (amdgpu_gtt_size == -1) { 1931 struct sysinfo si; 1932 1933 si_meminfo(&si); 1934 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1935 adev->gmc.mc_vram_size), 1936 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1937 } 1938 else 1939 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1940 1941 /* Initialize GTT memory pool */ 1942 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1943 if (r) { 1944 DRM_ERROR("Failed initializing GTT heap.\n"); 1945 return r; 1946 } 1947 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1948 (unsigned)(gtt_size / (1024 * 1024))); 1949 1950 /* Initialize various on-chip memory pools */ 1951 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1952 if (r) { 1953 DRM_ERROR("Failed initializing GDS heap.\n"); 1954 return r; 1955 } 1956 1957 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1958 if (r) { 1959 DRM_ERROR("Failed initializing gws heap.\n"); 1960 return r; 1961 } 1962 1963 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1964 if (r) { 1965 DRM_ERROR("Failed initializing oa heap.\n"); 1966 return r; 1967 } 1968 1969 return 0; 1970 } 1971 1972 /** 1973 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm 1974 */ 1975 void amdgpu_ttm_late_init(struct amdgpu_device *adev) 1976 { 1977 void *stolen_vga_buf; 1978 /* return the VGA stolen memory (if any) back to VRAM */ 1979 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 1980 } 1981 1982 /** 1983 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1984 */ 1985 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1986 { 1987 if (!adev->mman.initialized) 1988 return; 1989 1990 amdgpu_ttm_training_reserve_vram_fini(adev); 1991 /* return the IP Discovery TMR memory back to VRAM */ 1992 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL); 1993 amdgpu_ttm_fw_reserve_vram_fini(adev); 1994 1995 if (adev->mman.aper_base_kaddr) 1996 iounmap(adev->mman.aper_base_kaddr); 1997 adev->mman.aper_base_kaddr = NULL; 1998 1999 amdgpu_vram_mgr_fini(adev); 2000 amdgpu_gtt_mgr_fini(adev); 2001 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 2002 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2003 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2004 ttm_bo_device_release(&adev->mman.bdev); 2005 adev->mman.initialized = false; 2006 DRM_INFO("amdgpu: ttm finalized\n"); 2007 } 2008 2009 /** 2010 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2011 * 2012 * @adev: amdgpu_device pointer 2013 * @enable: true when we can use buffer functions. 2014 * 2015 * Enable/disable use of buffer functions during suspend/resume. This should 2016 * only be called at bootup or when userspace isn't running. 2017 */ 2018 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2019 { 2020 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2021 uint64_t size; 2022 int r; 2023 2024 if (!adev->mman.initialized || adev->in_gpu_reset || 2025 adev->mman.buffer_funcs_enabled == enable) 2026 return; 2027 2028 if (enable) { 2029 struct amdgpu_ring *ring; 2030 struct drm_gpu_scheduler *sched; 2031 2032 ring = adev->mman.buffer_funcs_ring; 2033 sched = &ring->sched; 2034 r = drm_sched_entity_init(&adev->mman.entity, 2035 DRM_SCHED_PRIORITY_KERNEL, &sched, 2036 1, NULL); 2037 if (r) { 2038 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2039 r); 2040 return; 2041 } 2042 } else { 2043 drm_sched_entity_destroy(&adev->mman.entity); 2044 dma_fence_put(man->move); 2045 man->move = NULL; 2046 } 2047 2048 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2049 if (enable) 2050 size = adev->gmc.real_vram_size; 2051 else 2052 size = adev->gmc.visible_vram_size; 2053 man->size = size >> PAGE_SHIFT; 2054 adev->mman.buffer_funcs_enabled = enable; 2055 } 2056 2057 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 2058 { 2059 struct drm_file *file_priv = filp->private_data; 2060 struct amdgpu_device *adev = file_priv->minor->dev->dev_private; 2061 2062 if (adev == NULL) 2063 return -EINVAL; 2064 2065 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 2066 } 2067 2068 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2069 uint64_t dst_offset, uint32_t byte_count, 2070 struct dma_resv *resv, 2071 struct dma_fence **fence, bool direct_submit, 2072 bool vm_needs_flush, bool tmz) 2073 { 2074 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 2075 AMDGPU_IB_POOL_DELAYED; 2076 struct amdgpu_device *adev = ring->adev; 2077 struct amdgpu_job *job; 2078 2079 uint32_t max_bytes; 2080 unsigned num_loops, num_dw; 2081 unsigned i; 2082 int r; 2083 2084 if (direct_submit && !ring->sched.ready) { 2085 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2086 return -EINVAL; 2087 } 2088 2089 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2090 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2091 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2092 2093 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 2094 if (r) 2095 return r; 2096 2097 if (vm_needs_flush) { 2098 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 2099 job->vm_needs_flush = true; 2100 } 2101 if (resv) { 2102 r = amdgpu_sync_resv(adev, &job->sync, resv, 2103 AMDGPU_SYNC_ALWAYS, 2104 AMDGPU_FENCE_OWNER_UNDEFINED); 2105 if (r) { 2106 DRM_ERROR("sync failed (%d).\n", r); 2107 goto error_free; 2108 } 2109 } 2110 2111 for (i = 0; i < num_loops; i++) { 2112 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2113 2114 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2115 dst_offset, cur_size_in_bytes, tmz); 2116 2117 src_offset += cur_size_in_bytes; 2118 dst_offset += cur_size_in_bytes; 2119 byte_count -= cur_size_in_bytes; 2120 } 2121 2122 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2123 WARN_ON(job->ibs[0].length_dw > num_dw); 2124 if (direct_submit) 2125 r = amdgpu_job_submit_direct(job, ring, fence); 2126 else 2127 r = amdgpu_job_submit(job, &adev->mman.entity, 2128 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2129 if (r) 2130 goto error_free; 2131 2132 return r; 2133 2134 error_free: 2135 amdgpu_job_free(job); 2136 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2137 return r; 2138 } 2139 2140 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2141 uint32_t src_data, 2142 struct dma_resv *resv, 2143 struct dma_fence **fence) 2144 { 2145 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2146 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2147 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2148 2149 struct drm_mm_node *mm_node; 2150 unsigned long num_pages; 2151 unsigned int num_loops, num_dw; 2152 2153 struct amdgpu_job *job; 2154 int r; 2155 2156 if (!adev->mman.buffer_funcs_enabled) { 2157 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2158 return -EINVAL; 2159 } 2160 2161 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2162 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2163 if (r) 2164 return r; 2165 } 2166 2167 num_pages = bo->tbo.num_pages; 2168 mm_node = bo->tbo.mem.mm_node; 2169 num_loops = 0; 2170 while (num_pages) { 2171 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2172 2173 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); 2174 num_pages -= mm_node->size; 2175 ++mm_node; 2176 } 2177 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2178 2179 /* for IB padding */ 2180 num_dw += 64; 2181 2182 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2183 &job); 2184 if (r) 2185 return r; 2186 2187 if (resv) { 2188 r = amdgpu_sync_resv(adev, &job->sync, resv, 2189 AMDGPU_SYNC_ALWAYS, 2190 AMDGPU_FENCE_OWNER_UNDEFINED); 2191 if (r) { 2192 DRM_ERROR("sync failed (%d).\n", r); 2193 goto error_free; 2194 } 2195 } 2196 2197 num_pages = bo->tbo.num_pages; 2198 mm_node = bo->tbo.mem.mm_node; 2199 2200 while (num_pages) { 2201 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2202 uint64_t dst_addr; 2203 2204 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); 2205 while (byte_count) { 2206 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, 2207 max_bytes); 2208 2209 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 2210 dst_addr, cur_size_in_bytes); 2211 2212 dst_addr += cur_size_in_bytes; 2213 byte_count -= cur_size_in_bytes; 2214 } 2215 2216 num_pages -= mm_node->size; 2217 ++mm_node; 2218 } 2219 2220 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2221 WARN_ON(job->ibs[0].length_dw > num_dw); 2222 r = amdgpu_job_submit(job, &adev->mman.entity, 2223 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2224 if (r) 2225 goto error_free; 2226 2227 return 0; 2228 2229 error_free: 2230 amdgpu_job_free(job); 2231 return r; 2232 } 2233 2234 #if defined(CONFIG_DEBUG_FS) 2235 2236 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 2237 { 2238 struct drm_info_node *node = (struct drm_info_node *)m->private; 2239 unsigned ttm_pl = (uintptr_t)node->info_ent->data; 2240 struct drm_device *dev = node->minor->dev; 2241 struct amdgpu_device *adev = dev->dev_private; 2242 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); 2243 struct drm_printer p = drm_seq_file_printer(m); 2244 2245 man->func->debug(man, &p); 2246 return 0; 2247 } 2248 2249 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 2250 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, 2251 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, 2252 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, 2253 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, 2254 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, 2255 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 2256 #ifdef CONFIG_SWIOTLB 2257 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 2258 #endif 2259 }; 2260 2261 /** 2262 * amdgpu_ttm_vram_read - Linear read access to VRAM 2263 * 2264 * Accesses VRAM via MMIO for debugging purposes. 2265 */ 2266 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2267 size_t size, loff_t *pos) 2268 { 2269 struct amdgpu_device *adev = file_inode(f)->i_private; 2270 ssize_t result = 0; 2271 2272 if (size & 0x3 || *pos & 0x3) 2273 return -EINVAL; 2274 2275 if (*pos >= adev->gmc.mc_vram_size) 2276 return -ENXIO; 2277 2278 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2279 while (size) { 2280 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2281 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2282 2283 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2284 if (copy_to_user(buf, value, bytes)) 2285 return -EFAULT; 2286 2287 result += bytes; 2288 buf += bytes; 2289 *pos += bytes; 2290 size -= bytes; 2291 } 2292 2293 return result; 2294 } 2295 2296 /** 2297 * amdgpu_ttm_vram_write - Linear write access to VRAM 2298 * 2299 * Accesses VRAM via MMIO for debugging purposes. 2300 */ 2301 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2302 size_t size, loff_t *pos) 2303 { 2304 struct amdgpu_device *adev = file_inode(f)->i_private; 2305 ssize_t result = 0; 2306 int r; 2307 2308 if (size & 0x3 || *pos & 0x3) 2309 return -EINVAL; 2310 2311 if (*pos >= adev->gmc.mc_vram_size) 2312 return -ENXIO; 2313 2314 while (size) { 2315 unsigned long flags; 2316 uint32_t value; 2317 2318 if (*pos >= adev->gmc.mc_vram_size) 2319 return result; 2320 2321 r = get_user(value, (uint32_t *)buf); 2322 if (r) 2323 return r; 2324 2325 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2326 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2327 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2328 WREG32_NO_KIQ(mmMM_DATA, value); 2329 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2330 2331 result += 4; 2332 buf += 4; 2333 *pos += 4; 2334 size -= 4; 2335 } 2336 2337 return result; 2338 } 2339 2340 static const struct file_operations amdgpu_ttm_vram_fops = { 2341 .owner = THIS_MODULE, 2342 .read = amdgpu_ttm_vram_read, 2343 .write = amdgpu_ttm_vram_write, 2344 .llseek = default_llseek, 2345 }; 2346 2347 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2348 2349 /** 2350 * amdgpu_ttm_gtt_read - Linear read access to GTT memory 2351 */ 2352 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 2353 size_t size, loff_t *pos) 2354 { 2355 struct amdgpu_device *adev = file_inode(f)->i_private; 2356 ssize_t result = 0; 2357 int r; 2358 2359 while (size) { 2360 loff_t p = *pos / PAGE_SIZE; 2361 unsigned off = *pos & ~PAGE_MASK; 2362 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 2363 struct page *page; 2364 void *ptr; 2365 2366 if (p >= adev->gart.num_cpu_pages) 2367 return result; 2368 2369 page = adev->gart.pages[p]; 2370 if (page) { 2371 ptr = kmap(page); 2372 ptr += off; 2373 2374 r = copy_to_user(buf, ptr, cur_size); 2375 kunmap(adev->gart.pages[p]); 2376 } else 2377 r = clear_user(buf, cur_size); 2378 2379 if (r) 2380 return -EFAULT; 2381 2382 result += cur_size; 2383 buf += cur_size; 2384 *pos += cur_size; 2385 size -= cur_size; 2386 } 2387 2388 return result; 2389 } 2390 2391 static const struct file_operations amdgpu_ttm_gtt_fops = { 2392 .owner = THIS_MODULE, 2393 .read = amdgpu_ttm_gtt_read, 2394 .llseek = default_llseek 2395 }; 2396 2397 #endif 2398 2399 /** 2400 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2401 * 2402 * This function is used to read memory that has been mapped to the 2403 * GPU and the known addresses are not physical addresses but instead 2404 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2405 */ 2406 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2407 size_t size, loff_t *pos) 2408 { 2409 struct amdgpu_device *adev = file_inode(f)->i_private; 2410 struct iommu_domain *dom; 2411 ssize_t result = 0; 2412 int r; 2413 2414 /* retrieve the IOMMU domain if any for this device */ 2415 dom = iommu_get_domain_for_dev(adev->dev); 2416 2417 while (size) { 2418 phys_addr_t addr = *pos & PAGE_MASK; 2419 loff_t off = *pos & ~PAGE_MASK; 2420 size_t bytes = PAGE_SIZE - off; 2421 unsigned long pfn; 2422 struct page *p; 2423 void *ptr; 2424 2425 bytes = bytes < size ? bytes : size; 2426 2427 /* Translate the bus address to a physical address. If 2428 * the domain is NULL it means there is no IOMMU active 2429 * and the address translation is the identity 2430 */ 2431 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2432 2433 pfn = addr >> PAGE_SHIFT; 2434 if (!pfn_valid(pfn)) 2435 return -EPERM; 2436 2437 p = pfn_to_page(pfn); 2438 if (p->mapping != adev->mman.bdev.dev_mapping) 2439 return -EPERM; 2440 2441 ptr = kmap(p); 2442 r = copy_to_user(buf, ptr + off, bytes); 2443 kunmap(p); 2444 if (r) 2445 return -EFAULT; 2446 2447 size -= bytes; 2448 *pos += bytes; 2449 result += bytes; 2450 } 2451 2452 return result; 2453 } 2454 2455 /** 2456 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2457 * 2458 * This function is used to write memory that has been mapped to the 2459 * GPU and the known addresses are not physical addresses but instead 2460 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2461 */ 2462 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2463 size_t size, loff_t *pos) 2464 { 2465 struct amdgpu_device *adev = file_inode(f)->i_private; 2466 struct iommu_domain *dom; 2467 ssize_t result = 0; 2468 int r; 2469 2470 dom = iommu_get_domain_for_dev(adev->dev); 2471 2472 while (size) { 2473 phys_addr_t addr = *pos & PAGE_MASK; 2474 loff_t off = *pos & ~PAGE_MASK; 2475 size_t bytes = PAGE_SIZE - off; 2476 unsigned long pfn; 2477 struct page *p; 2478 void *ptr; 2479 2480 bytes = bytes < size ? bytes : size; 2481 2482 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2483 2484 pfn = addr >> PAGE_SHIFT; 2485 if (!pfn_valid(pfn)) 2486 return -EPERM; 2487 2488 p = pfn_to_page(pfn); 2489 if (p->mapping != adev->mman.bdev.dev_mapping) 2490 return -EPERM; 2491 2492 ptr = kmap(p); 2493 r = copy_from_user(ptr + off, buf, bytes); 2494 kunmap(p); 2495 if (r) 2496 return -EFAULT; 2497 2498 size -= bytes; 2499 *pos += bytes; 2500 result += bytes; 2501 } 2502 2503 return result; 2504 } 2505 2506 static const struct file_operations amdgpu_ttm_iomem_fops = { 2507 .owner = THIS_MODULE, 2508 .read = amdgpu_iomem_read, 2509 .write = amdgpu_iomem_write, 2510 .llseek = default_llseek 2511 }; 2512 2513 static const struct { 2514 char *name; 2515 const struct file_operations *fops; 2516 int domain; 2517 } ttm_debugfs_entries[] = { 2518 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, 2519 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2520 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, 2521 #endif 2522 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, 2523 }; 2524 2525 #endif 2526 2527 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2528 { 2529 #if defined(CONFIG_DEBUG_FS) 2530 unsigned count; 2531 2532 struct drm_minor *minor = adev->ddev->primary; 2533 struct dentry *ent, *root = minor->debugfs_root; 2534 2535 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { 2536 ent = debugfs_create_file( 2537 ttm_debugfs_entries[count].name, 2538 S_IFREG | S_IRUGO, root, 2539 adev, 2540 ttm_debugfs_entries[count].fops); 2541 if (IS_ERR(ent)) 2542 return PTR_ERR(ent); 2543 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) 2544 i_size_write(ent->d_inode, adev->gmc.mc_vram_size); 2545 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) 2546 i_size_write(ent->d_inode, adev->gmc.gart_size); 2547 adev->mman.debugfs_entries[count] = ent; 2548 } 2549 2550 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 2551 2552 #ifdef CONFIG_SWIOTLB 2553 if (!(adev->need_swiotlb && swiotlb_nr_tbl())) 2554 --count; 2555 #endif 2556 2557 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 2558 #else 2559 return 0; 2560 #endif 2561 } 2562