1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 52 #include <drm/drm_debugfs.h> 53 #include <drm/amdgpu_drm.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "bif/bif_4_1_d.h" 62 63 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 64 65 66 /** 67 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of 68 * memory request. 69 * 70 * @bdev: The TTM BO device object (contains a reference to amdgpu_device) 71 * @type: The type of memory requested 72 * @man: The memory type manager for each domain 73 * 74 * This is called by ttm_bo_init_mm() when a buffer object is being 75 * initialized. 76 */ 77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 78 struct ttm_mem_type_manager *man) 79 { 80 struct amdgpu_device *adev; 81 82 adev = amdgpu_ttm_adev(bdev); 83 84 switch (type) { 85 case TTM_PL_SYSTEM: 86 /* System memory */ 87 man->flags = 0; 88 man->available_caching = TTM_PL_MASK_CACHING; 89 man->default_caching = TTM_PL_FLAG_CACHED; 90 break; 91 case TTM_PL_TT: 92 /* GTT memory */ 93 man->func = &amdgpu_gtt_mgr_func; 94 man->available_caching = TTM_PL_MASK_CACHING; 95 man->default_caching = TTM_PL_FLAG_CACHED; 96 man->flags = 0; 97 break; 98 case TTM_PL_VRAM: 99 /* "On-card" video ram */ 100 man->func = &amdgpu_vram_mgr_func; 101 man->flags = TTM_MEMTYPE_FLAG_FIXED; 102 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 103 man->default_caching = TTM_PL_FLAG_WC; 104 break; 105 case AMDGPU_PL_GDS: 106 case AMDGPU_PL_GWS: 107 case AMDGPU_PL_OA: 108 /* On-chip GDS memory*/ 109 man->func = &ttm_bo_manager_func; 110 man->flags = TTM_MEMTYPE_FLAG_FIXED; 111 man->available_caching = TTM_PL_FLAG_UNCACHED; 112 man->default_caching = TTM_PL_FLAG_UNCACHED; 113 break; 114 default: 115 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 116 return -EINVAL; 117 } 118 return 0; 119 } 120 121 /** 122 * amdgpu_evict_flags - Compute placement flags 123 * 124 * @bo: The buffer object to evict 125 * @placement: Possible destination(s) for evicted BO 126 * 127 * Fill in placement data when ttm_bo_evict() is called 128 */ 129 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 130 struct ttm_placement *placement) 131 { 132 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 133 struct amdgpu_bo *abo; 134 static const struct ttm_place placements = { 135 .fpfn = 0, 136 .lpfn = 0, 137 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 138 }; 139 140 /* Don't handle scatter gather BOs */ 141 if (bo->type == ttm_bo_type_sg) { 142 placement->num_placement = 0; 143 placement->num_busy_placement = 0; 144 return; 145 } 146 147 /* Object isn't an AMDGPU object so ignore */ 148 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 149 placement->placement = &placements; 150 placement->busy_placement = &placements; 151 placement->num_placement = 1; 152 placement->num_busy_placement = 1; 153 return; 154 } 155 156 abo = ttm_to_amdgpu_bo(bo); 157 switch (bo->mem.mem_type) { 158 case AMDGPU_PL_GDS: 159 case AMDGPU_PL_GWS: 160 case AMDGPU_PL_OA: 161 placement->num_placement = 0; 162 placement->num_busy_placement = 0; 163 return; 164 165 case TTM_PL_VRAM: 166 if (!adev->mman.buffer_funcs_enabled) { 167 /* Move to system memory */ 168 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 169 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 170 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 171 amdgpu_bo_in_cpu_visible_vram(abo)) { 172 173 /* Try evicting to the CPU inaccessible part of VRAM 174 * first, but only set GTT as busy placement, so this 175 * BO will be evicted to GTT rather than causing other 176 * BOs to be evicted from VRAM 177 */ 178 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 179 AMDGPU_GEM_DOMAIN_GTT); 180 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 181 abo->placements[0].lpfn = 0; 182 abo->placement.busy_placement = &abo->placements[1]; 183 abo->placement.num_busy_placement = 1; 184 } else { 185 /* Move to GTT memory */ 186 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 187 } 188 break; 189 case TTM_PL_TT: 190 default: 191 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 192 break; 193 } 194 *placement = abo->placement; 195 } 196 197 /** 198 * amdgpu_verify_access - Verify access for a mmap call 199 * 200 * @bo: The buffer object to map 201 * @filp: The file pointer from the process performing the mmap 202 * 203 * This is called by ttm_bo_mmap() to verify whether a process 204 * has the right to mmap a BO to their process space. 205 */ 206 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 207 { 208 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 209 210 /* 211 * Don't verify access for KFD BOs. They don't have a GEM 212 * object associated with them. 213 */ 214 if (abo->kfd_bo) 215 return 0; 216 217 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 218 return -EPERM; 219 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 220 filp->private_data); 221 } 222 223 /** 224 * amdgpu_move_null - Register memory for a buffer object 225 * 226 * @bo: The bo to assign the memory to 227 * @new_mem: The memory to be assigned. 228 * 229 * Assign the memory from new_mem to the memory of the buffer object bo. 230 */ 231 static void amdgpu_move_null(struct ttm_buffer_object *bo, 232 struct ttm_mem_reg *new_mem) 233 { 234 struct ttm_mem_reg *old_mem = &bo->mem; 235 236 BUG_ON(old_mem->mm_node != NULL); 237 *old_mem = *new_mem; 238 new_mem->mm_node = NULL; 239 } 240 241 /** 242 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. 243 * 244 * @bo: The bo to assign the memory to. 245 * @mm_node: Memory manager node for drm allocator. 246 * @mem: The region where the bo resides. 247 * 248 */ 249 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 250 struct drm_mm_node *mm_node, 251 struct ttm_mem_reg *mem) 252 { 253 uint64_t addr = 0; 254 255 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { 256 addr = mm_node->start << PAGE_SHIFT; 257 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev), 258 mem->mem_type); 259 } 260 return addr; 261 } 262 263 /** 264 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to 265 * @offset. It also modifies the offset to be within the drm_mm_node returned 266 * 267 * @mem: The region where the bo resides. 268 * @offset: The offset that drm_mm_node is used for finding. 269 * 270 */ 271 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem, 272 uint64_t *offset) 273 { 274 struct drm_mm_node *mm_node = mem->mm_node; 275 276 while (*offset >= (mm_node->size << PAGE_SHIFT)) { 277 *offset -= (mm_node->size << PAGE_SHIFT); 278 ++mm_node; 279 } 280 return mm_node; 281 } 282 283 /** 284 * amdgpu_ttm_map_buffer - Map memory into the GART windows 285 * @bo: buffer object to map 286 * @mem: memory object to map 287 * @mm_node: drm_mm node object to map 288 * @num_pages: number of pages to map 289 * @offset: offset into @mm_node where to start 290 * @window: which GART window to use 291 * @ring: DMA ring to use for the copy 292 * @tmz: if we should setup a TMZ enabled mapping 293 * @addr: resulting address inside the MC address space 294 * 295 * Setup one of the GART windows to access a specific piece of memory or return 296 * the physical address for local memory. 297 */ 298 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 299 struct ttm_mem_reg *mem, 300 struct drm_mm_node *mm_node, 301 unsigned num_pages, uint64_t offset, 302 unsigned window, struct amdgpu_ring *ring, 303 bool tmz, uint64_t *addr) 304 { 305 struct amdgpu_device *adev = ring->adev; 306 struct amdgpu_job *job; 307 unsigned num_dw, num_bytes; 308 struct dma_fence *fence; 309 uint64_t src_addr, dst_addr; 310 void *cpu_addr; 311 uint64_t flags; 312 unsigned int i; 313 int r; 314 315 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 316 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 317 318 /* Map only what can't be accessed directly */ 319 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 320 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; 321 return 0; 322 } 323 324 *addr = adev->gmc.gart_start; 325 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 326 AMDGPU_GPU_PAGE_SIZE; 327 *addr += offset & ~PAGE_MASK; 328 329 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 330 num_bytes = num_pages * 8; 331 332 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 333 AMDGPU_IB_POOL_DELAYED, &job); 334 if (r) 335 return r; 336 337 src_addr = num_dw * 4; 338 src_addr += job->ibs[0].gpu_addr; 339 340 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 341 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 342 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 343 dst_addr, num_bytes, false); 344 345 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 346 WARN_ON(job->ibs[0].length_dw > num_dw); 347 348 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 349 if (tmz) 350 flags |= AMDGPU_PTE_TMZ; 351 352 cpu_addr = &job->ibs[0].ptr[num_dw]; 353 354 if (mem->mem_type == TTM_PL_TT) { 355 struct ttm_dma_tt *dma; 356 dma_addr_t *dma_address; 357 358 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm); 359 dma_address = &dma->dma_address[offset >> PAGE_SHIFT]; 360 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, 361 cpu_addr); 362 if (r) 363 goto error_free; 364 } else { 365 dma_addr_t dma_address; 366 367 dma_address = (mm_node->start << PAGE_SHIFT) + offset; 368 dma_address += adev->vm_manager.vram_base_offset; 369 370 for (i = 0; i < num_pages; ++i) { 371 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 372 &dma_address, flags, cpu_addr); 373 if (r) 374 goto error_free; 375 376 dma_address += PAGE_SIZE; 377 } 378 } 379 380 r = amdgpu_job_submit(job, &adev->mman.entity, 381 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 382 if (r) 383 goto error_free; 384 385 dma_fence_put(fence); 386 387 return r; 388 389 error_free: 390 amdgpu_job_free(job); 391 return r; 392 } 393 394 /** 395 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 396 * @adev: amdgpu device 397 * @src: buffer/address where to read from 398 * @dst: buffer/address where to write to 399 * @size: number of bytes to copy 400 * @tmz: if a secure copy should be used 401 * @resv: resv object to sync to 402 * @f: Returns the last fence if multiple jobs are submitted. 403 * 404 * The function copies @size bytes from {src->mem + src->offset} to 405 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 406 * move and different for a BO to BO copy. 407 * 408 */ 409 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 410 const struct amdgpu_copy_mem *src, 411 const struct amdgpu_copy_mem *dst, 412 uint64_t size, bool tmz, 413 struct dma_resv *resv, 414 struct dma_fence **f) 415 { 416 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 417 AMDGPU_GPU_PAGE_SIZE); 418 419 uint64_t src_node_size, dst_node_size, src_offset, dst_offset; 420 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 421 struct drm_mm_node *src_mm, *dst_mm; 422 struct dma_fence *fence = NULL; 423 int r = 0; 424 425 if (!adev->mman.buffer_funcs_enabled) { 426 DRM_ERROR("Trying to move memory with ring turned off.\n"); 427 return -EINVAL; 428 } 429 430 src_offset = src->offset; 431 if (src->mem->mm_node) { 432 src_mm = amdgpu_find_mm_node(src->mem, &src_offset); 433 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; 434 } else { 435 src_mm = NULL; 436 src_node_size = ULLONG_MAX; 437 } 438 439 dst_offset = dst->offset; 440 if (dst->mem->mm_node) { 441 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); 442 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; 443 } else { 444 dst_mm = NULL; 445 dst_node_size = ULLONG_MAX; 446 } 447 448 mutex_lock(&adev->mman.gtt_window_lock); 449 450 while (size) { 451 uint32_t src_page_offset = src_offset & ~PAGE_MASK; 452 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; 453 struct dma_fence *next; 454 uint32_t cur_size; 455 uint64_t from, to; 456 457 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 458 * begins at an offset, then adjust the size accordingly 459 */ 460 cur_size = max(src_page_offset, dst_page_offset); 461 cur_size = min(min3(src_node_size, dst_node_size, size), 462 (uint64_t)(GTT_MAX_BYTES - cur_size)); 463 464 /* Map src to window 0 and dst to window 1. */ 465 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, 466 PFN_UP(cur_size + src_page_offset), 467 src_offset, 0, ring, tmz, &from); 468 if (r) 469 goto error; 470 471 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, 472 PFN_UP(cur_size + dst_page_offset), 473 dst_offset, 1, ring, tmz, &to); 474 if (r) 475 goto error; 476 477 r = amdgpu_copy_buffer(ring, from, to, cur_size, 478 resv, &next, false, true, tmz); 479 if (r) 480 goto error; 481 482 dma_fence_put(fence); 483 fence = next; 484 485 size -= cur_size; 486 if (!size) 487 break; 488 489 src_node_size -= cur_size; 490 if (!src_node_size) { 491 ++src_mm; 492 src_node_size = src_mm->size << PAGE_SHIFT; 493 src_offset = 0; 494 } else { 495 src_offset += cur_size; 496 } 497 498 dst_node_size -= cur_size; 499 if (!dst_node_size) { 500 ++dst_mm; 501 dst_node_size = dst_mm->size << PAGE_SHIFT; 502 dst_offset = 0; 503 } else { 504 dst_offset += cur_size; 505 } 506 } 507 error: 508 mutex_unlock(&adev->mman.gtt_window_lock); 509 if (f) 510 *f = dma_fence_get(fence); 511 dma_fence_put(fence); 512 return r; 513 } 514 515 /** 516 * amdgpu_move_blit - Copy an entire buffer to another buffer 517 * 518 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 519 * help move buffers to and from VRAM. 520 */ 521 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 522 bool evict, bool no_wait_gpu, 523 struct ttm_mem_reg *new_mem, 524 struct ttm_mem_reg *old_mem) 525 { 526 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 527 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 528 struct amdgpu_copy_mem src, dst; 529 struct dma_fence *fence = NULL; 530 int r; 531 532 src.bo = bo; 533 dst.bo = bo; 534 src.mem = old_mem; 535 dst.mem = new_mem; 536 src.offset = 0; 537 dst.offset = 0; 538 539 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 540 new_mem->num_pages << PAGE_SHIFT, 541 amdgpu_bo_encrypted(abo), 542 bo->base.resv, &fence); 543 if (r) 544 goto error; 545 546 /* clear the space being freed */ 547 if (old_mem->mem_type == TTM_PL_VRAM && 548 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 549 struct dma_fence *wipe_fence = NULL; 550 551 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 552 NULL, &wipe_fence); 553 if (r) { 554 goto error; 555 } else if (wipe_fence) { 556 dma_fence_put(fence); 557 fence = wipe_fence; 558 } 559 } 560 561 /* Always block for VM page tables before committing the new location */ 562 if (bo->type == ttm_bo_type_kernel) 563 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem); 564 else 565 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 566 dma_fence_put(fence); 567 return r; 568 569 error: 570 if (fence) 571 dma_fence_wait(fence, false); 572 dma_fence_put(fence); 573 return r; 574 } 575 576 /** 577 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer 578 * 579 * Called by amdgpu_bo_move(). 580 */ 581 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 582 struct ttm_operation_ctx *ctx, 583 struct ttm_mem_reg *new_mem) 584 { 585 struct ttm_mem_reg *old_mem = &bo->mem; 586 struct ttm_mem_reg tmp_mem; 587 struct ttm_place placements; 588 struct ttm_placement placement; 589 int r; 590 591 /* create space/pages for new_mem in GTT space */ 592 tmp_mem = *new_mem; 593 tmp_mem.mm_node = NULL; 594 placement.num_placement = 1; 595 placement.placement = &placements; 596 placement.num_busy_placement = 1; 597 placement.busy_placement = &placements; 598 placements.fpfn = 0; 599 placements.lpfn = 0; 600 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 601 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 602 if (unlikely(r)) { 603 pr_err("Failed to find GTT space for blit from VRAM\n"); 604 return r; 605 } 606 607 /* set caching flags */ 608 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 609 if (unlikely(r)) { 610 goto out_cleanup; 611 } 612 613 /* Bind the memory to the GTT space */ 614 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx); 615 if (unlikely(r)) { 616 goto out_cleanup; 617 } 618 619 /* blit VRAM to GTT */ 620 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem); 621 if (unlikely(r)) { 622 goto out_cleanup; 623 } 624 625 /* move BO (in tmp_mem) to new_mem */ 626 r = ttm_bo_move_ttm(bo, ctx, new_mem); 627 out_cleanup: 628 ttm_bo_mem_put(bo, &tmp_mem); 629 return r; 630 } 631 632 /** 633 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM 634 * 635 * Called by amdgpu_bo_move(). 636 */ 637 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 638 struct ttm_operation_ctx *ctx, 639 struct ttm_mem_reg *new_mem) 640 { 641 struct ttm_mem_reg *old_mem = &bo->mem; 642 struct ttm_mem_reg tmp_mem; 643 struct ttm_placement placement; 644 struct ttm_place placements; 645 int r; 646 647 /* make space in GTT for old_mem buffer */ 648 tmp_mem = *new_mem; 649 tmp_mem.mm_node = NULL; 650 placement.num_placement = 1; 651 placement.placement = &placements; 652 placement.num_busy_placement = 1; 653 placement.busy_placement = &placements; 654 placements.fpfn = 0; 655 placements.lpfn = 0; 656 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 657 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 658 if (unlikely(r)) { 659 pr_err("Failed to find GTT space for blit to VRAM\n"); 660 return r; 661 } 662 663 /* move/bind old memory to GTT space */ 664 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); 665 if (unlikely(r)) { 666 goto out_cleanup; 667 } 668 669 /* copy to VRAM */ 670 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem); 671 if (unlikely(r)) { 672 goto out_cleanup; 673 } 674 out_cleanup: 675 ttm_bo_mem_put(bo, &tmp_mem); 676 return r; 677 } 678 679 /** 680 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 681 * 682 * Called by amdgpu_bo_move() 683 */ 684 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 685 struct ttm_mem_reg *mem) 686 { 687 struct drm_mm_node *nodes = mem->mm_node; 688 689 if (mem->mem_type == TTM_PL_SYSTEM || 690 mem->mem_type == TTM_PL_TT) 691 return true; 692 if (mem->mem_type != TTM_PL_VRAM) 693 return false; 694 695 /* ttm_mem_reg_ioremap only supports contiguous memory */ 696 if (nodes->size != mem->num_pages) 697 return false; 698 699 return ((nodes->start + nodes->size) << PAGE_SHIFT) 700 <= adev->gmc.visible_vram_size; 701 } 702 703 /** 704 * amdgpu_bo_move - Move a buffer object to a new memory location 705 * 706 * Called by ttm_bo_handle_move_mem() 707 */ 708 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 709 struct ttm_operation_ctx *ctx, 710 struct ttm_mem_reg *new_mem) 711 { 712 struct amdgpu_device *adev; 713 struct amdgpu_bo *abo; 714 struct ttm_mem_reg *old_mem = &bo->mem; 715 int r; 716 717 /* Can't move a pinned BO */ 718 abo = ttm_to_amdgpu_bo(bo); 719 if (WARN_ON_ONCE(abo->pin_count > 0)) 720 return -EINVAL; 721 722 adev = amdgpu_ttm_adev(bo->bdev); 723 724 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 725 amdgpu_move_null(bo, new_mem); 726 return 0; 727 } 728 if ((old_mem->mem_type == TTM_PL_TT && 729 new_mem->mem_type == TTM_PL_SYSTEM) || 730 (old_mem->mem_type == TTM_PL_SYSTEM && 731 new_mem->mem_type == TTM_PL_TT)) { 732 /* bind is enough */ 733 amdgpu_move_null(bo, new_mem); 734 return 0; 735 } 736 if (old_mem->mem_type == AMDGPU_PL_GDS || 737 old_mem->mem_type == AMDGPU_PL_GWS || 738 old_mem->mem_type == AMDGPU_PL_OA || 739 new_mem->mem_type == AMDGPU_PL_GDS || 740 new_mem->mem_type == AMDGPU_PL_GWS || 741 new_mem->mem_type == AMDGPU_PL_OA) { 742 /* Nothing to save here */ 743 amdgpu_move_null(bo, new_mem); 744 return 0; 745 } 746 747 if (!adev->mman.buffer_funcs_enabled) { 748 r = -ENODEV; 749 goto memcpy; 750 } 751 752 if (old_mem->mem_type == TTM_PL_VRAM && 753 new_mem->mem_type == TTM_PL_SYSTEM) { 754 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); 755 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 756 new_mem->mem_type == TTM_PL_VRAM) { 757 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); 758 } else { 759 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, 760 new_mem, old_mem); 761 } 762 763 if (r) { 764 memcpy: 765 /* Check that all memory is CPU accessible */ 766 if (!amdgpu_mem_visible(adev, old_mem) || 767 !amdgpu_mem_visible(adev, new_mem)) { 768 pr_err("Move buffer fallback to memcpy unavailable\n"); 769 return r; 770 } 771 772 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 773 if (r) 774 return r; 775 } 776 777 if (bo->type == ttm_bo_type_device && 778 new_mem->mem_type == TTM_PL_VRAM && 779 old_mem->mem_type != TTM_PL_VRAM) { 780 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 781 * accesses the BO after it's moved. 782 */ 783 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 784 } 785 786 /* update statistics */ 787 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 788 return 0; 789 } 790 791 /** 792 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 793 * 794 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 795 */ 796 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 797 { 798 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 799 struct drm_mm_node *mm_node = mem->mm_node; 800 801 mem->bus.addr = NULL; 802 mem->bus.offset = 0; 803 mem->bus.size = mem->num_pages << PAGE_SHIFT; 804 mem->bus.base = 0; 805 mem->bus.is_iomem = false; 806 807 switch (mem->mem_type) { 808 case TTM_PL_SYSTEM: 809 /* system memory */ 810 return 0; 811 case TTM_PL_TT: 812 break; 813 case TTM_PL_VRAM: 814 mem->bus.offset = mem->start << PAGE_SHIFT; 815 /* check if it's visible */ 816 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size) 817 return -EINVAL; 818 /* Only physically contiguous buffers apply. In a contiguous 819 * buffer, size of the first mm_node would match the number of 820 * pages in ttm_mem_reg. 821 */ 822 if (adev->mman.aper_base_kaddr && 823 (mm_node->size == mem->num_pages)) 824 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 825 mem->bus.offset; 826 827 mem->bus.base = adev->gmc.aper_base; 828 mem->bus.is_iomem = true; 829 break; 830 default: 831 return -EINVAL; 832 } 833 return 0; 834 } 835 836 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 837 unsigned long page_offset) 838 { 839 uint64_t offset = (page_offset << PAGE_SHIFT); 840 struct drm_mm_node *mm; 841 842 mm = amdgpu_find_mm_node(&bo->mem, &offset); 843 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + 844 (offset >> PAGE_SHIFT); 845 } 846 847 /** 848 * amdgpu_ttm_domain_start - Returns GPU start address 849 * @adev: amdgpu device object 850 * @type: type of the memory 851 * 852 * Returns: 853 * GPU start address of a memory domain 854 */ 855 856 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 857 { 858 switch (type) { 859 case TTM_PL_TT: 860 return adev->gmc.gart_start; 861 case TTM_PL_VRAM: 862 return adev->gmc.vram_start; 863 } 864 865 return 0; 866 } 867 868 /* 869 * TTM backend functions. 870 */ 871 struct amdgpu_ttm_tt { 872 struct ttm_dma_tt ttm; 873 struct drm_gem_object *gobj; 874 u64 offset; 875 uint64_t userptr; 876 struct task_struct *usertask; 877 uint32_t userflags; 878 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 879 struct hmm_range *range; 880 #endif 881 }; 882 883 #ifdef CONFIG_DRM_AMDGPU_USERPTR 884 /** 885 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 886 * memory and start HMM tracking CPU page table update 887 * 888 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 889 * once afterwards to stop HMM tracking 890 */ 891 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 892 { 893 struct ttm_tt *ttm = bo->tbo.ttm; 894 struct amdgpu_ttm_tt *gtt = (void *)ttm; 895 unsigned long start = gtt->userptr; 896 struct vm_area_struct *vma; 897 struct hmm_range *range; 898 unsigned long timeout; 899 struct mm_struct *mm; 900 unsigned long i; 901 int r = 0; 902 903 mm = bo->notifier.mm; 904 if (unlikely(!mm)) { 905 DRM_DEBUG_DRIVER("BO is not registered?\n"); 906 return -EFAULT; 907 } 908 909 /* Another get_user_pages is running at the same time?? */ 910 if (WARN_ON(gtt->range)) 911 return -EFAULT; 912 913 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 914 return -ESRCH; 915 916 range = kzalloc(sizeof(*range), GFP_KERNEL); 917 if (unlikely(!range)) { 918 r = -ENOMEM; 919 goto out; 920 } 921 range->notifier = &bo->notifier; 922 range->start = bo->notifier.interval_tree.start; 923 range->end = bo->notifier.interval_tree.last + 1; 924 range->default_flags = HMM_PFN_REQ_FAULT; 925 if (!amdgpu_ttm_tt_is_readonly(ttm)) 926 range->default_flags |= HMM_PFN_REQ_WRITE; 927 928 range->hmm_pfns = kvmalloc_array(ttm->num_pages, 929 sizeof(*range->hmm_pfns), GFP_KERNEL); 930 if (unlikely(!range->hmm_pfns)) { 931 r = -ENOMEM; 932 goto out_free_ranges; 933 } 934 935 mmap_read_lock(mm); 936 vma = find_vma(mm, start); 937 if (unlikely(!vma || start < vma->vm_start)) { 938 r = -EFAULT; 939 goto out_unlock; 940 } 941 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 942 vma->vm_file)) { 943 r = -EPERM; 944 goto out_unlock; 945 } 946 mmap_read_unlock(mm); 947 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 948 949 retry: 950 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 951 952 mmap_read_lock(mm); 953 r = hmm_range_fault(range); 954 mmap_read_unlock(mm); 955 if (unlikely(r)) { 956 /* 957 * FIXME: This timeout should encompass the retry from 958 * mmu_interval_read_retry() as well. 959 */ 960 if (r == -EBUSY && !time_after(jiffies, timeout)) 961 goto retry; 962 goto out_free_pfns; 963 } 964 965 /* 966 * Due to default_flags, all pages are HMM_PFN_VALID or 967 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside 968 * the notifier_lock, and mmu_interval_read_retry() must be done first. 969 */ 970 for (i = 0; i < ttm->num_pages; i++) 971 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); 972 973 gtt->range = range; 974 mmput(mm); 975 976 return 0; 977 978 out_unlock: 979 mmap_read_unlock(mm); 980 out_free_pfns: 981 kvfree(range->hmm_pfns); 982 out_free_ranges: 983 kfree(range); 984 out: 985 mmput(mm); 986 return r; 987 } 988 989 /** 990 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 991 * Check if the pages backing this ttm range have been invalidated 992 * 993 * Returns: true if pages are still valid 994 */ 995 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 996 { 997 struct amdgpu_ttm_tt *gtt = (void *)ttm; 998 bool r = false; 999 1000 if (!gtt || !gtt->userptr) 1001 return false; 1002 1003 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n", 1004 gtt->userptr, ttm->num_pages); 1005 1006 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 1007 "No user pages to check\n"); 1008 1009 if (gtt->range) { 1010 /* 1011 * FIXME: Must always hold notifier_lock for this, and must 1012 * not ignore the return code. 1013 */ 1014 r = mmu_interval_read_retry(gtt->range->notifier, 1015 gtt->range->notifier_seq); 1016 kvfree(gtt->range->hmm_pfns); 1017 kfree(gtt->range); 1018 gtt->range = NULL; 1019 } 1020 1021 return !r; 1022 } 1023 #endif 1024 1025 /** 1026 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 1027 * 1028 * Called by amdgpu_cs_list_validate(). This creates the page list 1029 * that backs user memory and will ultimately be mapped into the device 1030 * address space. 1031 */ 1032 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 1033 { 1034 unsigned long i; 1035 1036 for (i = 0; i < ttm->num_pages; ++i) 1037 ttm->pages[i] = pages ? pages[i] : NULL; 1038 } 1039 1040 /** 1041 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 1042 * 1043 * Called by amdgpu_ttm_backend_bind() 1044 **/ 1045 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 1046 { 1047 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1048 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1049 int r; 1050 1051 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1052 enum dma_data_direction direction = write ? 1053 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1054 1055 /* Allocate an SG array and squash pages into it */ 1056 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 1057 ttm->num_pages << PAGE_SHIFT, 1058 GFP_KERNEL); 1059 if (r) 1060 goto release_sg; 1061 1062 /* Map SG to device */ 1063 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 1064 if (r) 1065 goto release_sg; 1066 1067 /* convert SG to linear array of pages and dma addresses */ 1068 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1069 gtt->ttm.dma_address, ttm->num_pages); 1070 1071 return 0; 1072 1073 release_sg: 1074 kfree(ttm->sg); 1075 return r; 1076 } 1077 1078 /** 1079 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 1080 */ 1081 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 1082 { 1083 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1084 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1085 1086 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1087 enum dma_data_direction direction = write ? 1088 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1089 1090 /* double check that we don't free the table twice */ 1091 if (!ttm->sg->sgl) 1092 return; 1093 1094 /* unmap the pages mapped to the device */ 1095 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 1096 sg_free_table(ttm->sg); 1097 1098 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 1099 if (gtt->range) { 1100 unsigned long i; 1101 1102 for (i = 0; i < ttm->num_pages; i++) { 1103 if (ttm->pages[i] != 1104 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 1105 break; 1106 } 1107 1108 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 1109 } 1110 #endif 1111 } 1112 1113 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 1114 struct ttm_buffer_object *tbo, 1115 uint64_t flags) 1116 { 1117 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 1118 struct ttm_tt *ttm = tbo->ttm; 1119 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1120 int r; 1121 1122 if (amdgpu_bo_encrypted(abo)) 1123 flags |= AMDGPU_PTE_TMZ; 1124 1125 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 1126 uint64_t page_idx = 1; 1127 1128 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 1129 ttm->pages, gtt->ttm.dma_address, flags); 1130 if (r) 1131 goto gart_bind_fail; 1132 1133 /* The memory type of the first page defaults to UC. Now 1134 * modify the memory type to NC from the second page of 1135 * the BO onward. 1136 */ 1137 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1138 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 1139 1140 r = amdgpu_gart_bind(adev, 1141 gtt->offset + (page_idx << PAGE_SHIFT), 1142 ttm->num_pages - page_idx, 1143 &ttm->pages[page_idx], 1144 &(gtt->ttm.dma_address[page_idx]), flags); 1145 } else { 1146 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1147 ttm->pages, gtt->ttm.dma_address, flags); 1148 } 1149 1150 gart_bind_fail: 1151 if (r) 1152 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1153 ttm->num_pages, gtt->offset); 1154 1155 return r; 1156 } 1157 1158 /** 1159 * amdgpu_ttm_backend_bind - Bind GTT memory 1160 * 1161 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 1162 * This handles binding GTT memory to the device address space. 1163 */ 1164 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 1165 struct ttm_mem_reg *bo_mem) 1166 { 1167 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1168 struct amdgpu_ttm_tt *gtt = (void*)ttm; 1169 uint64_t flags; 1170 int r = 0; 1171 1172 if (gtt->userptr) { 1173 r = amdgpu_ttm_tt_pin_userptr(ttm); 1174 if (r) { 1175 DRM_ERROR("failed to pin userptr\n"); 1176 return r; 1177 } 1178 } 1179 if (!ttm->num_pages) { 1180 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 1181 ttm->num_pages, bo_mem, ttm); 1182 } 1183 1184 if (bo_mem->mem_type == AMDGPU_PL_GDS || 1185 bo_mem->mem_type == AMDGPU_PL_GWS || 1186 bo_mem->mem_type == AMDGPU_PL_OA) 1187 return -EINVAL; 1188 1189 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 1190 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 1191 return 0; 1192 } 1193 1194 /* compute PTE flags relevant to this BO memory */ 1195 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 1196 1197 /* bind pages into GART page tables */ 1198 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 1199 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1200 ttm->pages, gtt->ttm.dma_address, flags); 1201 1202 if (r) 1203 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1204 ttm->num_pages, gtt->offset); 1205 return r; 1206 } 1207 1208 /** 1209 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object 1210 */ 1211 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1212 { 1213 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1214 struct ttm_operation_ctx ctx = { false, false }; 1215 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; 1216 struct ttm_mem_reg tmp; 1217 struct ttm_placement placement; 1218 struct ttm_place placements; 1219 uint64_t addr, flags; 1220 int r; 1221 1222 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1223 return 0; 1224 1225 addr = amdgpu_gmc_agp_addr(bo); 1226 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1227 bo->mem.start = addr >> PAGE_SHIFT; 1228 } else { 1229 1230 /* allocate GART space */ 1231 tmp = bo->mem; 1232 tmp.mm_node = NULL; 1233 placement.num_placement = 1; 1234 placement.placement = &placements; 1235 placement.num_busy_placement = 1; 1236 placement.busy_placement = &placements; 1237 placements.fpfn = 0; 1238 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1239 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | 1240 TTM_PL_FLAG_TT; 1241 1242 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1243 if (unlikely(r)) 1244 return r; 1245 1246 /* compute PTE flags for this buffer object */ 1247 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1248 1249 /* Bind pages */ 1250 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1251 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1252 if (unlikely(r)) { 1253 ttm_bo_mem_put(bo, &tmp); 1254 return r; 1255 } 1256 1257 ttm_bo_mem_put(bo, &bo->mem); 1258 bo->mem = tmp; 1259 } 1260 1261 return 0; 1262 } 1263 1264 /** 1265 * amdgpu_ttm_recover_gart - Rebind GTT pages 1266 * 1267 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1268 * rebind GTT pages during a GPU reset. 1269 */ 1270 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1271 { 1272 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1273 uint64_t flags; 1274 int r; 1275 1276 if (!tbo->ttm) 1277 return 0; 1278 1279 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1280 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1281 1282 return r; 1283 } 1284 1285 /** 1286 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1287 * 1288 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1289 * ttm_tt_destroy(). 1290 */ 1291 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 1292 { 1293 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1294 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1295 int r; 1296 1297 /* if the pages have userptr pinning then clear that first */ 1298 if (gtt->userptr) 1299 amdgpu_ttm_tt_unpin_userptr(ttm); 1300 1301 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1302 return 0; 1303 1304 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1305 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1306 if (r) 1307 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", 1308 gtt->ttm.ttm.num_pages, gtt->offset); 1309 return r; 1310 } 1311 1312 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 1313 { 1314 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1315 1316 if (gtt->usertask) 1317 put_task_struct(gtt->usertask); 1318 1319 ttm_dma_tt_fini(>t->ttm); 1320 kfree(gtt); 1321 } 1322 1323 static struct ttm_backend_func amdgpu_backend_func = { 1324 .bind = &amdgpu_ttm_backend_bind, 1325 .unbind = &amdgpu_ttm_backend_unbind, 1326 .destroy = &amdgpu_ttm_backend_destroy, 1327 }; 1328 1329 /** 1330 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1331 * 1332 * @bo: The buffer object to create a GTT ttm_tt object around 1333 * 1334 * Called by ttm_tt_create(). 1335 */ 1336 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1337 uint32_t page_flags) 1338 { 1339 struct amdgpu_ttm_tt *gtt; 1340 1341 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1342 if (gtt == NULL) { 1343 return NULL; 1344 } 1345 gtt->ttm.ttm.func = &amdgpu_backend_func; 1346 gtt->gobj = &bo->base; 1347 1348 /* allocate space for the uninitialized page entries */ 1349 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) { 1350 kfree(gtt); 1351 return NULL; 1352 } 1353 return >t->ttm.ttm; 1354 } 1355 1356 /** 1357 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1358 * 1359 * Map the pages of a ttm_tt object to an address space visible 1360 * to the underlying device. 1361 */ 1362 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, 1363 struct ttm_operation_ctx *ctx) 1364 { 1365 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1366 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1367 1368 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1369 if (gtt && gtt->userptr) { 1370 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1371 if (!ttm->sg) 1372 return -ENOMEM; 1373 1374 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1375 ttm->state = tt_unbound; 1376 return 0; 1377 } 1378 1379 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1380 if (!ttm->sg) { 1381 struct dma_buf_attachment *attach; 1382 struct sg_table *sgt; 1383 1384 attach = gtt->gobj->import_attach; 1385 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1386 if (IS_ERR(sgt)) 1387 return PTR_ERR(sgt); 1388 1389 ttm->sg = sgt; 1390 } 1391 1392 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1393 gtt->ttm.dma_address, 1394 ttm->num_pages); 1395 ttm->state = tt_unbound; 1396 return 0; 1397 } 1398 1399 #ifdef CONFIG_SWIOTLB 1400 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1401 return ttm_dma_populate(>t->ttm, adev->dev, ctx); 1402 } 1403 #endif 1404 1405 /* fall back to generic helper to populate the page array 1406 * and map them to the device */ 1407 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx); 1408 } 1409 1410 /** 1411 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1412 * 1413 * Unmaps pages of a ttm_tt object from the device address space and 1414 * unpopulates the page array backing it. 1415 */ 1416 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 1417 { 1418 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1419 struct amdgpu_device *adev; 1420 1421 if (gtt && gtt->userptr) { 1422 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1423 kfree(ttm->sg); 1424 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1425 return; 1426 } 1427 1428 if (ttm->sg && gtt->gobj->import_attach) { 1429 struct dma_buf_attachment *attach; 1430 1431 attach = gtt->gobj->import_attach; 1432 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1433 ttm->sg = NULL; 1434 return; 1435 } 1436 1437 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1438 return; 1439 1440 adev = amdgpu_ttm_adev(ttm->bdev); 1441 1442 #ifdef CONFIG_SWIOTLB 1443 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1444 ttm_dma_unpopulate(>t->ttm, adev->dev); 1445 return; 1446 } 1447 #endif 1448 1449 /* fall back to generic helper to unmap and unpopulate array */ 1450 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); 1451 } 1452 1453 /** 1454 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1455 * task 1456 * 1457 * @ttm: The ttm_tt object to bind this userptr object to 1458 * @addr: The address in the current tasks VM space to use 1459 * @flags: Requirements of userptr object. 1460 * 1461 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1462 * to current task 1463 */ 1464 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1465 uint32_t flags) 1466 { 1467 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1468 1469 if (gtt == NULL) 1470 return -EINVAL; 1471 1472 gtt->userptr = addr; 1473 gtt->userflags = flags; 1474 1475 if (gtt->usertask) 1476 put_task_struct(gtt->usertask); 1477 gtt->usertask = current->group_leader; 1478 get_task_struct(gtt->usertask); 1479 1480 return 0; 1481 } 1482 1483 /** 1484 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1485 */ 1486 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1487 { 1488 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1489 1490 if (gtt == NULL) 1491 return NULL; 1492 1493 if (gtt->usertask == NULL) 1494 return NULL; 1495 1496 return gtt->usertask->mm; 1497 } 1498 1499 /** 1500 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1501 * address range for the current task. 1502 * 1503 */ 1504 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1505 unsigned long end) 1506 { 1507 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1508 unsigned long size; 1509 1510 if (gtt == NULL || !gtt->userptr) 1511 return false; 1512 1513 /* Return false if no part of the ttm_tt object lies within 1514 * the range 1515 */ 1516 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 1517 if (gtt->userptr > end || gtt->userptr + size <= start) 1518 return false; 1519 1520 return true; 1521 } 1522 1523 /** 1524 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1525 */ 1526 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1527 { 1528 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1529 1530 if (gtt == NULL || !gtt->userptr) 1531 return false; 1532 1533 return true; 1534 } 1535 1536 /** 1537 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1538 */ 1539 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1540 { 1541 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1542 1543 if (gtt == NULL) 1544 return false; 1545 1546 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1547 } 1548 1549 /** 1550 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1551 * 1552 * @ttm: The ttm_tt object to compute the flags for 1553 * @mem: The memory registry backing this ttm_tt object 1554 * 1555 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1556 */ 1557 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem) 1558 { 1559 uint64_t flags = 0; 1560 1561 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1562 flags |= AMDGPU_PTE_VALID; 1563 1564 if (mem && mem->mem_type == TTM_PL_TT) { 1565 flags |= AMDGPU_PTE_SYSTEM; 1566 1567 if (ttm->caching_state == tt_cached) 1568 flags |= AMDGPU_PTE_SNOOPED; 1569 } 1570 1571 return flags; 1572 } 1573 1574 /** 1575 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1576 * 1577 * @ttm: The ttm_tt object to compute the flags for 1578 * @mem: The memory registry backing this ttm_tt object 1579 1580 * Figure out the flags to use for a VM PTE (Page Table Entry). 1581 */ 1582 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1583 struct ttm_mem_reg *mem) 1584 { 1585 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1586 1587 flags |= adev->gart.gart_pte_flags; 1588 flags |= AMDGPU_PTE_READABLE; 1589 1590 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1591 flags |= AMDGPU_PTE_WRITEABLE; 1592 1593 return flags; 1594 } 1595 1596 /** 1597 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1598 * object. 1599 * 1600 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1601 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1602 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1603 * used to clean out a memory space. 1604 */ 1605 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1606 const struct ttm_place *place) 1607 { 1608 unsigned long num_pages = bo->mem.num_pages; 1609 struct drm_mm_node *node = bo->mem.mm_node; 1610 struct dma_resv_list *flist; 1611 struct dma_fence *f; 1612 int i; 1613 1614 if (bo->type == ttm_bo_type_kernel && 1615 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1616 return false; 1617 1618 /* If bo is a KFD BO, check if the bo belongs to the current process. 1619 * If true, then return false as any KFD process needs all its BOs to 1620 * be resident to run successfully 1621 */ 1622 flist = dma_resv_get_list(bo->base.resv); 1623 if (flist) { 1624 for (i = 0; i < flist->shared_count; ++i) { 1625 f = rcu_dereference_protected(flist->shared[i], 1626 dma_resv_held(bo->base.resv)); 1627 if (amdkfd_fence_check_mm(f, current->mm)) 1628 return false; 1629 } 1630 } 1631 1632 switch (bo->mem.mem_type) { 1633 case TTM_PL_TT: 1634 if (amdgpu_bo_is_amdgpu_bo(bo) && 1635 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1636 return false; 1637 return true; 1638 1639 case TTM_PL_VRAM: 1640 /* Check each drm MM node individually */ 1641 while (num_pages) { 1642 if (place->fpfn < (node->start + node->size) && 1643 !(place->lpfn && place->lpfn <= node->start)) 1644 return true; 1645 1646 num_pages -= node->size; 1647 ++node; 1648 } 1649 return false; 1650 1651 default: 1652 break; 1653 } 1654 1655 return ttm_bo_eviction_valuable(bo, place); 1656 } 1657 1658 /** 1659 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1660 * 1661 * @bo: The buffer object to read/write 1662 * @offset: Offset into buffer object 1663 * @buf: Secondary buffer to write/read from 1664 * @len: Length in bytes of access 1665 * @write: true if writing 1666 * 1667 * This is used to access VRAM that backs a buffer object via MMIO 1668 * access for debugging purposes. 1669 */ 1670 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1671 unsigned long offset, 1672 void *buf, int len, int write) 1673 { 1674 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1675 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1676 struct drm_mm_node *nodes; 1677 uint32_t value = 0; 1678 int ret = 0; 1679 uint64_t pos; 1680 unsigned long flags; 1681 1682 if (bo->mem.mem_type != TTM_PL_VRAM) 1683 return -EIO; 1684 1685 pos = offset; 1686 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); 1687 pos += (nodes->start << PAGE_SHIFT); 1688 1689 while (len && pos < adev->gmc.mc_vram_size) { 1690 uint64_t aligned_pos = pos & ~(uint64_t)3; 1691 uint64_t bytes = 4 - (pos & 3); 1692 uint32_t shift = (pos & 3) * 8; 1693 uint32_t mask = 0xffffffff << shift; 1694 1695 if (len < bytes) { 1696 mask &= 0xffffffff >> (bytes - len) * 8; 1697 bytes = len; 1698 } 1699 1700 if (mask != 0xffffffff) { 1701 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1702 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1703 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1704 if (!write || mask != 0xffffffff) 1705 value = RREG32_NO_KIQ(mmMM_DATA); 1706 if (write) { 1707 value &= ~mask; 1708 value |= (*(uint32_t *)buf << shift) & mask; 1709 WREG32_NO_KIQ(mmMM_DATA, value); 1710 } 1711 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1712 if (!write) { 1713 value = (value & mask) >> shift; 1714 memcpy(buf, &value, bytes); 1715 } 1716 } else { 1717 bytes = (nodes->start + nodes->size) << PAGE_SHIFT; 1718 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); 1719 1720 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, 1721 bytes, write); 1722 } 1723 1724 ret += bytes; 1725 buf = (uint8_t *)buf + bytes; 1726 pos += bytes; 1727 len -= bytes; 1728 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { 1729 ++nodes; 1730 pos = (nodes->start << PAGE_SHIFT); 1731 } 1732 } 1733 1734 return ret; 1735 } 1736 1737 static struct ttm_bo_driver amdgpu_bo_driver = { 1738 .ttm_tt_create = &amdgpu_ttm_tt_create, 1739 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1740 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1741 .init_mem_type = &amdgpu_init_mem_type, 1742 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1743 .evict_flags = &amdgpu_evict_flags, 1744 .move = &amdgpu_bo_move, 1745 .verify_access = &amdgpu_verify_access, 1746 .move_notify = &amdgpu_bo_move_notify, 1747 .release_notify = &amdgpu_bo_release_notify, 1748 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1749 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1750 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1751 .access_memory = &amdgpu_ttm_access_memory, 1752 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1753 }; 1754 1755 /* 1756 * Firmware Reservation functions 1757 */ 1758 /** 1759 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1760 * 1761 * @adev: amdgpu_device pointer 1762 * 1763 * free fw reserved vram if it has been reserved. 1764 */ 1765 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1766 { 1767 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, 1768 NULL, &adev->fw_vram_usage.va); 1769 } 1770 1771 /** 1772 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1773 * 1774 * @adev: amdgpu_device pointer 1775 * 1776 * create bo vram reservation from fw. 1777 */ 1778 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1779 { 1780 uint64_t vram_size = adev->gmc.visible_vram_size; 1781 1782 adev->fw_vram_usage.va = NULL; 1783 adev->fw_vram_usage.reserved_bo = NULL; 1784 1785 if (adev->fw_vram_usage.size == 0 || 1786 adev->fw_vram_usage.size > vram_size) 1787 return 0; 1788 1789 return amdgpu_bo_create_kernel_at(adev, 1790 adev->fw_vram_usage.start_offset, 1791 adev->fw_vram_usage.size, 1792 AMDGPU_GEM_DOMAIN_VRAM, 1793 &adev->fw_vram_usage.reserved_bo, 1794 &adev->fw_vram_usage.va); 1795 } 1796 1797 /* 1798 * Memoy training reservation functions 1799 */ 1800 1801 /** 1802 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1803 * 1804 * @adev: amdgpu_device pointer 1805 * 1806 * free memory training reserved vram if it has been reserved. 1807 */ 1808 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1809 { 1810 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1811 1812 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1813 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1814 ctx->c2p_bo = NULL; 1815 1816 return 0; 1817 } 1818 1819 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size) 1820 { 1821 if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) ) 1822 vram_size -= SZ_1M; 1823 1824 return ALIGN(vram_size, SZ_1M); 1825 } 1826 1827 /** 1828 * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training 1829 * 1830 * @adev: amdgpu_device pointer 1831 * 1832 * create bo vram reservation from memory training. 1833 */ 1834 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev) 1835 { 1836 int ret; 1837 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1838 1839 memset(ctx, 0, sizeof(*ctx)); 1840 if (!adev->fw_vram_usage.mem_train_support) { 1841 DRM_DEBUG("memory training does not support!\n"); 1842 return 0; 1843 } 1844 1845 ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size); 1846 ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1847 ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1848 1849 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1850 ctx->train_data_size, 1851 ctx->p2c_train_data_offset, 1852 ctx->c2p_train_data_offset); 1853 1854 ret = amdgpu_bo_create_kernel_at(adev, 1855 ctx->c2p_train_data_offset, 1856 ctx->train_data_size, 1857 AMDGPU_GEM_DOMAIN_VRAM, 1858 &ctx->c2p_bo, 1859 NULL); 1860 if (ret) { 1861 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1862 amdgpu_ttm_training_reserve_vram_fini(adev); 1863 return ret; 1864 } 1865 1866 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1867 return 0; 1868 } 1869 1870 /** 1871 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1872 * gtt/vram related fields. 1873 * 1874 * This initializes all of the memory space pools that the TTM layer 1875 * will need such as the GTT space (system memory mapped to the device), 1876 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1877 * can be mapped per VMID. 1878 */ 1879 int amdgpu_ttm_init(struct amdgpu_device *adev) 1880 { 1881 uint64_t gtt_size; 1882 int r; 1883 u64 vis_vram_limit; 1884 void *stolen_vga_buf; 1885 1886 mutex_init(&adev->mman.gtt_window_lock); 1887 1888 /* No others user of address space so set it to 0 */ 1889 r = ttm_bo_device_init(&adev->mman.bdev, 1890 &amdgpu_bo_driver, 1891 adev->ddev->anon_inode->i_mapping, 1892 adev->ddev->vma_offset_manager, 1893 dma_addressing_limited(adev->dev)); 1894 if (r) { 1895 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1896 return r; 1897 } 1898 adev->mman.initialized = true; 1899 1900 /* We opt to avoid OOM on system pages allocations */ 1901 adev->mman.bdev.no_retry = true; 1902 1903 /* Initialize VRAM pool with all of VRAM divided into pages */ 1904 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1905 adev->gmc.real_vram_size >> PAGE_SHIFT); 1906 if (r) { 1907 DRM_ERROR("Failed initializing VRAM heap.\n"); 1908 return r; 1909 } 1910 1911 /* Reduce size of CPU-visible VRAM if requested */ 1912 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1913 if (amdgpu_vis_vram_limit > 0 && 1914 vis_vram_limit <= adev->gmc.visible_vram_size) 1915 adev->gmc.visible_vram_size = vis_vram_limit; 1916 1917 /* Change the size here instead of the init above so only lpfn is affected */ 1918 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1919 #ifdef CONFIG_64BIT 1920 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1921 adev->gmc.visible_vram_size); 1922 #endif 1923 1924 /* 1925 *The reserved vram for firmware must be pinned to the specified 1926 *place on the VRAM, so reserve it early. 1927 */ 1928 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1929 if (r) { 1930 return r; 1931 } 1932 1933 /* 1934 *The reserved vram for memory training must be pinned to the specified 1935 *place on the VRAM, so reserve it early. 1936 */ 1937 if (!amdgpu_sriov_vf(adev)) { 1938 r = amdgpu_ttm_training_reserve_vram_init(adev); 1939 if (r) 1940 return r; 1941 } 1942 1943 /* allocate memory as required for VGA 1944 * This is used for VGA emulation and pre-OS scanout buffers to 1945 * avoid display artifacts while transitioning between pre-OS 1946 * and driver. */ 1947 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, 1948 AMDGPU_GEM_DOMAIN_VRAM, 1949 &adev->stolen_vga_memory, 1950 NULL, &stolen_vga_buf); 1951 if (r) 1952 return r; 1953 1954 /* 1955 * reserve TMR memory at the top of VRAM which holds 1956 * IP Discovery data and is protected by PSP. 1957 */ 1958 if (adev->discovery_tmr_size > 0) { 1959 r = amdgpu_bo_create_kernel_at(adev, 1960 adev->gmc.real_vram_size - adev->discovery_tmr_size, 1961 adev->discovery_tmr_size, 1962 AMDGPU_GEM_DOMAIN_VRAM, 1963 &adev->discovery_memory, 1964 NULL); 1965 if (r) 1966 return r; 1967 } 1968 1969 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1970 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1971 1972 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1973 * or whatever the user passed on module init */ 1974 if (amdgpu_gtt_size == -1) { 1975 struct sysinfo si; 1976 1977 si_meminfo(&si); 1978 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1979 adev->gmc.mc_vram_size), 1980 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1981 } 1982 else 1983 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1984 1985 /* Initialize GTT memory pool */ 1986 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); 1987 if (r) { 1988 DRM_ERROR("Failed initializing GTT heap.\n"); 1989 return r; 1990 } 1991 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1992 (unsigned)(gtt_size / (1024 * 1024))); 1993 1994 /* Initialize various on-chip memory pools */ 1995 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 1996 adev->gds.gds_size); 1997 if (r) { 1998 DRM_ERROR("Failed initializing GDS heap.\n"); 1999 return r; 2000 } 2001 2002 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 2003 adev->gds.gws_size); 2004 if (r) { 2005 DRM_ERROR("Failed initializing gws heap.\n"); 2006 return r; 2007 } 2008 2009 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 2010 adev->gds.oa_size); 2011 if (r) { 2012 DRM_ERROR("Failed initializing oa heap.\n"); 2013 return r; 2014 } 2015 2016 return 0; 2017 } 2018 2019 /** 2020 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm 2021 */ 2022 void amdgpu_ttm_late_init(struct amdgpu_device *adev) 2023 { 2024 void *stolen_vga_buf; 2025 /* return the VGA stolen memory (if any) back to VRAM */ 2026 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 2027 } 2028 2029 /** 2030 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2031 */ 2032 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2033 { 2034 if (!adev->mman.initialized) 2035 return; 2036 2037 amdgpu_ttm_training_reserve_vram_fini(adev); 2038 /* return the IP Discovery TMR memory back to VRAM */ 2039 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL); 2040 amdgpu_ttm_fw_reserve_vram_fini(adev); 2041 2042 if (adev->mman.aper_base_kaddr) 2043 iounmap(adev->mman.aper_base_kaddr); 2044 adev->mman.aper_base_kaddr = NULL; 2045 2046 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 2047 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 2048 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 2049 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 2050 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 2051 ttm_bo_device_release(&adev->mman.bdev); 2052 adev->mman.initialized = false; 2053 DRM_INFO("amdgpu: ttm finalized\n"); 2054 } 2055 2056 /** 2057 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2058 * 2059 * @adev: amdgpu_device pointer 2060 * @enable: true when we can use buffer functions. 2061 * 2062 * Enable/disable use of buffer functions during suspend/resume. This should 2063 * only be called at bootup or when userspace isn't running. 2064 */ 2065 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2066 { 2067 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM]; 2068 uint64_t size; 2069 int r; 2070 2071 if (!adev->mman.initialized || adev->in_gpu_reset || 2072 adev->mman.buffer_funcs_enabled == enable) 2073 return; 2074 2075 if (enable) { 2076 struct amdgpu_ring *ring; 2077 struct drm_gpu_scheduler *sched; 2078 2079 ring = adev->mman.buffer_funcs_ring; 2080 sched = &ring->sched; 2081 r = drm_sched_entity_init(&adev->mman.entity, 2082 DRM_SCHED_PRIORITY_KERNEL, &sched, 2083 1, NULL); 2084 if (r) { 2085 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2086 r); 2087 return; 2088 } 2089 } else { 2090 drm_sched_entity_destroy(&adev->mman.entity); 2091 dma_fence_put(man->move); 2092 man->move = NULL; 2093 } 2094 2095 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2096 if (enable) 2097 size = adev->gmc.real_vram_size; 2098 else 2099 size = adev->gmc.visible_vram_size; 2100 man->size = size >> PAGE_SHIFT; 2101 adev->mman.buffer_funcs_enabled = enable; 2102 } 2103 2104 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 2105 { 2106 struct drm_file *file_priv = filp->private_data; 2107 struct amdgpu_device *adev = file_priv->minor->dev->dev_private; 2108 2109 if (adev == NULL) 2110 return -EINVAL; 2111 2112 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 2113 } 2114 2115 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2116 uint64_t dst_offset, uint32_t byte_count, 2117 struct dma_resv *resv, 2118 struct dma_fence **fence, bool direct_submit, 2119 bool vm_needs_flush, bool tmz) 2120 { 2121 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 2122 AMDGPU_IB_POOL_DELAYED; 2123 struct amdgpu_device *adev = ring->adev; 2124 struct amdgpu_job *job; 2125 2126 uint32_t max_bytes; 2127 unsigned num_loops, num_dw; 2128 unsigned i; 2129 int r; 2130 2131 if (direct_submit && !ring->sched.ready) { 2132 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2133 return -EINVAL; 2134 } 2135 2136 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2137 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2138 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2139 2140 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 2141 if (r) 2142 return r; 2143 2144 if (vm_needs_flush) { 2145 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 2146 job->vm_needs_flush = true; 2147 } 2148 if (resv) { 2149 r = amdgpu_sync_resv(adev, &job->sync, resv, 2150 AMDGPU_SYNC_ALWAYS, 2151 AMDGPU_FENCE_OWNER_UNDEFINED); 2152 if (r) { 2153 DRM_ERROR("sync failed (%d).\n", r); 2154 goto error_free; 2155 } 2156 } 2157 2158 for (i = 0; i < num_loops; i++) { 2159 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2160 2161 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2162 dst_offset, cur_size_in_bytes, tmz); 2163 2164 src_offset += cur_size_in_bytes; 2165 dst_offset += cur_size_in_bytes; 2166 byte_count -= cur_size_in_bytes; 2167 } 2168 2169 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2170 WARN_ON(job->ibs[0].length_dw > num_dw); 2171 if (direct_submit) 2172 r = amdgpu_job_submit_direct(job, ring, fence); 2173 else 2174 r = amdgpu_job_submit(job, &adev->mman.entity, 2175 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2176 if (r) 2177 goto error_free; 2178 2179 return r; 2180 2181 error_free: 2182 amdgpu_job_free(job); 2183 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2184 return r; 2185 } 2186 2187 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2188 uint32_t src_data, 2189 struct dma_resv *resv, 2190 struct dma_fence **fence) 2191 { 2192 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2193 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2194 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2195 2196 struct drm_mm_node *mm_node; 2197 unsigned long num_pages; 2198 unsigned int num_loops, num_dw; 2199 2200 struct amdgpu_job *job; 2201 int r; 2202 2203 if (!adev->mman.buffer_funcs_enabled) { 2204 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2205 return -EINVAL; 2206 } 2207 2208 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2209 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2210 if (r) 2211 return r; 2212 } 2213 2214 num_pages = bo->tbo.num_pages; 2215 mm_node = bo->tbo.mem.mm_node; 2216 num_loops = 0; 2217 while (num_pages) { 2218 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2219 2220 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); 2221 num_pages -= mm_node->size; 2222 ++mm_node; 2223 } 2224 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2225 2226 /* for IB padding */ 2227 num_dw += 64; 2228 2229 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2230 &job); 2231 if (r) 2232 return r; 2233 2234 if (resv) { 2235 r = amdgpu_sync_resv(adev, &job->sync, resv, 2236 AMDGPU_SYNC_ALWAYS, 2237 AMDGPU_FENCE_OWNER_UNDEFINED); 2238 if (r) { 2239 DRM_ERROR("sync failed (%d).\n", r); 2240 goto error_free; 2241 } 2242 } 2243 2244 num_pages = bo->tbo.num_pages; 2245 mm_node = bo->tbo.mem.mm_node; 2246 2247 while (num_pages) { 2248 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2249 uint64_t dst_addr; 2250 2251 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); 2252 while (byte_count) { 2253 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, 2254 max_bytes); 2255 2256 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 2257 dst_addr, cur_size_in_bytes); 2258 2259 dst_addr += cur_size_in_bytes; 2260 byte_count -= cur_size_in_bytes; 2261 } 2262 2263 num_pages -= mm_node->size; 2264 ++mm_node; 2265 } 2266 2267 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2268 WARN_ON(job->ibs[0].length_dw > num_dw); 2269 r = amdgpu_job_submit(job, &adev->mman.entity, 2270 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2271 if (r) 2272 goto error_free; 2273 2274 return 0; 2275 2276 error_free: 2277 amdgpu_job_free(job); 2278 return r; 2279 } 2280 2281 #if defined(CONFIG_DEBUG_FS) 2282 2283 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 2284 { 2285 struct drm_info_node *node = (struct drm_info_node *)m->private; 2286 unsigned ttm_pl = (uintptr_t)node->info_ent->data; 2287 struct drm_device *dev = node->minor->dev; 2288 struct amdgpu_device *adev = dev->dev_private; 2289 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl]; 2290 struct drm_printer p = drm_seq_file_printer(m); 2291 2292 man->func->debug(man, &p); 2293 return 0; 2294 } 2295 2296 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 2297 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, 2298 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, 2299 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, 2300 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, 2301 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, 2302 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 2303 #ifdef CONFIG_SWIOTLB 2304 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 2305 #endif 2306 }; 2307 2308 /** 2309 * amdgpu_ttm_vram_read - Linear read access to VRAM 2310 * 2311 * Accesses VRAM via MMIO for debugging purposes. 2312 */ 2313 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2314 size_t size, loff_t *pos) 2315 { 2316 struct amdgpu_device *adev = file_inode(f)->i_private; 2317 ssize_t result = 0; 2318 2319 if (size & 0x3 || *pos & 0x3) 2320 return -EINVAL; 2321 2322 if (*pos >= adev->gmc.mc_vram_size) 2323 return -ENXIO; 2324 2325 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2326 while (size) { 2327 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2328 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2329 2330 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2331 if (copy_to_user(buf, value, bytes)) 2332 return -EFAULT; 2333 2334 result += bytes; 2335 buf += bytes; 2336 *pos += bytes; 2337 size -= bytes; 2338 } 2339 2340 return result; 2341 } 2342 2343 /** 2344 * amdgpu_ttm_vram_write - Linear write access to VRAM 2345 * 2346 * Accesses VRAM via MMIO for debugging purposes. 2347 */ 2348 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2349 size_t size, loff_t *pos) 2350 { 2351 struct amdgpu_device *adev = file_inode(f)->i_private; 2352 ssize_t result = 0; 2353 int r; 2354 2355 if (size & 0x3 || *pos & 0x3) 2356 return -EINVAL; 2357 2358 if (*pos >= adev->gmc.mc_vram_size) 2359 return -ENXIO; 2360 2361 while (size) { 2362 unsigned long flags; 2363 uint32_t value; 2364 2365 if (*pos >= adev->gmc.mc_vram_size) 2366 return result; 2367 2368 r = get_user(value, (uint32_t *)buf); 2369 if (r) 2370 return r; 2371 2372 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2373 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2374 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2375 WREG32_NO_KIQ(mmMM_DATA, value); 2376 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2377 2378 result += 4; 2379 buf += 4; 2380 *pos += 4; 2381 size -= 4; 2382 } 2383 2384 return result; 2385 } 2386 2387 static const struct file_operations amdgpu_ttm_vram_fops = { 2388 .owner = THIS_MODULE, 2389 .read = amdgpu_ttm_vram_read, 2390 .write = amdgpu_ttm_vram_write, 2391 .llseek = default_llseek, 2392 }; 2393 2394 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2395 2396 /** 2397 * amdgpu_ttm_gtt_read - Linear read access to GTT memory 2398 */ 2399 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 2400 size_t size, loff_t *pos) 2401 { 2402 struct amdgpu_device *adev = file_inode(f)->i_private; 2403 ssize_t result = 0; 2404 int r; 2405 2406 while (size) { 2407 loff_t p = *pos / PAGE_SIZE; 2408 unsigned off = *pos & ~PAGE_MASK; 2409 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 2410 struct page *page; 2411 void *ptr; 2412 2413 if (p >= adev->gart.num_cpu_pages) 2414 return result; 2415 2416 page = adev->gart.pages[p]; 2417 if (page) { 2418 ptr = kmap(page); 2419 ptr += off; 2420 2421 r = copy_to_user(buf, ptr, cur_size); 2422 kunmap(adev->gart.pages[p]); 2423 } else 2424 r = clear_user(buf, cur_size); 2425 2426 if (r) 2427 return -EFAULT; 2428 2429 result += cur_size; 2430 buf += cur_size; 2431 *pos += cur_size; 2432 size -= cur_size; 2433 } 2434 2435 return result; 2436 } 2437 2438 static const struct file_operations amdgpu_ttm_gtt_fops = { 2439 .owner = THIS_MODULE, 2440 .read = amdgpu_ttm_gtt_read, 2441 .llseek = default_llseek 2442 }; 2443 2444 #endif 2445 2446 /** 2447 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2448 * 2449 * This function is used to read memory that has been mapped to the 2450 * GPU and the known addresses are not physical addresses but instead 2451 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2452 */ 2453 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2454 size_t size, loff_t *pos) 2455 { 2456 struct amdgpu_device *adev = file_inode(f)->i_private; 2457 struct iommu_domain *dom; 2458 ssize_t result = 0; 2459 int r; 2460 2461 /* retrieve the IOMMU domain if any for this device */ 2462 dom = iommu_get_domain_for_dev(adev->dev); 2463 2464 while (size) { 2465 phys_addr_t addr = *pos & PAGE_MASK; 2466 loff_t off = *pos & ~PAGE_MASK; 2467 size_t bytes = PAGE_SIZE - off; 2468 unsigned long pfn; 2469 struct page *p; 2470 void *ptr; 2471 2472 bytes = bytes < size ? bytes : size; 2473 2474 /* Translate the bus address to a physical address. If 2475 * the domain is NULL it means there is no IOMMU active 2476 * and the address translation is the identity 2477 */ 2478 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2479 2480 pfn = addr >> PAGE_SHIFT; 2481 if (!pfn_valid(pfn)) 2482 return -EPERM; 2483 2484 p = pfn_to_page(pfn); 2485 if (p->mapping != adev->mman.bdev.dev_mapping) 2486 return -EPERM; 2487 2488 ptr = kmap(p); 2489 r = copy_to_user(buf, ptr + off, bytes); 2490 kunmap(p); 2491 if (r) 2492 return -EFAULT; 2493 2494 size -= bytes; 2495 *pos += bytes; 2496 result += bytes; 2497 } 2498 2499 return result; 2500 } 2501 2502 /** 2503 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2504 * 2505 * This function is used to write memory that has been mapped to the 2506 * GPU and the known addresses are not physical addresses but instead 2507 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2508 */ 2509 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2510 size_t size, loff_t *pos) 2511 { 2512 struct amdgpu_device *adev = file_inode(f)->i_private; 2513 struct iommu_domain *dom; 2514 ssize_t result = 0; 2515 int r; 2516 2517 dom = iommu_get_domain_for_dev(adev->dev); 2518 2519 while (size) { 2520 phys_addr_t addr = *pos & PAGE_MASK; 2521 loff_t off = *pos & ~PAGE_MASK; 2522 size_t bytes = PAGE_SIZE - off; 2523 unsigned long pfn; 2524 struct page *p; 2525 void *ptr; 2526 2527 bytes = bytes < size ? bytes : size; 2528 2529 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2530 2531 pfn = addr >> PAGE_SHIFT; 2532 if (!pfn_valid(pfn)) 2533 return -EPERM; 2534 2535 p = pfn_to_page(pfn); 2536 if (p->mapping != adev->mman.bdev.dev_mapping) 2537 return -EPERM; 2538 2539 ptr = kmap(p); 2540 r = copy_from_user(ptr + off, buf, bytes); 2541 kunmap(p); 2542 if (r) 2543 return -EFAULT; 2544 2545 size -= bytes; 2546 *pos += bytes; 2547 result += bytes; 2548 } 2549 2550 return result; 2551 } 2552 2553 static const struct file_operations amdgpu_ttm_iomem_fops = { 2554 .owner = THIS_MODULE, 2555 .read = amdgpu_iomem_read, 2556 .write = amdgpu_iomem_write, 2557 .llseek = default_llseek 2558 }; 2559 2560 static const struct { 2561 char *name; 2562 const struct file_operations *fops; 2563 int domain; 2564 } ttm_debugfs_entries[] = { 2565 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, 2566 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2567 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, 2568 #endif 2569 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, 2570 }; 2571 2572 #endif 2573 2574 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2575 { 2576 #if defined(CONFIG_DEBUG_FS) 2577 unsigned count; 2578 2579 struct drm_minor *minor = adev->ddev->primary; 2580 struct dentry *ent, *root = minor->debugfs_root; 2581 2582 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { 2583 ent = debugfs_create_file( 2584 ttm_debugfs_entries[count].name, 2585 S_IFREG | S_IRUGO, root, 2586 adev, 2587 ttm_debugfs_entries[count].fops); 2588 if (IS_ERR(ent)) 2589 return PTR_ERR(ent); 2590 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) 2591 i_size_write(ent->d_inode, adev->gmc.mc_vram_size); 2592 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) 2593 i_size_write(ent->d_inode, adev->gmc.gart_size); 2594 adev->mman.debugfs_entries[count] = ent; 2595 } 2596 2597 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 2598 2599 #ifdef CONFIG_SWIOTLB 2600 if (!(adev->need_swiotlb && swiotlb_nr_tbl())) 2601 --count; 2602 #endif 2603 2604 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 2605 #else 2606 return 0; 2607 #endif 2608 } 2609