1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/pagemap.h>
36 #include <linux/sched/task.h>
37 #include <linux/sched/mm.h>
38 #include <linux/seq_file.h>
39 #include <linux/slab.h>
40 #include <linux/swap.h>
41 #include <linux/swiotlb.h>
42 #include <linux/dma-buf.h>
43 #include <linux/sizes.h>
44 #include <linux/module.h>
45 
46 #include <drm/drm_drv.h>
47 #include <drm/ttm/ttm_bo_api.h>
48 #include <drm/ttm/ttm_bo_driver.h>
49 #include <drm/ttm/ttm_placement.h>
50 #include <drm/ttm/ttm_range_manager.h>
51 
52 #include <drm/amdgpu_drm.h>
53 #include <drm/drm_drv.h>
54 
55 #include "amdgpu.h"
56 #include "amdgpu_object.h"
57 #include "amdgpu_trace.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_sdma.h"
60 #include "amdgpu_ras.h"
61 #include "amdgpu_atomfirmware.h"
62 #include "amdgpu_res_cursor.h"
63 #include "bif/bif_4_1_d.h"
64 
65 MODULE_IMPORT_NS(DMA_BUF);
66 
67 #define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128
68 
69 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
70 				   struct ttm_tt *ttm,
71 				   struct ttm_resource *bo_mem);
72 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
73 				      struct ttm_tt *ttm);
74 
75 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
76 				    unsigned int type,
77 				    uint64_t size_in_page)
78 {
79 	return ttm_range_man_init(&adev->mman.bdev, type,
80 				  false, size_in_page);
81 }
82 
83 /**
84  * amdgpu_evict_flags - Compute placement flags
85  *
86  * @bo: The buffer object to evict
87  * @placement: Possible destination(s) for evicted BO
88  *
89  * Fill in placement data when ttm_bo_evict() is called
90  */
91 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
92 				struct ttm_placement *placement)
93 {
94 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
95 	struct amdgpu_bo *abo;
96 	static const struct ttm_place placements = {
97 		.fpfn = 0,
98 		.lpfn = 0,
99 		.mem_type = TTM_PL_SYSTEM,
100 		.flags = 0
101 	};
102 
103 	/* Don't handle scatter gather BOs */
104 	if (bo->type == ttm_bo_type_sg) {
105 		placement->num_placement = 0;
106 		placement->num_busy_placement = 0;
107 		return;
108 	}
109 
110 	/* Object isn't an AMDGPU object so ignore */
111 	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
112 		placement->placement = &placements;
113 		placement->busy_placement = &placements;
114 		placement->num_placement = 1;
115 		placement->num_busy_placement = 1;
116 		return;
117 	}
118 
119 	abo = ttm_to_amdgpu_bo(bo);
120 	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
121 		placement->num_placement = 0;
122 		placement->num_busy_placement = 0;
123 		return;
124 	}
125 
126 	switch (bo->resource->mem_type) {
127 	case AMDGPU_PL_GDS:
128 	case AMDGPU_PL_GWS:
129 	case AMDGPU_PL_OA:
130 		placement->num_placement = 0;
131 		placement->num_busy_placement = 0;
132 		return;
133 
134 	case TTM_PL_VRAM:
135 		if (!adev->mman.buffer_funcs_enabled) {
136 			/* Move to system memory */
137 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
138 		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
139 			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
140 			   amdgpu_bo_in_cpu_visible_vram(abo)) {
141 
142 			/* Try evicting to the CPU inaccessible part of VRAM
143 			 * first, but only set GTT as busy placement, so this
144 			 * BO will be evicted to GTT rather than causing other
145 			 * BOs to be evicted from VRAM
146 			 */
147 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
148 							AMDGPU_GEM_DOMAIN_GTT |
149 							AMDGPU_GEM_DOMAIN_CPU);
150 			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
151 			abo->placements[0].lpfn = 0;
152 			abo->placement.busy_placement = &abo->placements[1];
153 			abo->placement.num_busy_placement = 1;
154 		} else {
155 			/* Move to GTT memory */
156 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
157 							AMDGPU_GEM_DOMAIN_CPU);
158 		}
159 		break;
160 	case TTM_PL_TT:
161 	case AMDGPU_PL_PREEMPT:
162 	default:
163 		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
164 		break;
165 	}
166 	*placement = abo->placement;
167 }
168 
169 /**
170  * amdgpu_ttm_map_buffer - Map memory into the GART windows
171  * @bo: buffer object to map
172  * @mem: memory object to map
173  * @mm_cur: range to map
174  * @window: which GART window to use
175  * @ring: DMA ring to use for the copy
176  * @tmz: if we should setup a TMZ enabled mapping
177  * @size: in number of bytes to map, out number of bytes mapped
178  * @addr: resulting address inside the MC address space
179  *
180  * Setup one of the GART windows to access a specific piece of memory or return
181  * the physical address for local memory.
182  */
183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
184 				 struct ttm_resource *mem,
185 				 struct amdgpu_res_cursor *mm_cur,
186 				 unsigned window, struct amdgpu_ring *ring,
187 				 bool tmz, uint64_t *size, uint64_t *addr)
188 {
189 	struct amdgpu_device *adev = ring->adev;
190 	unsigned offset, num_pages, num_dw, num_bytes;
191 	uint64_t src_addr, dst_addr;
192 	struct dma_fence *fence;
193 	struct amdgpu_job *job;
194 	void *cpu_addr;
195 	uint64_t flags;
196 	unsigned int i;
197 	int r;
198 
199 	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
200 	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
201 
202 	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
203 		return -EINVAL;
204 
205 	/* Map only what can't be accessed directly */
206 	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
207 		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
208 			mm_cur->start;
209 		return 0;
210 	}
211 
212 
213 	/*
214 	 * If start begins at an offset inside the page, then adjust the size
215 	 * and addr accordingly
216 	 */
217 	offset = mm_cur->start & ~PAGE_MASK;
218 
219 	num_pages = PFN_UP(*size + offset);
220 	num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
221 
222 	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
223 
224 	*addr = adev->gmc.gart_start;
225 	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
226 		AMDGPU_GPU_PAGE_SIZE;
227 	*addr += offset;
228 
229 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
230 	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
231 
232 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
233 				     AMDGPU_IB_POOL_DELAYED, &job);
234 	if (r)
235 		return r;
236 
237 	src_addr = num_dw * 4;
238 	src_addr += job->ibs[0].gpu_addr;
239 
240 	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
241 	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
242 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
243 				dst_addr, num_bytes, false);
244 
245 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
246 	WARN_ON(job->ibs[0].length_dw > num_dw);
247 
248 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
249 	if (tmz)
250 		flags |= AMDGPU_PTE_TMZ;
251 
252 	cpu_addr = &job->ibs[0].ptr[num_dw];
253 
254 	if (mem->mem_type == TTM_PL_TT) {
255 		dma_addr_t *dma_addr;
256 
257 		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
258 		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
259 	} else {
260 		dma_addr_t dma_address;
261 
262 		dma_address = mm_cur->start;
263 		dma_address += adev->vm_manager.vram_base_offset;
264 
265 		for (i = 0; i < num_pages; ++i) {
266 			amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
267 					flags, cpu_addr);
268 			dma_address += PAGE_SIZE;
269 		}
270 	}
271 
272 	r = amdgpu_job_submit(job, &adev->mman.entity,
273 			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
274 	if (r)
275 		goto error_free;
276 
277 	dma_fence_put(fence);
278 
279 	return r;
280 
281 error_free:
282 	amdgpu_job_free(job);
283 	return r;
284 }
285 
286 /**
287  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
288  * @adev: amdgpu device
289  * @src: buffer/address where to read from
290  * @dst: buffer/address where to write to
291  * @size: number of bytes to copy
292  * @tmz: if a secure copy should be used
293  * @resv: resv object to sync to
294  * @f: Returns the last fence if multiple jobs are submitted.
295  *
296  * The function copies @size bytes from {src->mem + src->offset} to
297  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
298  * move and different for a BO to BO copy.
299  *
300  */
301 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
302 			       const struct amdgpu_copy_mem *src,
303 			       const struct amdgpu_copy_mem *dst,
304 			       uint64_t size, bool tmz,
305 			       struct dma_resv *resv,
306 			       struct dma_fence **f)
307 {
308 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
309 	struct amdgpu_res_cursor src_mm, dst_mm;
310 	struct dma_fence *fence = NULL;
311 	int r = 0;
312 
313 	if (!adev->mman.buffer_funcs_enabled) {
314 		DRM_ERROR("Trying to move memory with ring turned off.\n");
315 		return -EINVAL;
316 	}
317 
318 	amdgpu_res_first(src->mem, src->offset, size, &src_mm);
319 	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
320 
321 	mutex_lock(&adev->mman.gtt_window_lock);
322 	while (src_mm.remaining) {
323 		uint64_t from, to, cur_size;
324 		struct dma_fence *next;
325 
326 		/* Never copy more than 256MiB at once to avoid a timeout */
327 		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
328 
329 		/* Map src to window 0 and dst to window 1. */
330 		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
331 					  0, ring, tmz, &cur_size, &from);
332 		if (r)
333 			goto error;
334 
335 		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
336 					  1, ring, tmz, &cur_size, &to);
337 		if (r)
338 			goto error;
339 
340 		r = amdgpu_copy_buffer(ring, from, to, cur_size,
341 				       resv, &next, false, true, tmz);
342 		if (r)
343 			goto error;
344 
345 		dma_fence_put(fence);
346 		fence = next;
347 
348 		amdgpu_res_next(&src_mm, cur_size);
349 		amdgpu_res_next(&dst_mm, cur_size);
350 	}
351 error:
352 	mutex_unlock(&adev->mman.gtt_window_lock);
353 	if (f)
354 		*f = dma_fence_get(fence);
355 	dma_fence_put(fence);
356 	return r;
357 }
358 
359 /*
360  * amdgpu_move_blit - Copy an entire buffer to another buffer
361  *
362  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
363  * help move buffers to and from VRAM.
364  */
365 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
366 			    bool evict,
367 			    struct ttm_resource *new_mem,
368 			    struct ttm_resource *old_mem)
369 {
370 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
371 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
372 	struct amdgpu_copy_mem src, dst;
373 	struct dma_fence *fence = NULL;
374 	int r;
375 
376 	src.bo = bo;
377 	dst.bo = bo;
378 	src.mem = old_mem;
379 	dst.mem = new_mem;
380 	src.offset = 0;
381 	dst.offset = 0;
382 
383 	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
384 				       new_mem->num_pages << PAGE_SHIFT,
385 				       amdgpu_bo_encrypted(abo),
386 				       bo->base.resv, &fence);
387 	if (r)
388 		goto error;
389 
390 	/* clear the space being freed */
391 	if (old_mem->mem_type == TTM_PL_VRAM &&
392 	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
393 		struct dma_fence *wipe_fence = NULL;
394 
395 		r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence);
396 		if (r) {
397 			goto error;
398 		} else if (wipe_fence) {
399 			dma_fence_put(fence);
400 			fence = wipe_fence;
401 		}
402 	}
403 
404 	/* Always block for VM page tables before committing the new location */
405 	if (bo->type == ttm_bo_type_kernel)
406 		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
407 	else
408 		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
409 	dma_fence_put(fence);
410 	return r;
411 
412 error:
413 	if (fence)
414 		dma_fence_wait(fence, false);
415 	dma_fence_put(fence);
416 	return r;
417 }
418 
419 /*
420  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
421  *
422  * Called by amdgpu_bo_move()
423  */
424 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
425 			       struct ttm_resource *mem)
426 {
427 	u64 mem_size = (u64)mem->num_pages << PAGE_SHIFT;
428 	struct amdgpu_res_cursor cursor;
429 	u64 end;
430 
431 	if (mem->mem_type == TTM_PL_SYSTEM ||
432 	    mem->mem_type == TTM_PL_TT)
433 		return true;
434 	if (mem->mem_type != TTM_PL_VRAM)
435 		return false;
436 
437 	amdgpu_res_first(mem, 0, mem_size, &cursor);
438 	end = cursor.start + cursor.size;
439 	while (cursor.remaining) {
440 		amdgpu_res_next(&cursor, cursor.size);
441 
442 		if (!cursor.remaining)
443 			break;
444 
445 		/* ttm_resource_ioremap only supports contiguous memory */
446 		if (end != cursor.start)
447 			return false;
448 
449 		end = cursor.start + cursor.size;
450 	}
451 
452 	return end <= adev->gmc.visible_vram_size;
453 }
454 
455 /*
456  * amdgpu_bo_move - Move a buffer object to a new memory location
457  *
458  * Called by ttm_bo_handle_move_mem()
459  */
460 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
461 			  struct ttm_operation_ctx *ctx,
462 			  struct ttm_resource *new_mem,
463 			  struct ttm_place *hop)
464 {
465 	struct amdgpu_device *adev;
466 	struct amdgpu_bo *abo;
467 	struct ttm_resource *old_mem = bo->resource;
468 	int r;
469 
470 	if (new_mem->mem_type == TTM_PL_TT ||
471 	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
472 		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
473 		if (r)
474 			return r;
475 	}
476 
477 	/* Can't move a pinned BO */
478 	abo = ttm_to_amdgpu_bo(bo);
479 	if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
480 		return -EINVAL;
481 
482 	adev = amdgpu_ttm_adev(bo->bdev);
483 
484 	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
485 			 bo->ttm == NULL)) {
486 		ttm_bo_move_null(bo, new_mem);
487 		goto out;
488 	}
489 	if (old_mem->mem_type == TTM_PL_SYSTEM &&
490 	    (new_mem->mem_type == TTM_PL_TT ||
491 	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
492 		ttm_bo_move_null(bo, new_mem);
493 		goto out;
494 	}
495 	if ((old_mem->mem_type == TTM_PL_TT ||
496 	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
497 	    new_mem->mem_type == TTM_PL_SYSTEM) {
498 		r = ttm_bo_wait_ctx(bo, ctx);
499 		if (r)
500 			return r;
501 
502 		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
503 		ttm_resource_free(bo, &bo->resource);
504 		ttm_bo_assign_mem(bo, new_mem);
505 		goto out;
506 	}
507 
508 	if (old_mem->mem_type == AMDGPU_PL_GDS ||
509 	    old_mem->mem_type == AMDGPU_PL_GWS ||
510 	    old_mem->mem_type == AMDGPU_PL_OA ||
511 	    new_mem->mem_type == AMDGPU_PL_GDS ||
512 	    new_mem->mem_type == AMDGPU_PL_GWS ||
513 	    new_mem->mem_type == AMDGPU_PL_OA) {
514 		/* Nothing to save here */
515 		ttm_bo_move_null(bo, new_mem);
516 		goto out;
517 	}
518 
519 	if (bo->type == ttm_bo_type_device &&
520 	    new_mem->mem_type == TTM_PL_VRAM &&
521 	    old_mem->mem_type != TTM_PL_VRAM) {
522 		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
523 		 * accesses the BO after it's moved.
524 		 */
525 		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
526 	}
527 
528 	if (adev->mman.buffer_funcs_enabled) {
529 		if (((old_mem->mem_type == TTM_PL_SYSTEM &&
530 		      new_mem->mem_type == TTM_PL_VRAM) ||
531 		     (old_mem->mem_type == TTM_PL_VRAM &&
532 		      new_mem->mem_type == TTM_PL_SYSTEM))) {
533 			hop->fpfn = 0;
534 			hop->lpfn = 0;
535 			hop->mem_type = TTM_PL_TT;
536 			hop->flags = TTM_PL_FLAG_TEMPORARY;
537 			return -EMULTIHOP;
538 		}
539 
540 		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
541 	} else {
542 		r = -ENODEV;
543 	}
544 
545 	if (r) {
546 		/* Check that all memory is CPU accessible */
547 		if (!amdgpu_mem_visible(adev, old_mem) ||
548 		    !amdgpu_mem_visible(adev, new_mem)) {
549 			pr_err("Move buffer fallback to memcpy unavailable\n");
550 			return r;
551 		}
552 
553 		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
554 		if (r)
555 			return r;
556 	}
557 
558 out:
559 	/* update statistics */
560 	atomic64_add(bo->base.size, &adev->num_bytes_moved);
561 	amdgpu_bo_move_notify(bo, evict, new_mem);
562 	return 0;
563 }
564 
565 /*
566  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
567  *
568  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
569  */
570 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
571 				     struct ttm_resource *mem)
572 {
573 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
574 	size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
575 
576 	switch (mem->mem_type) {
577 	case TTM_PL_SYSTEM:
578 		/* system memory */
579 		return 0;
580 	case TTM_PL_TT:
581 	case AMDGPU_PL_PREEMPT:
582 		break;
583 	case TTM_PL_VRAM:
584 		mem->bus.offset = mem->start << PAGE_SHIFT;
585 		/* check if it's visible */
586 		if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
587 			return -EINVAL;
588 
589 		if (adev->mman.aper_base_kaddr &&
590 		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
591 			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
592 					mem->bus.offset;
593 
594 		mem->bus.offset += adev->gmc.aper_base;
595 		mem->bus.is_iomem = true;
596 		break;
597 	default:
598 		return -EINVAL;
599 	}
600 	return 0;
601 }
602 
603 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
604 					   unsigned long page_offset)
605 {
606 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
607 	struct amdgpu_res_cursor cursor;
608 
609 	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
610 			 &cursor);
611 	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
612 }
613 
614 /**
615  * amdgpu_ttm_domain_start - Returns GPU start address
616  * @adev: amdgpu device object
617  * @type: type of the memory
618  *
619  * Returns:
620  * GPU start address of a memory domain
621  */
622 
623 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
624 {
625 	switch (type) {
626 	case TTM_PL_TT:
627 		return adev->gmc.gart_start;
628 	case TTM_PL_VRAM:
629 		return adev->gmc.vram_start;
630 	}
631 
632 	return 0;
633 }
634 
635 /*
636  * TTM backend functions.
637  */
638 struct amdgpu_ttm_tt {
639 	struct ttm_tt	ttm;
640 	struct drm_gem_object	*gobj;
641 	u64			offset;
642 	uint64_t		userptr;
643 	struct task_struct	*usertask;
644 	uint32_t		userflags;
645 	bool			bound;
646 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
647 	struct hmm_range	*range;
648 #endif
649 };
650 
651 #define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)
652 
653 #ifdef CONFIG_DRM_AMDGPU_USERPTR
654 /*
655  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
656  * memory and start HMM tracking CPU page table update
657  *
658  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
659  * once afterwards to stop HMM tracking
660  */
661 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
662 {
663 	struct ttm_tt *ttm = bo->tbo.ttm;
664 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
665 	unsigned long start = gtt->userptr;
666 	struct vm_area_struct *vma;
667 	struct mm_struct *mm;
668 	bool readonly;
669 	int r = 0;
670 
671 	mm = bo->notifier.mm;
672 	if (unlikely(!mm)) {
673 		DRM_DEBUG_DRIVER("BO is not registered?\n");
674 		return -EFAULT;
675 	}
676 
677 	/* Another get_user_pages is running at the same time?? */
678 	if (WARN_ON(gtt->range))
679 		return -EFAULT;
680 
681 	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
682 		return -ESRCH;
683 
684 	mmap_read_lock(mm);
685 	vma = vma_lookup(mm, start);
686 	if (unlikely(!vma)) {
687 		r = -EFAULT;
688 		goto out_unlock;
689 	}
690 	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
691 		vma->vm_file)) {
692 		r = -EPERM;
693 		goto out_unlock;
694 	}
695 
696 	readonly = amdgpu_ttm_tt_is_readonly(ttm);
697 	r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
698 				       ttm->num_pages, &gtt->range, readonly,
699 				       true, NULL);
700 out_unlock:
701 	mmap_read_unlock(mm);
702 	if (r)
703 		pr_debug("failed %d to get user pages 0x%lx\n", r, start);
704 
705 	mmput(mm);
706 
707 	return r;
708 }
709 
710 /*
711  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
712  * Check if the pages backing this ttm range have been invalidated
713  *
714  * Returns: true if pages are still valid
715  */
716 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
717 {
718 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
719 	bool r = false;
720 
721 	if (!gtt || !gtt->userptr)
722 		return false;
723 
724 	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
725 		gtt->userptr, ttm->num_pages);
726 
727 	WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
728 		"No user pages to check\n");
729 
730 	if (gtt->range) {
731 		/*
732 		 * FIXME: Must always hold notifier_lock for this, and must
733 		 * not ignore the return code.
734 		 */
735 		r = amdgpu_hmm_range_get_pages_done(gtt->range);
736 		gtt->range = NULL;
737 	}
738 
739 	return !r;
740 }
741 #endif
742 
743 /*
744  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
745  *
746  * Called by amdgpu_cs_list_validate(). This creates the page list
747  * that backs user memory and will ultimately be mapped into the device
748  * address space.
749  */
750 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
751 {
752 	unsigned long i;
753 
754 	for (i = 0; i < ttm->num_pages; ++i)
755 		ttm->pages[i] = pages ? pages[i] : NULL;
756 }
757 
758 /*
759  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
760  *
761  * Called by amdgpu_ttm_backend_bind()
762  **/
763 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
764 				     struct ttm_tt *ttm)
765 {
766 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
767 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
768 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
769 	enum dma_data_direction direction = write ?
770 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
771 	int r;
772 
773 	/* Allocate an SG array and squash pages into it */
774 	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
775 				      (u64)ttm->num_pages << PAGE_SHIFT,
776 				      GFP_KERNEL);
777 	if (r)
778 		goto release_sg;
779 
780 	/* Map SG to device */
781 	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
782 	if (r)
783 		goto release_sg;
784 
785 	/* convert SG to linear array of pages and dma addresses */
786 	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
787 				       ttm->num_pages);
788 
789 	return 0;
790 
791 release_sg:
792 	kfree(ttm->sg);
793 	ttm->sg = NULL;
794 	return r;
795 }
796 
797 /*
798  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
799  */
800 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
801 					struct ttm_tt *ttm)
802 {
803 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
804 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
805 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
806 	enum dma_data_direction direction = write ?
807 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
808 
809 	/* double check that we don't free the table twice */
810 	if (!ttm->sg || !ttm->sg->sgl)
811 		return;
812 
813 	/* unmap the pages mapped to the device */
814 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
815 	sg_free_table(ttm->sg);
816 
817 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
818 	if (gtt->range) {
819 		unsigned long i;
820 
821 		for (i = 0; i < ttm->num_pages; i++) {
822 			if (ttm->pages[i] !=
823 			    hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
824 				break;
825 		}
826 
827 		WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
828 	}
829 #endif
830 }
831 
832 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
833 				 struct ttm_buffer_object *tbo,
834 				 uint64_t flags)
835 {
836 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
837 	struct ttm_tt *ttm = tbo->ttm;
838 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
839 
840 	if (amdgpu_bo_encrypted(abo))
841 		flags |= AMDGPU_PTE_TMZ;
842 
843 	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
844 		uint64_t page_idx = 1;
845 
846 		amdgpu_gart_bind(adev, gtt->offset, page_idx,
847 				 gtt->ttm.dma_address, flags);
848 
849 		/* The memory type of the first page defaults to UC. Now
850 		 * modify the memory type to NC from the second page of
851 		 * the BO onward.
852 		 */
853 		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
854 		flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
855 
856 		amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT),
857 				 ttm->num_pages - page_idx,
858 				 &(gtt->ttm.dma_address[page_idx]), flags);
859 	} else {
860 		amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
861 				 gtt->ttm.dma_address, flags);
862 	}
863 }
864 
865 /*
866  * amdgpu_ttm_backend_bind - Bind GTT memory
867  *
868  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
869  * This handles binding GTT memory to the device address space.
870  */
871 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
872 				   struct ttm_tt *ttm,
873 				   struct ttm_resource *bo_mem)
874 {
875 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
876 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
877 	uint64_t flags;
878 	int r;
879 
880 	if (!bo_mem)
881 		return -EINVAL;
882 
883 	if (gtt->bound)
884 		return 0;
885 
886 	if (gtt->userptr) {
887 		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
888 		if (r) {
889 			DRM_ERROR("failed to pin userptr\n");
890 			return r;
891 		}
892 	} else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
893 		if (!ttm->sg) {
894 			struct dma_buf_attachment *attach;
895 			struct sg_table *sgt;
896 
897 			attach = gtt->gobj->import_attach;
898 			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
899 			if (IS_ERR(sgt))
900 				return PTR_ERR(sgt);
901 
902 			ttm->sg = sgt;
903 		}
904 
905 		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
906 					       ttm->num_pages);
907 	}
908 
909 	if (!ttm->num_pages) {
910 		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
911 		     ttm->num_pages, bo_mem, ttm);
912 	}
913 
914 	if (bo_mem->mem_type != TTM_PL_TT ||
915 	    !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
916 		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
917 		return 0;
918 	}
919 
920 	/* compute PTE flags relevant to this BO memory */
921 	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
922 
923 	/* bind pages into GART page tables */
924 	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
925 	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
926 			 gtt->ttm.dma_address, flags);
927 	gtt->bound = true;
928 	return 0;
929 }
930 
931 /*
932  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
933  * through AGP or GART aperture.
934  *
935  * If bo is accessible through AGP aperture, then use AGP aperture
936  * to access bo; otherwise allocate logical space in GART aperture
937  * and map bo to GART aperture.
938  */
939 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
940 {
941 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
942 	struct ttm_operation_ctx ctx = { false, false };
943 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
944 	struct ttm_placement placement;
945 	struct ttm_place placements;
946 	struct ttm_resource *tmp;
947 	uint64_t addr, flags;
948 	int r;
949 
950 	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
951 		return 0;
952 
953 	addr = amdgpu_gmc_agp_addr(bo);
954 	if (addr != AMDGPU_BO_INVALID_OFFSET) {
955 		bo->resource->start = addr >> PAGE_SHIFT;
956 		return 0;
957 	}
958 
959 	/* allocate GART space */
960 	placement.num_placement = 1;
961 	placement.placement = &placements;
962 	placement.num_busy_placement = 1;
963 	placement.busy_placement = &placements;
964 	placements.fpfn = 0;
965 	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
966 	placements.mem_type = TTM_PL_TT;
967 	placements.flags = bo->resource->placement;
968 
969 	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
970 	if (unlikely(r))
971 		return r;
972 
973 	/* compute PTE flags for this buffer object */
974 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
975 
976 	/* Bind pages */
977 	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
978 	amdgpu_ttm_gart_bind(adev, bo, flags);
979 	amdgpu_gart_invalidate_tlb(adev);
980 	ttm_resource_free(bo, &bo->resource);
981 	ttm_bo_assign_mem(bo, tmp);
982 
983 	return 0;
984 }
985 
986 /*
987  * amdgpu_ttm_recover_gart - Rebind GTT pages
988  *
989  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
990  * rebind GTT pages during a GPU reset.
991  */
992 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
993 {
994 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
995 	uint64_t flags;
996 
997 	if (!tbo->ttm)
998 		return;
999 
1000 	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1001 	amdgpu_ttm_gart_bind(adev, tbo, flags);
1002 }
1003 
1004 /*
1005  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1006  *
1007  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1008  * ttm_tt_destroy().
1009  */
1010 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1011 				      struct ttm_tt *ttm)
1012 {
1013 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1014 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1015 
1016 	/* if the pages have userptr pinning then clear that first */
1017 	if (gtt->userptr) {
1018 		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1019 	} else if (ttm->sg && gtt->gobj->import_attach) {
1020 		struct dma_buf_attachment *attach;
1021 
1022 		attach = gtt->gobj->import_attach;
1023 		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1024 		ttm->sg = NULL;
1025 	}
1026 
1027 	if (!gtt->bound)
1028 		return;
1029 
1030 	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1031 		return;
1032 
1033 	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1034 	amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1035 	gtt->bound = false;
1036 }
1037 
1038 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1039 				       struct ttm_tt *ttm)
1040 {
1041 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1042 
1043 	if (gtt->usertask)
1044 		put_task_struct(gtt->usertask);
1045 
1046 	ttm_tt_fini(&gtt->ttm);
1047 	kfree(gtt);
1048 }
1049 
1050 /**
1051  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1052  *
1053  * @bo: The buffer object to create a GTT ttm_tt object around
1054  * @page_flags: Page flags to be added to the ttm_tt object
1055  *
1056  * Called by ttm_tt_create().
1057  */
1058 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1059 					   uint32_t page_flags)
1060 {
1061 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1062 	struct amdgpu_ttm_tt *gtt;
1063 	enum ttm_caching caching;
1064 
1065 	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1066 	if (gtt == NULL) {
1067 		return NULL;
1068 	}
1069 	gtt->gobj = &bo->base;
1070 
1071 	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1072 		caching = ttm_write_combined;
1073 	else
1074 		caching = ttm_cached;
1075 
1076 	/* allocate space for the uninitialized page entries */
1077 	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1078 		kfree(gtt);
1079 		return NULL;
1080 	}
1081 	return &gtt->ttm;
1082 }
1083 
1084 /*
1085  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1086  *
1087  * Map the pages of a ttm_tt object to an address space visible
1088  * to the underlying device.
1089  */
1090 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1091 				  struct ttm_tt *ttm,
1092 				  struct ttm_operation_ctx *ctx)
1093 {
1094 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1095 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1096 	pgoff_t i;
1097 	int ret;
1098 
1099 	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1100 	if (gtt->userptr) {
1101 		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1102 		if (!ttm->sg)
1103 			return -ENOMEM;
1104 		return 0;
1105 	}
1106 
1107 	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1108 		return 0;
1109 
1110 	ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1111 	if (ret)
1112 		return ret;
1113 
1114 	for (i = 0; i < ttm->num_pages; ++i)
1115 		ttm->pages[i]->mapping = bdev->dev_mapping;
1116 
1117 	return 0;
1118 }
1119 
1120 /*
1121  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1122  *
1123  * Unmaps pages of a ttm_tt object from the device address space and
1124  * unpopulates the page array backing it.
1125  */
1126 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1127 				     struct ttm_tt *ttm)
1128 {
1129 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1130 	struct amdgpu_device *adev;
1131 	pgoff_t i;
1132 
1133 	amdgpu_ttm_backend_unbind(bdev, ttm);
1134 
1135 	if (gtt->userptr) {
1136 		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1137 		kfree(ttm->sg);
1138 		ttm->sg = NULL;
1139 		return;
1140 	}
1141 
1142 	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1143 		return;
1144 
1145 	for (i = 0; i < ttm->num_pages; ++i)
1146 		ttm->pages[i]->mapping = NULL;
1147 
1148 	adev = amdgpu_ttm_adev(bdev);
1149 	return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1150 }
1151 
1152 /**
1153  * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1154  * task
1155  *
1156  * @tbo: The ttm_buffer_object that contains the userptr
1157  * @user_addr:  The returned value
1158  */
1159 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1160 			      uint64_t *user_addr)
1161 {
1162 	struct amdgpu_ttm_tt *gtt;
1163 
1164 	if (!tbo->ttm)
1165 		return -EINVAL;
1166 
1167 	gtt = (void *)tbo->ttm;
1168 	*user_addr = gtt->userptr;
1169 	return 0;
1170 }
1171 
1172 /**
1173  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1174  * task
1175  *
1176  * @bo: The ttm_buffer_object to bind this userptr to
1177  * @addr:  The address in the current tasks VM space to use
1178  * @flags: Requirements of userptr object.
1179  *
1180  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1181  * to current task
1182  */
1183 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1184 			      uint64_t addr, uint32_t flags)
1185 {
1186 	struct amdgpu_ttm_tt *gtt;
1187 
1188 	if (!bo->ttm) {
1189 		/* TODO: We want a separate TTM object type for userptrs */
1190 		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1191 		if (bo->ttm == NULL)
1192 			return -ENOMEM;
1193 	}
1194 
1195 	/* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1196 	bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1197 
1198 	gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1199 	gtt->userptr = addr;
1200 	gtt->userflags = flags;
1201 
1202 	if (gtt->usertask)
1203 		put_task_struct(gtt->usertask);
1204 	gtt->usertask = current->group_leader;
1205 	get_task_struct(gtt->usertask);
1206 
1207 	return 0;
1208 }
1209 
1210 /*
1211  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1212  */
1213 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1214 {
1215 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1216 
1217 	if (gtt == NULL)
1218 		return NULL;
1219 
1220 	if (gtt->usertask == NULL)
1221 		return NULL;
1222 
1223 	return gtt->usertask->mm;
1224 }
1225 
1226 /*
1227  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1228  * address range for the current task.
1229  *
1230  */
1231 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1232 				  unsigned long end, unsigned long *userptr)
1233 {
1234 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1235 	unsigned long size;
1236 
1237 	if (gtt == NULL || !gtt->userptr)
1238 		return false;
1239 
1240 	/* Return false if no part of the ttm_tt object lies within
1241 	 * the range
1242 	 */
1243 	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1244 	if (gtt->userptr > end || gtt->userptr + size <= start)
1245 		return false;
1246 
1247 	if (userptr)
1248 		*userptr = gtt->userptr;
1249 	return true;
1250 }
1251 
1252 /*
1253  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1254  */
1255 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1256 {
1257 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1258 
1259 	if (gtt == NULL || !gtt->userptr)
1260 		return false;
1261 
1262 	return true;
1263 }
1264 
1265 /*
1266  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1267  */
1268 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1269 {
1270 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1271 
1272 	if (gtt == NULL)
1273 		return false;
1274 
1275 	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1276 }
1277 
1278 /**
1279  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1280  *
1281  * @ttm: The ttm_tt object to compute the flags for
1282  * @mem: The memory registry backing this ttm_tt object
1283  *
1284  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1285  */
1286 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1287 {
1288 	uint64_t flags = 0;
1289 
1290 	if (mem && mem->mem_type != TTM_PL_SYSTEM)
1291 		flags |= AMDGPU_PTE_VALID;
1292 
1293 	if (mem && (mem->mem_type == TTM_PL_TT ||
1294 		    mem->mem_type == AMDGPU_PL_PREEMPT)) {
1295 		flags |= AMDGPU_PTE_SYSTEM;
1296 
1297 		if (ttm->caching == ttm_cached)
1298 			flags |= AMDGPU_PTE_SNOOPED;
1299 	}
1300 
1301 	if (mem && mem->mem_type == TTM_PL_VRAM &&
1302 			mem->bus.caching == ttm_cached)
1303 		flags |= AMDGPU_PTE_SNOOPED;
1304 
1305 	return flags;
1306 }
1307 
1308 /**
1309  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1310  *
1311  * @adev: amdgpu_device pointer
1312  * @ttm: The ttm_tt object to compute the flags for
1313  * @mem: The memory registry backing this ttm_tt object
1314  *
1315  * Figure out the flags to use for a VM PTE (Page Table Entry).
1316  */
1317 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1318 				 struct ttm_resource *mem)
1319 {
1320 	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1321 
1322 	flags |= adev->gart.gart_pte_flags;
1323 	flags |= AMDGPU_PTE_READABLE;
1324 
1325 	if (!amdgpu_ttm_tt_is_readonly(ttm))
1326 		flags |= AMDGPU_PTE_WRITEABLE;
1327 
1328 	return flags;
1329 }
1330 
1331 /*
1332  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1333  * object.
1334  *
1335  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1336  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1337  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1338  * used to clean out a memory space.
1339  */
1340 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1341 					    const struct ttm_place *place)
1342 {
1343 	struct dma_resv_iter resv_cursor;
1344 	struct dma_fence *f;
1345 
1346 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1347 		return ttm_bo_eviction_valuable(bo, place);
1348 
1349 	/* Swapout? */
1350 	if (bo->resource->mem_type == TTM_PL_SYSTEM)
1351 		return true;
1352 
1353 	if (bo->type == ttm_bo_type_kernel &&
1354 	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1355 		return false;
1356 
1357 	/* If bo is a KFD BO, check if the bo belongs to the current process.
1358 	 * If true, then return false as any KFD process needs all its BOs to
1359 	 * be resident to run successfully
1360 	 */
1361 	dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1362 				DMA_RESV_USAGE_BOOKKEEP, f) {
1363 		if (amdkfd_fence_check_mm(f, current->mm))
1364 			return false;
1365 	}
1366 
1367 	/* Preemptible BOs don't own system resources managed by the
1368 	 * driver (pages, VRAM, GART space). They point to resources
1369 	 * owned by someone else (e.g. pageable memory in user mode
1370 	 * or a DMABuf). They are used in a preemptible context so we
1371 	 * can guarantee no deadlocks and good QoS in case of MMU
1372 	 * notifiers or DMABuf move notifiers from the resource owner.
1373 	 */
1374 	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1375 		return false;
1376 
1377 	if (bo->resource->mem_type == TTM_PL_TT &&
1378 	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1379 		return false;
1380 
1381 	return ttm_bo_eviction_valuable(bo, place);
1382 }
1383 
1384 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1385 				      void *buf, size_t size, bool write)
1386 {
1387 	while (size) {
1388 		uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1389 		uint64_t bytes = 4 - (pos & 0x3);
1390 		uint32_t shift = (pos & 0x3) * 8;
1391 		uint32_t mask = 0xffffffff << shift;
1392 		uint32_t value = 0;
1393 
1394 		if (size < bytes) {
1395 			mask &= 0xffffffff >> (bytes - size) * 8;
1396 			bytes = size;
1397 		}
1398 
1399 		if (mask != 0xffffffff) {
1400 			amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1401 			if (write) {
1402 				value &= ~mask;
1403 				value |= (*(uint32_t *)buf << shift) & mask;
1404 				amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1405 			} else {
1406 				value = (value & mask) >> shift;
1407 				memcpy(buf, &value, bytes);
1408 			}
1409 		} else {
1410 			amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1411 		}
1412 
1413 		pos += bytes;
1414 		buf += bytes;
1415 		size -= bytes;
1416 	}
1417 }
1418 
1419 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1420 					unsigned long offset, void *buf, int len, int write)
1421 {
1422 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1423 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1424 	struct amdgpu_res_cursor src_mm;
1425 	struct amdgpu_job *job;
1426 	struct dma_fence *fence;
1427 	uint64_t src_addr, dst_addr;
1428 	unsigned int num_dw;
1429 	int r, idx;
1430 
1431 	if (len != PAGE_SIZE)
1432 		return -EINVAL;
1433 
1434 	if (!adev->mman.sdma_access_ptr)
1435 		return -EACCES;
1436 
1437 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1438 		return -ENODEV;
1439 
1440 	if (write)
1441 		memcpy(adev->mman.sdma_access_ptr, buf, len);
1442 
1443 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1444 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job);
1445 	if (r)
1446 		goto out;
1447 
1448 	amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1449 	src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start;
1450 	dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1451 	if (write)
1452 		swap(src_addr, dst_addr);
1453 
1454 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, false);
1455 
1456 	amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1457 	WARN_ON(job->ibs[0].length_dw > num_dw);
1458 
1459 	r = amdgpu_job_submit(job, &adev->mman.entity, AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1460 	if (r) {
1461 		amdgpu_job_free(job);
1462 		goto out;
1463 	}
1464 
1465 	if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1466 		r = -ETIMEDOUT;
1467 	dma_fence_put(fence);
1468 
1469 	if (!(r || write))
1470 		memcpy(buf, adev->mman.sdma_access_ptr, len);
1471 out:
1472 	drm_dev_exit(idx);
1473 	return r;
1474 }
1475 
1476 /**
1477  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1478  *
1479  * @bo:  The buffer object to read/write
1480  * @offset:  Offset into buffer object
1481  * @buf:  Secondary buffer to write/read from
1482  * @len: Length in bytes of access
1483  * @write:  true if writing
1484  *
1485  * This is used to access VRAM that backs a buffer object via MMIO
1486  * access for debugging purposes.
1487  */
1488 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1489 				    unsigned long offset, void *buf, int len,
1490 				    int write)
1491 {
1492 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1493 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1494 	struct amdgpu_res_cursor cursor;
1495 	int ret = 0;
1496 
1497 	if (bo->resource->mem_type != TTM_PL_VRAM)
1498 		return -EIO;
1499 
1500 	if (amdgpu_device_has_timeouts_enabled(adev) &&
1501 			!amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1502 		return len;
1503 
1504 	amdgpu_res_first(bo->resource, offset, len, &cursor);
1505 	while (cursor.remaining) {
1506 		size_t count, size = cursor.size;
1507 		loff_t pos = cursor.start;
1508 
1509 		count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1510 		size -= count;
1511 		if (size) {
1512 			/* using MM to access rest vram and handle un-aligned address */
1513 			pos += count;
1514 			buf += count;
1515 			amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1516 		}
1517 
1518 		ret += cursor.size;
1519 		buf += cursor.size;
1520 		amdgpu_res_next(&cursor, cursor.size);
1521 	}
1522 
1523 	return ret;
1524 }
1525 
1526 static void
1527 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1528 {
1529 	amdgpu_bo_move_notify(bo, false, NULL);
1530 }
1531 
1532 static struct ttm_device_funcs amdgpu_bo_driver = {
1533 	.ttm_tt_create = &amdgpu_ttm_tt_create,
1534 	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
1535 	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1536 	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1537 	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1538 	.evict_flags = &amdgpu_evict_flags,
1539 	.move = &amdgpu_bo_move,
1540 	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1541 	.release_notify = &amdgpu_bo_release_notify,
1542 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1543 	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1544 	.access_memory = &amdgpu_ttm_access_memory,
1545 };
1546 
1547 /*
1548  * Firmware Reservation functions
1549  */
1550 /**
1551  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1552  *
1553  * @adev: amdgpu_device pointer
1554  *
1555  * free fw reserved vram if it has been reserved.
1556  */
1557 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1558 {
1559 	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1560 		NULL, &adev->mman.fw_vram_usage_va);
1561 }
1562 
1563 /**
1564  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1565  *
1566  * @adev: amdgpu_device pointer
1567  *
1568  * create bo vram reservation from fw.
1569  */
1570 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1571 {
1572 	uint64_t vram_size = adev->gmc.visible_vram_size;
1573 
1574 	adev->mman.fw_vram_usage_va = NULL;
1575 	adev->mman.fw_vram_usage_reserved_bo = NULL;
1576 
1577 	if (adev->mman.fw_vram_usage_size == 0 ||
1578 	    adev->mman.fw_vram_usage_size > vram_size)
1579 		return 0;
1580 
1581 	return amdgpu_bo_create_kernel_at(adev,
1582 					  adev->mman.fw_vram_usage_start_offset,
1583 					  adev->mman.fw_vram_usage_size,
1584 					  AMDGPU_GEM_DOMAIN_VRAM,
1585 					  &adev->mman.fw_vram_usage_reserved_bo,
1586 					  &adev->mman.fw_vram_usage_va);
1587 }
1588 
1589 /*
1590  * Memoy training reservation functions
1591  */
1592 
1593 /**
1594  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1595  *
1596  * @adev: amdgpu_device pointer
1597  *
1598  * free memory training reserved vram if it has been reserved.
1599  */
1600 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1601 {
1602 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1603 
1604 	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1605 	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1606 	ctx->c2p_bo = NULL;
1607 
1608 	return 0;
1609 }
1610 
1611 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1612 {
1613 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1614 
1615 	memset(ctx, 0, sizeof(*ctx));
1616 
1617 	ctx->c2p_train_data_offset =
1618 		ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1619 	ctx->p2c_train_data_offset =
1620 		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1621 	ctx->train_data_size =
1622 		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1623 
1624 	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1625 			ctx->train_data_size,
1626 			ctx->p2c_train_data_offset,
1627 			ctx->c2p_train_data_offset);
1628 }
1629 
1630 /*
1631  * reserve TMR memory at the top of VRAM which holds
1632  * IP Discovery data and is protected by PSP.
1633  */
1634 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1635 {
1636 	int ret;
1637 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1638 	bool mem_train_support = false;
1639 
1640 	if (!amdgpu_sriov_vf(adev)) {
1641 		if (amdgpu_atomfirmware_mem_training_supported(adev))
1642 			mem_train_support = true;
1643 		else
1644 			DRM_DEBUG("memory training does not support!\n");
1645 	}
1646 
1647 	/*
1648 	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1649 	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1650 	 *
1651 	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1652 	 * discovery data and G6 memory training data respectively
1653 	 */
1654 	adev->mman.discovery_tmr_size =
1655 		amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1656 	if (!adev->mman.discovery_tmr_size)
1657 		adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1658 
1659 	if (mem_train_support) {
1660 		/* reserve vram for mem train according to TMR location */
1661 		amdgpu_ttm_training_data_block_init(adev);
1662 		ret = amdgpu_bo_create_kernel_at(adev,
1663 					 ctx->c2p_train_data_offset,
1664 					 ctx->train_data_size,
1665 					 AMDGPU_GEM_DOMAIN_VRAM,
1666 					 &ctx->c2p_bo,
1667 					 NULL);
1668 		if (ret) {
1669 			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1670 			amdgpu_ttm_training_reserve_vram_fini(adev);
1671 			return ret;
1672 		}
1673 		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1674 	}
1675 
1676 	ret = amdgpu_bo_create_kernel_at(adev,
1677 				adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1678 				adev->mman.discovery_tmr_size,
1679 				AMDGPU_GEM_DOMAIN_VRAM,
1680 				&adev->mman.discovery_memory,
1681 				NULL);
1682 	if (ret) {
1683 		DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1684 		amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1685 		return ret;
1686 	}
1687 
1688 	return 0;
1689 }
1690 
1691 /*
1692  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1693  * gtt/vram related fields.
1694  *
1695  * This initializes all of the memory space pools that the TTM layer
1696  * will need such as the GTT space (system memory mapped to the device),
1697  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1698  * can be mapped per VMID.
1699  */
1700 int amdgpu_ttm_init(struct amdgpu_device *adev)
1701 {
1702 	uint64_t gtt_size;
1703 	int r;
1704 	u64 vis_vram_limit;
1705 
1706 	mutex_init(&adev->mman.gtt_window_lock);
1707 
1708 	/* No others user of address space so set it to 0 */
1709 	r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1710 			       adev_to_drm(adev)->anon_inode->i_mapping,
1711 			       adev_to_drm(adev)->vma_offset_manager,
1712 			       adev->need_swiotlb,
1713 			       dma_addressing_limited(adev->dev));
1714 	if (r) {
1715 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1716 		return r;
1717 	}
1718 	adev->mman.initialized = true;
1719 
1720 	/* Initialize VRAM pool with all of VRAM divided into pages */
1721 	r = amdgpu_vram_mgr_init(adev);
1722 	if (r) {
1723 		DRM_ERROR("Failed initializing VRAM heap.\n");
1724 		return r;
1725 	}
1726 
1727 	/* Reduce size of CPU-visible VRAM if requested */
1728 	vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1729 	if (amdgpu_vis_vram_limit > 0 &&
1730 	    vis_vram_limit <= adev->gmc.visible_vram_size)
1731 		adev->gmc.visible_vram_size = vis_vram_limit;
1732 
1733 	/* Change the size here instead of the init above so only lpfn is affected */
1734 	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1735 #ifdef CONFIG_64BIT
1736 #ifdef CONFIG_X86
1737 	if (adev->gmc.xgmi.connected_to_cpu)
1738 		adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1739 				adev->gmc.visible_vram_size);
1740 
1741 	else
1742 #endif
1743 		adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1744 				adev->gmc.visible_vram_size);
1745 #endif
1746 
1747 	/*
1748 	 *The reserved vram for firmware must be pinned to the specified
1749 	 *place on the VRAM, so reserve it early.
1750 	 */
1751 	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1752 	if (r) {
1753 		return r;
1754 	}
1755 
1756 	/*
1757 	 * only NAVI10 and onwards ASIC support for IP discovery.
1758 	 * If IP discovery enabled, a block of memory should be
1759 	 * reserved for IP discovey.
1760 	 */
1761 	if (adev->mman.discovery_bin) {
1762 		r = amdgpu_ttm_reserve_tmr(adev);
1763 		if (r)
1764 			return r;
1765 	}
1766 
1767 	/* allocate memory as required for VGA
1768 	 * This is used for VGA emulation and pre-OS scanout buffers to
1769 	 * avoid display artifacts while transitioning between pre-OS
1770 	 * and driver.  */
1771 	r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1772 				       AMDGPU_GEM_DOMAIN_VRAM,
1773 				       &adev->mman.stolen_vga_memory,
1774 				       NULL);
1775 	if (r)
1776 		return r;
1777 	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1778 				       adev->mman.stolen_extended_size,
1779 				       AMDGPU_GEM_DOMAIN_VRAM,
1780 				       &adev->mman.stolen_extended_memory,
1781 				       NULL);
1782 	if (r)
1783 		return r;
1784 	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1785 				       adev->mman.stolen_reserved_size,
1786 				       AMDGPU_GEM_DOMAIN_VRAM,
1787 				       &adev->mman.stolen_reserved_memory,
1788 				       NULL);
1789 	if (r)
1790 		return r;
1791 
1792 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1793 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1794 
1795 	/* Compute GTT size, either based on 1/2 the size of RAM size
1796 	 * or whatever the user passed on module init */
1797 	if (amdgpu_gtt_size == -1) {
1798 		struct sysinfo si;
1799 
1800 		si_meminfo(&si);
1801 		/* Certain GL unit tests for large textures can cause problems
1802 		 * with the OOM killer since there is no way to link this memory
1803 		 * to a process.  This was originally mitigated (but not necessarily
1804 		 * eliminated) by limiting the GTT size.  The problem is this limit
1805 		 * is often too low for many modern games so just make the limit 1/2
1806 		 * of system memory which aligns with TTM. The OOM accounting needs
1807 		 * to be addressed, but we shouldn't prevent common 3D applications
1808 		 * from being usable just to potentially mitigate that corner case.
1809 		 */
1810 		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1811 			       (u64)si.totalram * si.mem_unit / 2);
1812 	} else {
1813 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1814 	}
1815 
1816 	/* Initialize GTT memory pool */
1817 	r = amdgpu_gtt_mgr_init(adev, gtt_size);
1818 	if (r) {
1819 		DRM_ERROR("Failed initializing GTT heap.\n");
1820 		return r;
1821 	}
1822 	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1823 		 (unsigned)(gtt_size / (1024 * 1024)));
1824 
1825 	/* Initialize preemptible memory pool */
1826 	r = amdgpu_preempt_mgr_init(adev);
1827 	if (r) {
1828 		DRM_ERROR("Failed initializing PREEMPT heap.\n");
1829 		return r;
1830 	}
1831 
1832 	/* Initialize various on-chip memory pools */
1833 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1834 	if (r) {
1835 		DRM_ERROR("Failed initializing GDS heap.\n");
1836 		return r;
1837 	}
1838 
1839 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1840 	if (r) {
1841 		DRM_ERROR("Failed initializing gws heap.\n");
1842 		return r;
1843 	}
1844 
1845 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1846 	if (r) {
1847 		DRM_ERROR("Failed initializing oa heap.\n");
1848 		return r;
1849 	}
1850 
1851 	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1852 				AMDGPU_GEM_DOMAIN_GTT,
1853 				&adev->mman.sdma_access_bo, NULL,
1854 				&adev->mman.sdma_access_ptr))
1855 		DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1856 
1857 	return 0;
1858 }
1859 
1860 /*
1861  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1862  */
1863 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1864 {
1865 	int idx;
1866 	if (!adev->mman.initialized)
1867 		return;
1868 
1869 	amdgpu_ttm_training_reserve_vram_fini(adev);
1870 	/* return the stolen vga memory back to VRAM */
1871 	amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1872 	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1873 	/* return the IP Discovery TMR memory back to VRAM */
1874 	amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1875 	if (adev->mman.stolen_reserved_size)
1876 		amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1877 				      NULL, NULL);
1878 	amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
1879 					&adev->mman.sdma_access_ptr);
1880 	amdgpu_ttm_fw_reserve_vram_fini(adev);
1881 
1882 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1883 
1884 		if (adev->mman.aper_base_kaddr)
1885 			iounmap(adev->mman.aper_base_kaddr);
1886 		adev->mman.aper_base_kaddr = NULL;
1887 
1888 		drm_dev_exit(idx);
1889 	}
1890 
1891 	amdgpu_vram_mgr_fini(adev);
1892 	amdgpu_gtt_mgr_fini(adev);
1893 	amdgpu_preempt_mgr_fini(adev);
1894 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1895 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1896 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1897 	ttm_device_fini(&adev->mman.bdev);
1898 	adev->mman.initialized = false;
1899 	DRM_INFO("amdgpu: ttm finalized\n");
1900 }
1901 
1902 /**
1903  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1904  *
1905  * @adev: amdgpu_device pointer
1906  * @enable: true when we can use buffer functions.
1907  *
1908  * Enable/disable use of buffer functions during suspend/resume. This should
1909  * only be called at bootup or when userspace isn't running.
1910  */
1911 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1912 {
1913 	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1914 	uint64_t size;
1915 	int r;
1916 
1917 	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1918 	    adev->mman.buffer_funcs_enabled == enable)
1919 		return;
1920 
1921 	if (enable) {
1922 		struct amdgpu_ring *ring;
1923 		struct drm_gpu_scheduler *sched;
1924 
1925 		ring = adev->mman.buffer_funcs_ring;
1926 		sched = &ring->sched;
1927 		r = drm_sched_entity_init(&adev->mman.entity,
1928 					  DRM_SCHED_PRIORITY_KERNEL, &sched,
1929 					  1, NULL);
1930 		if (r) {
1931 			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1932 				  r);
1933 			return;
1934 		}
1935 	} else {
1936 		drm_sched_entity_destroy(&adev->mman.entity);
1937 		dma_fence_put(man->move);
1938 		man->move = NULL;
1939 	}
1940 
1941 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
1942 	if (enable)
1943 		size = adev->gmc.real_vram_size;
1944 	else
1945 		size = adev->gmc.visible_vram_size;
1946 	man->size = size;
1947 	adev->mman.buffer_funcs_enabled = enable;
1948 }
1949 
1950 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
1951 				  bool direct_submit,
1952 				  unsigned int num_dw,
1953 				  struct dma_resv *resv,
1954 				  bool vm_needs_flush,
1955 				  struct amdgpu_job **job)
1956 {
1957 	enum amdgpu_ib_pool_type pool = direct_submit ?
1958 		AMDGPU_IB_POOL_DIRECT :
1959 		AMDGPU_IB_POOL_DELAYED;
1960 	int r;
1961 
1962 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, job);
1963 	if (r)
1964 		return r;
1965 
1966 	if (vm_needs_flush) {
1967 		(*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1968 							adev->gmc.pdb0_bo :
1969 							adev->gart.bo);
1970 		(*job)->vm_needs_flush = true;
1971 	}
1972 	if (resv) {
1973 		r = amdgpu_sync_resv(adev, &(*job)->sync, resv,
1974 				     AMDGPU_SYNC_ALWAYS,
1975 				     AMDGPU_FENCE_OWNER_UNDEFINED);
1976 		if (r) {
1977 			DRM_ERROR("sync failed (%d).\n", r);
1978 			amdgpu_job_free(*job);
1979 			return r;
1980 		}
1981 	}
1982 	return 0;
1983 }
1984 
1985 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1986 		       uint64_t dst_offset, uint32_t byte_count,
1987 		       struct dma_resv *resv,
1988 		       struct dma_fence **fence, bool direct_submit,
1989 		       bool vm_needs_flush, bool tmz)
1990 {
1991 	struct amdgpu_device *adev = ring->adev;
1992 	unsigned num_loops, num_dw;
1993 	struct amdgpu_job *job;
1994 	uint32_t max_bytes;
1995 	unsigned i;
1996 	int r;
1997 
1998 	if (!direct_submit && !ring->sched.ready) {
1999 		DRM_ERROR("Trying to move memory with ring turned off.\n");
2000 		return -EINVAL;
2001 	}
2002 
2003 	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2004 	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2005 	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2006 	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2007 				   resv, vm_needs_flush, &job);
2008 	if (r)
2009 		return r;
2010 
2011 	for (i = 0; i < num_loops; i++) {
2012 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2013 
2014 		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2015 					dst_offset, cur_size_in_bytes, tmz);
2016 
2017 		src_offset += cur_size_in_bytes;
2018 		dst_offset += cur_size_in_bytes;
2019 		byte_count -= cur_size_in_bytes;
2020 	}
2021 
2022 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2023 	WARN_ON(job->ibs[0].length_dw > num_dw);
2024 	if (direct_submit)
2025 		r = amdgpu_job_submit_direct(job, ring, fence);
2026 	else
2027 		r = amdgpu_job_submit(job, &adev->mman.entity,
2028 				      AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2029 	if (r)
2030 		goto error_free;
2031 
2032 	return r;
2033 
2034 error_free:
2035 	amdgpu_job_free(job);
2036 	DRM_ERROR("Error scheduling IBs (%d)\n", r);
2037 	return r;
2038 }
2039 
2040 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2041 			       uint64_t dst_addr, uint32_t byte_count,
2042 			       struct dma_resv *resv,
2043 			       struct dma_fence **fence,
2044 			       bool vm_needs_flush)
2045 {
2046 	struct amdgpu_device *adev = ring->adev;
2047 	unsigned int num_loops, num_dw;
2048 	struct amdgpu_job *job;
2049 	uint32_t max_bytes;
2050 	unsigned int i;
2051 	int r;
2052 
2053 	max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2054 	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2055 	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2056 	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2057 				   &job);
2058 	if (r)
2059 		return r;
2060 
2061 	for (i = 0; i < num_loops; i++) {
2062 		uint32_t cur_size = min(byte_count, max_bytes);
2063 
2064 		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2065 					cur_size);
2066 
2067 		dst_addr += cur_size;
2068 		byte_count -= cur_size;
2069 	}
2070 
2071 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2072 	WARN_ON(job->ibs[0].length_dw > num_dw);
2073 	r = amdgpu_job_submit(job, &adev->mman.entity,
2074 			      AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2075 	if (r)
2076 		goto error_free;
2077 
2078 	return 0;
2079 
2080 error_free:
2081 	amdgpu_job_free(job);
2082 	return r;
2083 }
2084 
2085 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2086 			uint32_t src_data,
2087 			struct dma_resv *resv,
2088 			struct dma_fence **f)
2089 {
2090 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2091 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2092 	struct dma_fence *fence = NULL;
2093 	struct amdgpu_res_cursor dst;
2094 	int r;
2095 
2096 	if (!adev->mman.buffer_funcs_enabled) {
2097 		DRM_ERROR("Trying to clear memory with ring turned off.\n");
2098 		return -EINVAL;
2099 	}
2100 
2101 	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2102 
2103 	mutex_lock(&adev->mman.gtt_window_lock);
2104 	while (dst.remaining) {
2105 		struct dma_fence *next;
2106 		uint64_t cur_size, to;
2107 
2108 		/* Never fill more than 256MiB at once to avoid timeouts */
2109 		cur_size = min(dst.size, 256ULL << 20);
2110 
2111 		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2112 					  1, ring, false, &cur_size, &to);
2113 		if (r)
2114 			goto error;
2115 
2116 		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2117 					&next, true);
2118 		if (r)
2119 			goto error;
2120 
2121 		dma_fence_put(fence);
2122 		fence = next;
2123 
2124 		amdgpu_res_next(&dst, cur_size);
2125 	}
2126 error:
2127 	mutex_unlock(&adev->mman.gtt_window_lock);
2128 	if (f)
2129 		*f = dma_fence_get(fence);
2130 	dma_fence_put(fence);
2131 	return r;
2132 }
2133 
2134 /**
2135  * amdgpu_ttm_evict_resources - evict memory buffers
2136  * @adev: amdgpu device object
2137  * @mem_type: evicted BO's memory type
2138  *
2139  * Evicts all @mem_type buffers on the lru list of the memory type.
2140  *
2141  * Returns:
2142  * 0 for success or a negative error code on failure.
2143  */
2144 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2145 {
2146 	struct ttm_resource_manager *man;
2147 
2148 	switch (mem_type) {
2149 	case TTM_PL_VRAM:
2150 	case TTM_PL_TT:
2151 	case AMDGPU_PL_GWS:
2152 	case AMDGPU_PL_GDS:
2153 	case AMDGPU_PL_OA:
2154 		man = ttm_manager_type(&adev->mman.bdev, mem_type);
2155 		break;
2156 	default:
2157 		DRM_ERROR("Trying to evict invalid memory type\n");
2158 		return -EINVAL;
2159 	}
2160 
2161 	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2162 }
2163 
2164 #if defined(CONFIG_DEBUG_FS)
2165 
2166 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2167 {
2168 	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2169 
2170 	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2171 }
2172 
2173 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2174 
2175 /*
2176  * amdgpu_ttm_vram_read - Linear read access to VRAM
2177  *
2178  * Accesses VRAM via MMIO for debugging purposes.
2179  */
2180 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2181 				    size_t size, loff_t *pos)
2182 {
2183 	struct amdgpu_device *adev = file_inode(f)->i_private;
2184 	ssize_t result = 0;
2185 
2186 	if (size & 0x3 || *pos & 0x3)
2187 		return -EINVAL;
2188 
2189 	if (*pos >= adev->gmc.mc_vram_size)
2190 		return -ENXIO;
2191 
2192 	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2193 	while (size) {
2194 		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2195 		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2196 
2197 		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2198 		if (copy_to_user(buf, value, bytes))
2199 			return -EFAULT;
2200 
2201 		result += bytes;
2202 		buf += bytes;
2203 		*pos += bytes;
2204 		size -= bytes;
2205 	}
2206 
2207 	return result;
2208 }
2209 
2210 /*
2211  * amdgpu_ttm_vram_write - Linear write access to VRAM
2212  *
2213  * Accesses VRAM via MMIO for debugging purposes.
2214  */
2215 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2216 				    size_t size, loff_t *pos)
2217 {
2218 	struct amdgpu_device *adev = file_inode(f)->i_private;
2219 	ssize_t result = 0;
2220 	int r;
2221 
2222 	if (size & 0x3 || *pos & 0x3)
2223 		return -EINVAL;
2224 
2225 	if (*pos >= adev->gmc.mc_vram_size)
2226 		return -ENXIO;
2227 
2228 	while (size) {
2229 		uint32_t value;
2230 
2231 		if (*pos >= adev->gmc.mc_vram_size)
2232 			return result;
2233 
2234 		r = get_user(value, (uint32_t *)buf);
2235 		if (r)
2236 			return r;
2237 
2238 		amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2239 
2240 		result += 4;
2241 		buf += 4;
2242 		*pos += 4;
2243 		size -= 4;
2244 	}
2245 
2246 	return result;
2247 }
2248 
2249 static const struct file_operations amdgpu_ttm_vram_fops = {
2250 	.owner = THIS_MODULE,
2251 	.read = amdgpu_ttm_vram_read,
2252 	.write = amdgpu_ttm_vram_write,
2253 	.llseek = default_llseek,
2254 };
2255 
2256 /*
2257  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2258  *
2259  * This function is used to read memory that has been mapped to the
2260  * GPU and the known addresses are not physical addresses but instead
2261  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2262  */
2263 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2264 				 size_t size, loff_t *pos)
2265 {
2266 	struct amdgpu_device *adev = file_inode(f)->i_private;
2267 	struct iommu_domain *dom;
2268 	ssize_t result = 0;
2269 	int r;
2270 
2271 	/* retrieve the IOMMU domain if any for this device */
2272 	dom = iommu_get_domain_for_dev(adev->dev);
2273 
2274 	while (size) {
2275 		phys_addr_t addr = *pos & PAGE_MASK;
2276 		loff_t off = *pos & ~PAGE_MASK;
2277 		size_t bytes = PAGE_SIZE - off;
2278 		unsigned long pfn;
2279 		struct page *p;
2280 		void *ptr;
2281 
2282 		bytes = bytes < size ? bytes : size;
2283 
2284 		/* Translate the bus address to a physical address.  If
2285 		 * the domain is NULL it means there is no IOMMU active
2286 		 * and the address translation is the identity
2287 		 */
2288 		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2289 
2290 		pfn = addr >> PAGE_SHIFT;
2291 		if (!pfn_valid(pfn))
2292 			return -EPERM;
2293 
2294 		p = pfn_to_page(pfn);
2295 		if (p->mapping != adev->mman.bdev.dev_mapping)
2296 			return -EPERM;
2297 
2298 		ptr = kmap(p);
2299 		r = copy_to_user(buf, ptr + off, bytes);
2300 		kunmap(p);
2301 		if (r)
2302 			return -EFAULT;
2303 
2304 		size -= bytes;
2305 		*pos += bytes;
2306 		result += bytes;
2307 	}
2308 
2309 	return result;
2310 }
2311 
2312 /*
2313  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2314  *
2315  * This function is used to write memory that has been mapped to the
2316  * GPU and the known addresses are not physical addresses but instead
2317  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2318  */
2319 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2320 				 size_t size, loff_t *pos)
2321 {
2322 	struct amdgpu_device *adev = file_inode(f)->i_private;
2323 	struct iommu_domain *dom;
2324 	ssize_t result = 0;
2325 	int r;
2326 
2327 	dom = iommu_get_domain_for_dev(adev->dev);
2328 
2329 	while (size) {
2330 		phys_addr_t addr = *pos & PAGE_MASK;
2331 		loff_t off = *pos & ~PAGE_MASK;
2332 		size_t bytes = PAGE_SIZE - off;
2333 		unsigned long pfn;
2334 		struct page *p;
2335 		void *ptr;
2336 
2337 		bytes = bytes < size ? bytes : size;
2338 
2339 		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2340 
2341 		pfn = addr >> PAGE_SHIFT;
2342 		if (!pfn_valid(pfn))
2343 			return -EPERM;
2344 
2345 		p = pfn_to_page(pfn);
2346 		if (p->mapping != adev->mman.bdev.dev_mapping)
2347 			return -EPERM;
2348 
2349 		ptr = kmap(p);
2350 		r = copy_from_user(ptr + off, buf, bytes);
2351 		kunmap(p);
2352 		if (r)
2353 			return -EFAULT;
2354 
2355 		size -= bytes;
2356 		*pos += bytes;
2357 		result += bytes;
2358 	}
2359 
2360 	return result;
2361 }
2362 
2363 static const struct file_operations amdgpu_ttm_iomem_fops = {
2364 	.owner = THIS_MODULE,
2365 	.read = amdgpu_iomem_read,
2366 	.write = amdgpu_iomem_write,
2367 	.llseek = default_llseek
2368 };
2369 
2370 #endif
2371 
2372 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2373 {
2374 #if defined(CONFIG_DEBUG_FS)
2375 	struct drm_minor *minor = adev_to_drm(adev)->primary;
2376 	struct dentry *root = minor->debugfs_root;
2377 
2378 	debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2379 				 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2380 	debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2381 			    &amdgpu_ttm_iomem_fops);
2382 	debugfs_create_file("ttm_page_pool", 0444, root, adev,
2383 			    &amdgpu_ttm_page_pool_fops);
2384 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2385 							     TTM_PL_VRAM),
2386 					    root, "amdgpu_vram_mm");
2387 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2388 							     TTM_PL_TT),
2389 					    root, "amdgpu_gtt_mm");
2390 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2391 							     AMDGPU_PL_GDS),
2392 					    root, "amdgpu_gds_mm");
2393 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2394 							     AMDGPU_PL_GWS),
2395 					    root, "amdgpu_gws_mm");
2396 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2397 							     AMDGPU_PL_OA),
2398 					    root, "amdgpu_oa_mm");
2399 
2400 #endif
2401 }
2402