1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 #include <linux/module.h> 45 46 #include <drm/drm_drv.h> 47 #include <drm/ttm/ttm_bo_api.h> 48 #include <drm/ttm/ttm_bo_driver.h> 49 #include <drm/ttm/ttm_placement.h> 50 #include <drm/ttm/ttm_range_manager.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_drv.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "amdgpu_atomfirmware.h" 62 #include "amdgpu_res_cursor.h" 63 #include "bif/bif_4_1_d.h" 64 65 MODULE_IMPORT_NS(DMA_BUF); 66 67 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 68 69 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 70 struct ttm_tt *ttm, 71 struct ttm_resource *bo_mem); 72 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 73 struct ttm_tt *ttm); 74 75 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 76 unsigned int type, 77 uint64_t size_in_page) 78 { 79 return ttm_range_man_init(&adev->mman.bdev, type, 80 false, size_in_page); 81 } 82 83 /** 84 * amdgpu_evict_flags - Compute placement flags 85 * 86 * @bo: The buffer object to evict 87 * @placement: Possible destination(s) for evicted BO 88 * 89 * Fill in placement data when ttm_bo_evict() is called 90 */ 91 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 92 struct ttm_placement *placement) 93 { 94 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 95 struct amdgpu_bo *abo; 96 static const struct ttm_place placements = { 97 .fpfn = 0, 98 .lpfn = 0, 99 .mem_type = TTM_PL_SYSTEM, 100 .flags = 0 101 }; 102 103 /* Don't handle scatter gather BOs */ 104 if (bo->type == ttm_bo_type_sg) { 105 placement->num_placement = 0; 106 placement->num_busy_placement = 0; 107 return; 108 } 109 110 /* Object isn't an AMDGPU object so ignore */ 111 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 112 placement->placement = &placements; 113 placement->busy_placement = &placements; 114 placement->num_placement = 1; 115 placement->num_busy_placement = 1; 116 return; 117 } 118 119 abo = ttm_to_amdgpu_bo(bo); 120 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 121 placement->num_placement = 0; 122 placement->num_busy_placement = 0; 123 return; 124 } 125 126 switch (bo->resource->mem_type) { 127 case AMDGPU_PL_GDS: 128 case AMDGPU_PL_GWS: 129 case AMDGPU_PL_OA: 130 placement->num_placement = 0; 131 placement->num_busy_placement = 0; 132 return; 133 134 case TTM_PL_VRAM: 135 if (!adev->mman.buffer_funcs_enabled) { 136 /* Move to system memory */ 137 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 139 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 140 amdgpu_bo_in_cpu_visible_vram(abo)) { 141 142 /* Try evicting to the CPU inaccessible part of VRAM 143 * first, but only set GTT as busy placement, so this 144 * BO will be evicted to GTT rather than causing other 145 * BOs to be evicted from VRAM 146 */ 147 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 148 AMDGPU_GEM_DOMAIN_GTT | 149 AMDGPU_GEM_DOMAIN_CPU); 150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 151 abo->placements[0].lpfn = 0; 152 abo->placement.busy_placement = &abo->placements[1]; 153 abo->placement.num_busy_placement = 1; 154 } else { 155 /* Move to GTT memory */ 156 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 157 AMDGPU_GEM_DOMAIN_CPU); 158 } 159 break; 160 case TTM_PL_TT: 161 case AMDGPU_PL_PREEMPT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 /** 170 * amdgpu_ttm_map_buffer - Map memory into the GART windows 171 * @bo: buffer object to map 172 * @mem: memory object to map 173 * @mm_cur: range to map 174 * @num_pages: number of pages to map 175 * @window: which GART window to use 176 * @ring: DMA ring to use for the copy 177 * @tmz: if we should setup a TMZ enabled mapping 178 * @addr: resulting address inside the MC address space 179 * 180 * Setup one of the GART windows to access a specific piece of memory or return 181 * the physical address for local memory. 182 */ 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 184 struct ttm_resource *mem, 185 struct amdgpu_res_cursor *mm_cur, 186 unsigned num_pages, unsigned window, 187 struct amdgpu_ring *ring, bool tmz, 188 uint64_t *addr) 189 { 190 struct amdgpu_device *adev = ring->adev; 191 struct amdgpu_job *job; 192 unsigned num_dw, num_bytes; 193 struct dma_fence *fence; 194 uint64_t src_addr, dst_addr; 195 void *cpu_addr; 196 uint64_t flags; 197 unsigned int i; 198 int r; 199 200 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 201 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 202 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); 203 204 /* Map only what can't be accessed directly */ 205 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 206 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 207 mm_cur->start; 208 return 0; 209 } 210 211 *addr = adev->gmc.gart_start; 212 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 213 AMDGPU_GPU_PAGE_SIZE; 214 *addr += mm_cur->start & ~PAGE_MASK; 215 216 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 217 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 218 219 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 220 AMDGPU_IB_POOL_DELAYED, &job); 221 if (r) 222 return r; 223 224 src_addr = num_dw * 4; 225 src_addr += job->ibs[0].gpu_addr; 226 227 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 228 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 229 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 230 dst_addr, num_bytes, false); 231 232 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 233 WARN_ON(job->ibs[0].length_dw > num_dw); 234 235 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 236 if (tmz) 237 flags |= AMDGPU_PTE_TMZ; 238 239 cpu_addr = &job->ibs[0].ptr[num_dw]; 240 241 if (mem->mem_type == TTM_PL_TT) { 242 dma_addr_t *dma_addr; 243 244 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 245 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 246 } else { 247 dma_addr_t dma_address; 248 249 dma_address = mm_cur->start; 250 dma_address += adev->vm_manager.vram_base_offset; 251 252 for (i = 0; i < num_pages; ++i) { 253 amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address, 254 flags, cpu_addr); 255 dma_address += PAGE_SIZE; 256 } 257 } 258 259 r = amdgpu_job_submit(job, &adev->mman.entity, 260 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 261 if (r) 262 goto error_free; 263 264 dma_fence_put(fence); 265 266 return r; 267 268 error_free: 269 amdgpu_job_free(job); 270 return r; 271 } 272 273 /** 274 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 275 * @adev: amdgpu device 276 * @src: buffer/address where to read from 277 * @dst: buffer/address where to write to 278 * @size: number of bytes to copy 279 * @tmz: if a secure copy should be used 280 * @resv: resv object to sync to 281 * @f: Returns the last fence if multiple jobs are submitted. 282 * 283 * The function copies @size bytes from {src->mem + src->offset} to 284 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 285 * move and different for a BO to BO copy. 286 * 287 */ 288 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 289 const struct amdgpu_copy_mem *src, 290 const struct amdgpu_copy_mem *dst, 291 uint64_t size, bool tmz, 292 struct dma_resv *resv, 293 struct dma_fence **f) 294 { 295 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 296 AMDGPU_GPU_PAGE_SIZE); 297 298 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 299 struct amdgpu_res_cursor src_mm, dst_mm; 300 struct dma_fence *fence = NULL; 301 int r = 0; 302 303 if (!adev->mman.buffer_funcs_enabled) { 304 DRM_ERROR("Trying to move memory with ring turned off.\n"); 305 return -EINVAL; 306 } 307 308 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 309 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 310 311 mutex_lock(&adev->mman.gtt_window_lock); 312 while (src_mm.remaining) { 313 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 314 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 315 struct dma_fence *next; 316 uint32_t cur_size; 317 uint64_t from, to; 318 319 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 320 * begins at an offset, then adjust the size accordingly 321 */ 322 cur_size = max(src_page_offset, dst_page_offset); 323 cur_size = min(min3(src_mm.size, dst_mm.size, size), 324 (uint64_t)(GTT_MAX_BYTES - cur_size)); 325 326 /* Map src to window 0 and dst to window 1. */ 327 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 328 PFN_UP(cur_size + src_page_offset), 329 0, ring, tmz, &from); 330 if (r) 331 goto error; 332 333 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 334 PFN_UP(cur_size + dst_page_offset), 335 1, ring, tmz, &to); 336 if (r) 337 goto error; 338 339 r = amdgpu_copy_buffer(ring, from, to, cur_size, 340 resv, &next, false, true, tmz); 341 if (r) 342 goto error; 343 344 dma_fence_put(fence); 345 fence = next; 346 347 amdgpu_res_next(&src_mm, cur_size); 348 amdgpu_res_next(&dst_mm, cur_size); 349 } 350 error: 351 mutex_unlock(&adev->mman.gtt_window_lock); 352 if (f) 353 *f = dma_fence_get(fence); 354 dma_fence_put(fence); 355 return r; 356 } 357 358 /* 359 * amdgpu_move_blit - Copy an entire buffer to another buffer 360 * 361 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 362 * help move buffers to and from VRAM. 363 */ 364 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 365 bool evict, 366 struct ttm_resource *new_mem, 367 struct ttm_resource *old_mem) 368 { 369 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 370 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 371 struct amdgpu_copy_mem src, dst; 372 struct dma_fence *fence = NULL; 373 int r; 374 375 src.bo = bo; 376 dst.bo = bo; 377 src.mem = old_mem; 378 dst.mem = new_mem; 379 src.offset = 0; 380 dst.offset = 0; 381 382 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 383 new_mem->num_pages << PAGE_SHIFT, 384 amdgpu_bo_encrypted(abo), 385 bo->base.resv, &fence); 386 if (r) 387 goto error; 388 389 /* clear the space being freed */ 390 if (old_mem->mem_type == TTM_PL_VRAM && 391 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 392 struct dma_fence *wipe_fence = NULL; 393 394 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 395 NULL, &wipe_fence); 396 if (r) { 397 goto error; 398 } else if (wipe_fence) { 399 dma_fence_put(fence); 400 fence = wipe_fence; 401 } 402 } 403 404 /* Always block for VM page tables before committing the new location */ 405 if (bo->type == ttm_bo_type_kernel) 406 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 407 else 408 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 409 dma_fence_put(fence); 410 return r; 411 412 error: 413 if (fence) 414 dma_fence_wait(fence, false); 415 dma_fence_put(fence); 416 return r; 417 } 418 419 /* 420 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 421 * 422 * Called by amdgpu_bo_move() 423 */ 424 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 425 struct ttm_resource *mem) 426 { 427 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 428 struct amdgpu_res_cursor cursor; 429 430 if (mem->mem_type == TTM_PL_SYSTEM || 431 mem->mem_type == TTM_PL_TT) 432 return true; 433 if (mem->mem_type != TTM_PL_VRAM) 434 return false; 435 436 amdgpu_res_first(mem, 0, mem_size, &cursor); 437 438 /* ttm_resource_ioremap only supports contiguous memory */ 439 if (cursor.size != mem_size) 440 return false; 441 442 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 443 } 444 445 /* 446 * amdgpu_bo_move - Move a buffer object to a new memory location 447 * 448 * Called by ttm_bo_handle_move_mem() 449 */ 450 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 451 struct ttm_operation_ctx *ctx, 452 struct ttm_resource *new_mem, 453 struct ttm_place *hop) 454 { 455 struct amdgpu_device *adev; 456 struct amdgpu_bo *abo; 457 struct ttm_resource *old_mem = bo->resource; 458 int r; 459 460 if (new_mem->mem_type == TTM_PL_TT || 461 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 462 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 463 if (r) 464 return r; 465 } 466 467 /* Can't move a pinned BO */ 468 abo = ttm_to_amdgpu_bo(bo); 469 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 470 return -EINVAL; 471 472 adev = amdgpu_ttm_adev(bo->bdev); 473 474 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 475 ttm_bo_move_null(bo, new_mem); 476 goto out; 477 } 478 if (old_mem->mem_type == TTM_PL_SYSTEM && 479 (new_mem->mem_type == TTM_PL_TT || 480 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 481 ttm_bo_move_null(bo, new_mem); 482 goto out; 483 } 484 if ((old_mem->mem_type == TTM_PL_TT || 485 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 486 new_mem->mem_type == TTM_PL_SYSTEM) { 487 r = ttm_bo_wait_ctx(bo, ctx); 488 if (r) 489 return r; 490 491 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 492 ttm_resource_free(bo, &bo->resource); 493 ttm_bo_assign_mem(bo, new_mem); 494 goto out; 495 } 496 497 if (old_mem->mem_type == AMDGPU_PL_GDS || 498 old_mem->mem_type == AMDGPU_PL_GWS || 499 old_mem->mem_type == AMDGPU_PL_OA || 500 new_mem->mem_type == AMDGPU_PL_GDS || 501 new_mem->mem_type == AMDGPU_PL_GWS || 502 new_mem->mem_type == AMDGPU_PL_OA) { 503 /* Nothing to save here */ 504 ttm_bo_move_null(bo, new_mem); 505 goto out; 506 } 507 508 if (bo->type == ttm_bo_type_device && 509 new_mem->mem_type == TTM_PL_VRAM && 510 old_mem->mem_type != TTM_PL_VRAM) { 511 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 512 * accesses the BO after it's moved. 513 */ 514 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 515 } 516 517 if (adev->mman.buffer_funcs_enabled) { 518 if (((old_mem->mem_type == TTM_PL_SYSTEM && 519 new_mem->mem_type == TTM_PL_VRAM) || 520 (old_mem->mem_type == TTM_PL_VRAM && 521 new_mem->mem_type == TTM_PL_SYSTEM))) { 522 hop->fpfn = 0; 523 hop->lpfn = 0; 524 hop->mem_type = TTM_PL_TT; 525 hop->flags = TTM_PL_FLAG_TEMPORARY; 526 return -EMULTIHOP; 527 } 528 529 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 530 } else { 531 r = -ENODEV; 532 } 533 534 if (r) { 535 /* Check that all memory is CPU accessible */ 536 if (!amdgpu_mem_visible(adev, old_mem) || 537 !amdgpu_mem_visible(adev, new_mem)) { 538 pr_err("Move buffer fallback to memcpy unavailable\n"); 539 return r; 540 } 541 542 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 543 if (r) 544 return r; 545 } 546 547 out: 548 /* update statistics */ 549 atomic64_add(bo->base.size, &adev->num_bytes_moved); 550 amdgpu_bo_move_notify(bo, evict, new_mem); 551 return 0; 552 } 553 554 /* 555 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 556 * 557 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 558 */ 559 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 560 struct ttm_resource *mem) 561 { 562 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 563 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 564 565 switch (mem->mem_type) { 566 case TTM_PL_SYSTEM: 567 /* system memory */ 568 return 0; 569 case TTM_PL_TT: 570 case AMDGPU_PL_PREEMPT: 571 break; 572 case TTM_PL_VRAM: 573 mem->bus.offset = mem->start << PAGE_SHIFT; 574 /* check if it's visible */ 575 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 576 return -EINVAL; 577 578 if (adev->mman.aper_base_kaddr && 579 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 580 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 581 mem->bus.offset; 582 583 mem->bus.offset += adev->gmc.aper_base; 584 mem->bus.is_iomem = true; 585 break; 586 default: 587 return -EINVAL; 588 } 589 return 0; 590 } 591 592 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 593 unsigned long page_offset) 594 { 595 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 596 struct amdgpu_res_cursor cursor; 597 598 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 599 &cursor); 600 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 601 } 602 603 /** 604 * amdgpu_ttm_domain_start - Returns GPU start address 605 * @adev: amdgpu device object 606 * @type: type of the memory 607 * 608 * Returns: 609 * GPU start address of a memory domain 610 */ 611 612 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 613 { 614 switch (type) { 615 case TTM_PL_TT: 616 return adev->gmc.gart_start; 617 case TTM_PL_VRAM: 618 return adev->gmc.vram_start; 619 } 620 621 return 0; 622 } 623 624 /* 625 * TTM backend functions. 626 */ 627 struct amdgpu_ttm_tt { 628 struct ttm_tt ttm; 629 struct drm_gem_object *gobj; 630 u64 offset; 631 uint64_t userptr; 632 struct task_struct *usertask; 633 uint32_t userflags; 634 bool bound; 635 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 636 struct hmm_range *range; 637 #endif 638 }; 639 640 #ifdef CONFIG_DRM_AMDGPU_USERPTR 641 /* 642 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 643 * memory and start HMM tracking CPU page table update 644 * 645 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 646 * once afterwards to stop HMM tracking 647 */ 648 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 649 { 650 struct ttm_tt *ttm = bo->tbo.ttm; 651 struct amdgpu_ttm_tt *gtt = (void *)ttm; 652 unsigned long start = gtt->userptr; 653 struct vm_area_struct *vma; 654 struct mm_struct *mm; 655 bool readonly; 656 int r = 0; 657 658 mm = bo->notifier.mm; 659 if (unlikely(!mm)) { 660 DRM_DEBUG_DRIVER("BO is not registered?\n"); 661 return -EFAULT; 662 } 663 664 /* Another get_user_pages is running at the same time?? */ 665 if (WARN_ON(gtt->range)) 666 return -EFAULT; 667 668 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 669 return -ESRCH; 670 671 mmap_read_lock(mm); 672 vma = vma_lookup(mm, start); 673 if (unlikely(!vma)) { 674 r = -EFAULT; 675 goto out_unlock; 676 } 677 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 678 vma->vm_file)) { 679 r = -EPERM; 680 goto out_unlock; 681 } 682 683 readonly = amdgpu_ttm_tt_is_readonly(ttm); 684 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 685 ttm->num_pages, >t->range, readonly, 686 true, NULL); 687 out_unlock: 688 mmap_read_unlock(mm); 689 if (r) 690 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 691 692 mmput(mm); 693 694 return r; 695 } 696 697 /* 698 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 699 * Check if the pages backing this ttm range have been invalidated 700 * 701 * Returns: true if pages are still valid 702 */ 703 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 704 { 705 struct amdgpu_ttm_tt *gtt = (void *)ttm; 706 bool r = false; 707 708 if (!gtt || !gtt->userptr) 709 return false; 710 711 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 712 gtt->userptr, ttm->num_pages); 713 714 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 715 "No user pages to check\n"); 716 717 if (gtt->range) { 718 /* 719 * FIXME: Must always hold notifier_lock for this, and must 720 * not ignore the return code. 721 */ 722 r = amdgpu_hmm_range_get_pages_done(gtt->range); 723 gtt->range = NULL; 724 } 725 726 return !r; 727 } 728 #endif 729 730 /* 731 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 732 * 733 * Called by amdgpu_cs_list_validate(). This creates the page list 734 * that backs user memory and will ultimately be mapped into the device 735 * address space. 736 */ 737 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 738 { 739 unsigned long i; 740 741 for (i = 0; i < ttm->num_pages; ++i) 742 ttm->pages[i] = pages ? pages[i] : NULL; 743 } 744 745 /* 746 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 747 * 748 * Called by amdgpu_ttm_backend_bind() 749 **/ 750 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 751 struct ttm_tt *ttm) 752 { 753 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 754 struct amdgpu_ttm_tt *gtt = (void *)ttm; 755 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 756 enum dma_data_direction direction = write ? 757 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 758 int r; 759 760 /* Allocate an SG array and squash pages into it */ 761 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 762 (u64)ttm->num_pages << PAGE_SHIFT, 763 GFP_KERNEL); 764 if (r) 765 goto release_sg; 766 767 /* Map SG to device */ 768 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 769 if (r) 770 goto release_sg; 771 772 /* convert SG to linear array of pages and dma addresses */ 773 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 774 ttm->num_pages); 775 776 return 0; 777 778 release_sg: 779 kfree(ttm->sg); 780 ttm->sg = NULL; 781 return r; 782 } 783 784 /* 785 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 786 */ 787 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 788 struct ttm_tt *ttm) 789 { 790 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 791 struct amdgpu_ttm_tt *gtt = (void *)ttm; 792 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 793 enum dma_data_direction direction = write ? 794 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 795 796 /* double check that we don't free the table twice */ 797 if (!ttm->sg || !ttm->sg->sgl) 798 return; 799 800 /* unmap the pages mapped to the device */ 801 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 802 sg_free_table(ttm->sg); 803 804 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 805 if (gtt->range) { 806 unsigned long i; 807 808 for (i = 0; i < ttm->num_pages; i++) { 809 if (ttm->pages[i] != 810 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 811 break; 812 } 813 814 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 815 } 816 #endif 817 } 818 819 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 820 struct ttm_buffer_object *tbo, 821 uint64_t flags) 822 { 823 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 824 struct ttm_tt *ttm = tbo->ttm; 825 struct amdgpu_ttm_tt *gtt = (void *)ttm; 826 827 if (amdgpu_bo_encrypted(abo)) 828 flags |= AMDGPU_PTE_TMZ; 829 830 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 831 uint64_t page_idx = 1; 832 833 amdgpu_gart_bind(adev, gtt->offset, page_idx, 834 gtt->ttm.dma_address, flags); 835 836 /* The memory type of the first page defaults to UC. Now 837 * modify the memory type to NC from the second page of 838 * the BO onward. 839 */ 840 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 841 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 842 843 amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT), 844 ttm->num_pages - page_idx, 845 &(gtt->ttm.dma_address[page_idx]), flags); 846 } else { 847 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 848 gtt->ttm.dma_address, flags); 849 } 850 } 851 852 /* 853 * amdgpu_ttm_backend_bind - Bind GTT memory 854 * 855 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 856 * This handles binding GTT memory to the device address space. 857 */ 858 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 859 struct ttm_tt *ttm, 860 struct ttm_resource *bo_mem) 861 { 862 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 863 struct amdgpu_ttm_tt *gtt = (void*)ttm; 864 uint64_t flags; 865 int r; 866 867 if (!bo_mem) 868 return -EINVAL; 869 870 if (gtt->bound) 871 return 0; 872 873 if (gtt->userptr) { 874 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 875 if (r) { 876 DRM_ERROR("failed to pin userptr\n"); 877 return r; 878 } 879 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 880 if (!ttm->sg) { 881 struct dma_buf_attachment *attach; 882 struct sg_table *sgt; 883 884 attach = gtt->gobj->import_attach; 885 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 886 if (IS_ERR(sgt)) 887 return PTR_ERR(sgt); 888 889 ttm->sg = sgt; 890 } 891 892 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 893 ttm->num_pages); 894 } 895 896 if (!ttm->num_pages) { 897 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 898 ttm->num_pages, bo_mem, ttm); 899 } 900 901 if (bo_mem->mem_type != TTM_PL_TT || 902 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 903 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 904 return 0; 905 } 906 907 /* compute PTE flags relevant to this BO memory */ 908 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 909 910 /* bind pages into GART page tables */ 911 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 912 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 913 gtt->ttm.dma_address, flags); 914 gtt->bound = true; 915 return 0; 916 } 917 918 /* 919 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 920 * through AGP or GART aperture. 921 * 922 * If bo is accessible through AGP aperture, then use AGP aperture 923 * to access bo; otherwise allocate logical space in GART aperture 924 * and map bo to GART aperture. 925 */ 926 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 927 { 928 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 929 struct ttm_operation_ctx ctx = { false, false }; 930 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 931 struct ttm_placement placement; 932 struct ttm_place placements; 933 struct ttm_resource *tmp; 934 uint64_t addr, flags; 935 int r; 936 937 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 938 return 0; 939 940 addr = amdgpu_gmc_agp_addr(bo); 941 if (addr != AMDGPU_BO_INVALID_OFFSET) { 942 bo->resource->start = addr >> PAGE_SHIFT; 943 return 0; 944 } 945 946 /* allocate GART space */ 947 placement.num_placement = 1; 948 placement.placement = &placements; 949 placement.num_busy_placement = 1; 950 placement.busy_placement = &placements; 951 placements.fpfn = 0; 952 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 953 placements.mem_type = TTM_PL_TT; 954 placements.flags = bo->resource->placement; 955 956 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 957 if (unlikely(r)) 958 return r; 959 960 /* compute PTE flags for this buffer object */ 961 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 962 963 /* Bind pages */ 964 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 965 amdgpu_ttm_gart_bind(adev, bo, flags); 966 amdgpu_gart_invalidate_tlb(adev); 967 ttm_resource_free(bo, &bo->resource); 968 ttm_bo_assign_mem(bo, tmp); 969 970 return 0; 971 } 972 973 /* 974 * amdgpu_ttm_recover_gart - Rebind GTT pages 975 * 976 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 977 * rebind GTT pages during a GPU reset. 978 */ 979 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 980 { 981 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 982 uint64_t flags; 983 984 if (!tbo->ttm) 985 return; 986 987 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 988 amdgpu_ttm_gart_bind(adev, tbo, flags); 989 } 990 991 /* 992 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 993 * 994 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 995 * ttm_tt_destroy(). 996 */ 997 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 998 struct ttm_tt *ttm) 999 { 1000 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1001 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1002 1003 /* if the pages have userptr pinning then clear that first */ 1004 if (gtt->userptr) { 1005 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1006 } else if (ttm->sg && gtt->gobj->import_attach) { 1007 struct dma_buf_attachment *attach; 1008 1009 attach = gtt->gobj->import_attach; 1010 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1011 ttm->sg = NULL; 1012 } 1013 1014 if (!gtt->bound) 1015 return; 1016 1017 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1018 return; 1019 1020 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1021 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1022 gtt->bound = false; 1023 } 1024 1025 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1026 struct ttm_tt *ttm) 1027 { 1028 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1029 1030 if (gtt->usertask) 1031 put_task_struct(gtt->usertask); 1032 1033 ttm_tt_fini(>t->ttm); 1034 kfree(gtt); 1035 } 1036 1037 /** 1038 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1039 * 1040 * @bo: The buffer object to create a GTT ttm_tt object around 1041 * @page_flags: Page flags to be added to the ttm_tt object 1042 * 1043 * Called by ttm_tt_create(). 1044 */ 1045 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1046 uint32_t page_flags) 1047 { 1048 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1049 struct amdgpu_ttm_tt *gtt; 1050 enum ttm_caching caching; 1051 1052 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1053 if (gtt == NULL) { 1054 return NULL; 1055 } 1056 gtt->gobj = &bo->base; 1057 1058 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1059 caching = ttm_write_combined; 1060 else 1061 caching = ttm_cached; 1062 1063 /* allocate space for the uninitialized page entries */ 1064 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1065 kfree(gtt); 1066 return NULL; 1067 } 1068 return >t->ttm; 1069 } 1070 1071 /* 1072 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1073 * 1074 * Map the pages of a ttm_tt object to an address space visible 1075 * to the underlying device. 1076 */ 1077 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1078 struct ttm_tt *ttm, 1079 struct ttm_operation_ctx *ctx) 1080 { 1081 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1082 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1083 pgoff_t i; 1084 int ret; 1085 1086 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1087 if (gtt->userptr) { 1088 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1089 if (!ttm->sg) 1090 return -ENOMEM; 1091 return 0; 1092 } 1093 1094 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1095 return 0; 1096 1097 ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1098 if (ret) 1099 return ret; 1100 1101 for (i = 0; i < ttm->num_pages; ++i) 1102 ttm->pages[i]->mapping = bdev->dev_mapping; 1103 1104 return 0; 1105 } 1106 1107 /* 1108 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1109 * 1110 * Unmaps pages of a ttm_tt object from the device address space and 1111 * unpopulates the page array backing it. 1112 */ 1113 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1114 struct ttm_tt *ttm) 1115 { 1116 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1117 struct amdgpu_device *adev; 1118 pgoff_t i; 1119 1120 amdgpu_ttm_backend_unbind(bdev, ttm); 1121 1122 if (gtt->userptr) { 1123 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1124 kfree(ttm->sg); 1125 ttm->sg = NULL; 1126 return; 1127 } 1128 1129 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1130 return; 1131 1132 for (i = 0; i < ttm->num_pages; ++i) 1133 ttm->pages[i]->mapping = NULL; 1134 1135 adev = amdgpu_ttm_adev(bdev); 1136 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1137 } 1138 1139 /** 1140 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1141 * task 1142 * 1143 * @bo: The ttm_buffer_object to bind this userptr to 1144 * @addr: The address in the current tasks VM space to use 1145 * @flags: Requirements of userptr object. 1146 * 1147 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1148 * to current task 1149 */ 1150 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1151 uint64_t addr, uint32_t flags) 1152 { 1153 struct amdgpu_ttm_tt *gtt; 1154 1155 if (!bo->ttm) { 1156 /* TODO: We want a separate TTM object type for userptrs */ 1157 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1158 if (bo->ttm == NULL) 1159 return -ENOMEM; 1160 } 1161 1162 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1163 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1164 1165 gtt = (void *)bo->ttm; 1166 gtt->userptr = addr; 1167 gtt->userflags = flags; 1168 1169 if (gtt->usertask) 1170 put_task_struct(gtt->usertask); 1171 gtt->usertask = current->group_leader; 1172 get_task_struct(gtt->usertask); 1173 1174 return 0; 1175 } 1176 1177 /* 1178 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1179 */ 1180 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1181 { 1182 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1183 1184 if (gtt == NULL) 1185 return NULL; 1186 1187 if (gtt->usertask == NULL) 1188 return NULL; 1189 1190 return gtt->usertask->mm; 1191 } 1192 1193 /* 1194 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1195 * address range for the current task. 1196 * 1197 */ 1198 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1199 unsigned long end, unsigned long *userptr) 1200 { 1201 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1202 unsigned long size; 1203 1204 if (gtt == NULL || !gtt->userptr) 1205 return false; 1206 1207 /* Return false if no part of the ttm_tt object lies within 1208 * the range 1209 */ 1210 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1211 if (gtt->userptr > end || gtt->userptr + size <= start) 1212 return false; 1213 1214 if (userptr) 1215 *userptr = gtt->userptr; 1216 return true; 1217 } 1218 1219 /* 1220 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1221 */ 1222 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1223 { 1224 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1225 1226 if (gtt == NULL || !gtt->userptr) 1227 return false; 1228 1229 return true; 1230 } 1231 1232 /* 1233 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1234 */ 1235 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1236 { 1237 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1238 1239 if (gtt == NULL) 1240 return false; 1241 1242 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1243 } 1244 1245 /** 1246 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1247 * 1248 * @ttm: The ttm_tt object to compute the flags for 1249 * @mem: The memory registry backing this ttm_tt object 1250 * 1251 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1252 */ 1253 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1254 { 1255 uint64_t flags = 0; 1256 1257 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1258 flags |= AMDGPU_PTE_VALID; 1259 1260 if (mem && (mem->mem_type == TTM_PL_TT || 1261 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1262 flags |= AMDGPU_PTE_SYSTEM; 1263 1264 if (ttm->caching == ttm_cached) 1265 flags |= AMDGPU_PTE_SNOOPED; 1266 } 1267 1268 if (mem && mem->mem_type == TTM_PL_VRAM && 1269 mem->bus.caching == ttm_cached) 1270 flags |= AMDGPU_PTE_SNOOPED; 1271 1272 return flags; 1273 } 1274 1275 /** 1276 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1277 * 1278 * @adev: amdgpu_device pointer 1279 * @ttm: The ttm_tt object to compute the flags for 1280 * @mem: The memory registry backing this ttm_tt object 1281 * 1282 * Figure out the flags to use for a VM PTE (Page Table Entry). 1283 */ 1284 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1285 struct ttm_resource *mem) 1286 { 1287 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1288 1289 flags |= adev->gart.gart_pte_flags; 1290 flags |= AMDGPU_PTE_READABLE; 1291 1292 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1293 flags |= AMDGPU_PTE_WRITEABLE; 1294 1295 return flags; 1296 } 1297 1298 /* 1299 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1300 * object. 1301 * 1302 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1303 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1304 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1305 * used to clean out a memory space. 1306 */ 1307 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1308 const struct ttm_place *place) 1309 { 1310 unsigned long num_pages = bo->resource->num_pages; 1311 struct dma_resv_iter resv_cursor; 1312 struct amdgpu_res_cursor cursor; 1313 struct dma_fence *f; 1314 1315 /* Swapout? */ 1316 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1317 return true; 1318 1319 if (bo->type == ttm_bo_type_kernel && 1320 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1321 return false; 1322 1323 /* If bo is a KFD BO, check if the bo belongs to the current process. 1324 * If true, then return false as any KFD process needs all its BOs to 1325 * be resident to run successfully 1326 */ 1327 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, true, f) { 1328 if (amdkfd_fence_check_mm(f, current->mm)) 1329 return false; 1330 } 1331 1332 switch (bo->resource->mem_type) { 1333 case AMDGPU_PL_PREEMPT: 1334 /* Preemptible BOs don't own system resources managed by the 1335 * driver (pages, VRAM, GART space). They point to resources 1336 * owned by someone else (e.g. pageable memory in user mode 1337 * or a DMABuf). They are used in a preemptible context so we 1338 * can guarantee no deadlocks and good QoS in case of MMU 1339 * notifiers or DMABuf move notifiers from the resource owner. 1340 */ 1341 return false; 1342 case TTM_PL_TT: 1343 if (amdgpu_bo_is_amdgpu_bo(bo) && 1344 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1345 return false; 1346 return true; 1347 1348 case TTM_PL_VRAM: 1349 /* Check each drm MM node individually */ 1350 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1351 &cursor); 1352 while (cursor.remaining) { 1353 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1354 && !(place->lpfn && 1355 place->lpfn <= PFN_DOWN(cursor.start))) 1356 return true; 1357 1358 amdgpu_res_next(&cursor, cursor.size); 1359 } 1360 return false; 1361 1362 default: 1363 break; 1364 } 1365 1366 return ttm_bo_eviction_valuable(bo, place); 1367 } 1368 1369 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1370 void *buf, size_t size, bool write) 1371 { 1372 while (size) { 1373 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1374 uint64_t bytes = 4 - (pos & 0x3); 1375 uint32_t shift = (pos & 0x3) * 8; 1376 uint32_t mask = 0xffffffff << shift; 1377 uint32_t value = 0; 1378 1379 if (size < bytes) { 1380 mask &= 0xffffffff >> (bytes - size) * 8; 1381 bytes = size; 1382 } 1383 1384 if (mask != 0xffffffff) { 1385 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1386 if (write) { 1387 value &= ~mask; 1388 value |= (*(uint32_t *)buf << shift) & mask; 1389 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1390 } else { 1391 value = (value & mask) >> shift; 1392 memcpy(buf, &value, bytes); 1393 } 1394 } else { 1395 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1396 } 1397 1398 pos += bytes; 1399 buf += bytes; 1400 size -= bytes; 1401 } 1402 } 1403 1404 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1405 unsigned long offset, void *buf, int len, int write) 1406 { 1407 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1408 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1409 struct amdgpu_res_cursor src_mm; 1410 struct amdgpu_job *job; 1411 struct dma_fence *fence; 1412 uint64_t src_addr, dst_addr; 1413 unsigned int num_dw; 1414 int r, idx; 1415 1416 if (len != PAGE_SIZE) 1417 return -EINVAL; 1418 1419 if (!adev->mman.sdma_access_ptr) 1420 return -EACCES; 1421 1422 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1423 return -ENODEV; 1424 1425 if (write) 1426 memcpy(adev->mman.sdma_access_ptr, buf, len); 1427 1428 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1429 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job); 1430 if (r) 1431 goto out; 1432 1433 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1434 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start; 1435 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1436 if (write) 1437 swap(src_addr, dst_addr); 1438 1439 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, false); 1440 1441 amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); 1442 WARN_ON(job->ibs[0].length_dw > num_dw); 1443 1444 r = amdgpu_job_submit(job, &adev->mman.entity, AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 1445 if (r) { 1446 amdgpu_job_free(job); 1447 goto out; 1448 } 1449 1450 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1451 r = -ETIMEDOUT; 1452 dma_fence_put(fence); 1453 1454 if (!(r || write)) 1455 memcpy(buf, adev->mman.sdma_access_ptr, len); 1456 out: 1457 drm_dev_exit(idx); 1458 return r; 1459 } 1460 1461 /** 1462 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1463 * 1464 * @bo: The buffer object to read/write 1465 * @offset: Offset into buffer object 1466 * @buf: Secondary buffer to write/read from 1467 * @len: Length in bytes of access 1468 * @write: true if writing 1469 * 1470 * This is used to access VRAM that backs a buffer object via MMIO 1471 * access for debugging purposes. 1472 */ 1473 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1474 unsigned long offset, void *buf, int len, 1475 int write) 1476 { 1477 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1478 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1479 struct amdgpu_res_cursor cursor; 1480 int ret = 0; 1481 1482 if (bo->resource->mem_type != TTM_PL_VRAM) 1483 return -EIO; 1484 1485 if (amdgpu_device_has_timeouts_enabled(adev) && 1486 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1487 return len; 1488 1489 amdgpu_res_first(bo->resource, offset, len, &cursor); 1490 while (cursor.remaining) { 1491 size_t count, size = cursor.size; 1492 loff_t pos = cursor.start; 1493 1494 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1495 size -= count; 1496 if (size) { 1497 /* using MM to access rest vram and handle un-aligned address */ 1498 pos += count; 1499 buf += count; 1500 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1501 } 1502 1503 ret += cursor.size; 1504 buf += cursor.size; 1505 amdgpu_res_next(&cursor, cursor.size); 1506 } 1507 1508 return ret; 1509 } 1510 1511 static void 1512 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1513 { 1514 amdgpu_bo_move_notify(bo, false, NULL); 1515 } 1516 1517 static struct ttm_device_funcs amdgpu_bo_driver = { 1518 .ttm_tt_create = &amdgpu_ttm_tt_create, 1519 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1520 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1521 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1522 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1523 .evict_flags = &amdgpu_evict_flags, 1524 .move = &amdgpu_bo_move, 1525 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1526 .release_notify = &amdgpu_bo_release_notify, 1527 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1528 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1529 .access_memory = &amdgpu_ttm_access_memory, 1530 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1531 }; 1532 1533 /* 1534 * Firmware Reservation functions 1535 */ 1536 /** 1537 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1538 * 1539 * @adev: amdgpu_device pointer 1540 * 1541 * free fw reserved vram if it has been reserved. 1542 */ 1543 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1544 { 1545 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1546 NULL, &adev->mman.fw_vram_usage_va); 1547 } 1548 1549 /** 1550 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1551 * 1552 * @adev: amdgpu_device pointer 1553 * 1554 * create bo vram reservation from fw. 1555 */ 1556 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1557 { 1558 uint64_t vram_size = adev->gmc.visible_vram_size; 1559 1560 adev->mman.fw_vram_usage_va = NULL; 1561 adev->mman.fw_vram_usage_reserved_bo = NULL; 1562 1563 if (adev->mman.fw_vram_usage_size == 0 || 1564 adev->mman.fw_vram_usage_size > vram_size) 1565 return 0; 1566 1567 return amdgpu_bo_create_kernel_at(adev, 1568 adev->mman.fw_vram_usage_start_offset, 1569 adev->mman.fw_vram_usage_size, 1570 AMDGPU_GEM_DOMAIN_VRAM, 1571 &adev->mman.fw_vram_usage_reserved_bo, 1572 &adev->mman.fw_vram_usage_va); 1573 } 1574 1575 /* 1576 * Memoy training reservation functions 1577 */ 1578 1579 /** 1580 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1581 * 1582 * @adev: amdgpu_device pointer 1583 * 1584 * free memory training reserved vram if it has been reserved. 1585 */ 1586 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1587 { 1588 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1589 1590 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1591 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1592 ctx->c2p_bo = NULL; 1593 1594 return 0; 1595 } 1596 1597 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1598 { 1599 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1600 1601 memset(ctx, 0, sizeof(*ctx)); 1602 1603 ctx->c2p_train_data_offset = 1604 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1605 ctx->p2c_train_data_offset = 1606 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1607 ctx->train_data_size = 1608 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1609 1610 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1611 ctx->train_data_size, 1612 ctx->p2c_train_data_offset, 1613 ctx->c2p_train_data_offset); 1614 } 1615 1616 /* 1617 * reserve TMR memory at the top of VRAM which holds 1618 * IP Discovery data and is protected by PSP. 1619 */ 1620 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1621 { 1622 int ret; 1623 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1624 bool mem_train_support = false; 1625 1626 if (!amdgpu_sriov_vf(adev)) { 1627 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1628 mem_train_support = true; 1629 else 1630 DRM_DEBUG("memory training does not support!\n"); 1631 } 1632 1633 /* 1634 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1635 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1636 * 1637 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1638 * discovery data and G6 memory training data respectively 1639 */ 1640 adev->mman.discovery_tmr_size = 1641 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1642 if (!adev->mman.discovery_tmr_size) 1643 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1644 1645 if (mem_train_support) { 1646 /* reserve vram for mem train according to TMR location */ 1647 amdgpu_ttm_training_data_block_init(adev); 1648 ret = amdgpu_bo_create_kernel_at(adev, 1649 ctx->c2p_train_data_offset, 1650 ctx->train_data_size, 1651 AMDGPU_GEM_DOMAIN_VRAM, 1652 &ctx->c2p_bo, 1653 NULL); 1654 if (ret) { 1655 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1656 amdgpu_ttm_training_reserve_vram_fini(adev); 1657 return ret; 1658 } 1659 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1660 } 1661 1662 ret = amdgpu_bo_create_kernel_at(adev, 1663 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1664 adev->mman.discovery_tmr_size, 1665 AMDGPU_GEM_DOMAIN_VRAM, 1666 &adev->mman.discovery_memory, 1667 NULL); 1668 if (ret) { 1669 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1670 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1671 return ret; 1672 } 1673 1674 return 0; 1675 } 1676 1677 /* 1678 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1679 * gtt/vram related fields. 1680 * 1681 * This initializes all of the memory space pools that the TTM layer 1682 * will need such as the GTT space (system memory mapped to the device), 1683 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1684 * can be mapped per VMID. 1685 */ 1686 int amdgpu_ttm_init(struct amdgpu_device *adev) 1687 { 1688 uint64_t gtt_size; 1689 int r; 1690 u64 vis_vram_limit; 1691 1692 mutex_init(&adev->mman.gtt_window_lock); 1693 1694 /* No others user of address space so set it to 0 */ 1695 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1696 adev_to_drm(adev)->anon_inode->i_mapping, 1697 adev_to_drm(adev)->vma_offset_manager, 1698 adev->need_swiotlb, 1699 dma_addressing_limited(adev->dev)); 1700 if (r) { 1701 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1702 return r; 1703 } 1704 adev->mman.initialized = true; 1705 1706 /* Initialize VRAM pool with all of VRAM divided into pages */ 1707 r = amdgpu_vram_mgr_init(adev); 1708 if (r) { 1709 DRM_ERROR("Failed initializing VRAM heap.\n"); 1710 return r; 1711 } 1712 1713 /* Reduce size of CPU-visible VRAM if requested */ 1714 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1715 if (amdgpu_vis_vram_limit > 0 && 1716 vis_vram_limit <= adev->gmc.visible_vram_size) 1717 adev->gmc.visible_vram_size = vis_vram_limit; 1718 1719 /* Change the size here instead of the init above so only lpfn is affected */ 1720 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1721 #ifdef CONFIG_64BIT 1722 #ifdef CONFIG_X86 1723 if (adev->gmc.xgmi.connected_to_cpu) 1724 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1725 adev->gmc.visible_vram_size); 1726 1727 else 1728 #endif 1729 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1730 adev->gmc.visible_vram_size); 1731 #endif 1732 1733 /* 1734 *The reserved vram for firmware must be pinned to the specified 1735 *place on the VRAM, so reserve it early. 1736 */ 1737 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1738 if (r) { 1739 return r; 1740 } 1741 1742 /* 1743 * only NAVI10 and onwards ASIC support for IP discovery. 1744 * If IP discovery enabled, a block of memory should be 1745 * reserved for IP discovey. 1746 */ 1747 if (adev->mman.discovery_bin) { 1748 r = amdgpu_ttm_reserve_tmr(adev); 1749 if (r) 1750 return r; 1751 } 1752 1753 /* allocate memory as required for VGA 1754 * This is used for VGA emulation and pre-OS scanout buffers to 1755 * avoid display artifacts while transitioning between pre-OS 1756 * and driver. */ 1757 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1758 AMDGPU_GEM_DOMAIN_VRAM, 1759 &adev->mman.stolen_vga_memory, 1760 NULL); 1761 if (r) 1762 return r; 1763 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1764 adev->mman.stolen_extended_size, 1765 AMDGPU_GEM_DOMAIN_VRAM, 1766 &adev->mman.stolen_extended_memory, 1767 NULL); 1768 if (r) 1769 return r; 1770 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1771 adev->mman.stolen_reserved_size, 1772 AMDGPU_GEM_DOMAIN_VRAM, 1773 &adev->mman.stolen_reserved_memory, 1774 NULL); 1775 if (r) 1776 return r; 1777 1778 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1779 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1780 1781 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1782 * or whatever the user passed on module init */ 1783 if (amdgpu_gtt_size == -1) { 1784 struct sysinfo si; 1785 1786 si_meminfo(&si); 1787 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1788 adev->gmc.mc_vram_size), 1789 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1790 } 1791 else 1792 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1793 1794 /* Initialize GTT memory pool */ 1795 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1796 if (r) { 1797 DRM_ERROR("Failed initializing GTT heap.\n"); 1798 return r; 1799 } 1800 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1801 (unsigned)(gtt_size / (1024 * 1024))); 1802 1803 /* Initialize preemptible memory pool */ 1804 r = amdgpu_preempt_mgr_init(adev); 1805 if (r) { 1806 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1807 return r; 1808 } 1809 1810 /* Initialize various on-chip memory pools */ 1811 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1812 if (r) { 1813 DRM_ERROR("Failed initializing GDS heap.\n"); 1814 return r; 1815 } 1816 1817 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1818 if (r) { 1819 DRM_ERROR("Failed initializing gws heap.\n"); 1820 return r; 1821 } 1822 1823 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1824 if (r) { 1825 DRM_ERROR("Failed initializing oa heap.\n"); 1826 return r; 1827 } 1828 1829 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1830 AMDGPU_GEM_DOMAIN_GTT, 1831 &adev->mman.sdma_access_bo, NULL, 1832 &adev->mman.sdma_access_ptr)) 1833 DRM_WARN("Debug VRAM access will use slowpath MM access\n"); 1834 1835 return 0; 1836 } 1837 1838 /* 1839 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1840 */ 1841 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1842 { 1843 int idx; 1844 if (!adev->mman.initialized) 1845 return; 1846 1847 amdgpu_ttm_training_reserve_vram_fini(adev); 1848 /* return the stolen vga memory back to VRAM */ 1849 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1850 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1851 /* return the IP Discovery TMR memory back to VRAM */ 1852 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1853 if (adev->mman.stolen_reserved_size) 1854 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1855 NULL, NULL); 1856 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 1857 &adev->mman.sdma_access_ptr); 1858 amdgpu_ttm_fw_reserve_vram_fini(adev); 1859 1860 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1861 1862 if (adev->mman.aper_base_kaddr) 1863 iounmap(adev->mman.aper_base_kaddr); 1864 adev->mman.aper_base_kaddr = NULL; 1865 1866 drm_dev_exit(idx); 1867 } 1868 1869 amdgpu_vram_mgr_fini(adev); 1870 amdgpu_gtt_mgr_fini(adev); 1871 amdgpu_preempt_mgr_fini(adev); 1872 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1873 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1874 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1875 ttm_device_fini(&adev->mman.bdev); 1876 adev->mman.initialized = false; 1877 DRM_INFO("amdgpu: ttm finalized\n"); 1878 } 1879 1880 /** 1881 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1882 * 1883 * @adev: amdgpu_device pointer 1884 * @enable: true when we can use buffer functions. 1885 * 1886 * Enable/disable use of buffer functions during suspend/resume. This should 1887 * only be called at bootup or when userspace isn't running. 1888 */ 1889 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1890 { 1891 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1892 uint64_t size; 1893 int r; 1894 1895 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1896 adev->mman.buffer_funcs_enabled == enable) 1897 return; 1898 1899 if (enable) { 1900 struct amdgpu_ring *ring; 1901 struct drm_gpu_scheduler *sched; 1902 1903 ring = adev->mman.buffer_funcs_ring; 1904 sched = &ring->sched; 1905 r = drm_sched_entity_init(&adev->mman.entity, 1906 DRM_SCHED_PRIORITY_KERNEL, &sched, 1907 1, NULL); 1908 if (r) { 1909 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1910 r); 1911 return; 1912 } 1913 } else { 1914 drm_sched_entity_destroy(&adev->mman.entity); 1915 dma_fence_put(man->move); 1916 man->move = NULL; 1917 } 1918 1919 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1920 if (enable) 1921 size = adev->gmc.real_vram_size; 1922 else 1923 size = adev->gmc.visible_vram_size; 1924 man->size = size >> PAGE_SHIFT; 1925 adev->mman.buffer_funcs_enabled = enable; 1926 } 1927 1928 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1929 uint64_t dst_offset, uint32_t byte_count, 1930 struct dma_resv *resv, 1931 struct dma_fence **fence, bool direct_submit, 1932 bool vm_needs_flush, bool tmz) 1933 { 1934 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1935 AMDGPU_IB_POOL_DELAYED; 1936 struct amdgpu_device *adev = ring->adev; 1937 struct amdgpu_job *job; 1938 1939 uint32_t max_bytes; 1940 unsigned num_loops, num_dw; 1941 unsigned i; 1942 int r; 1943 1944 if (direct_submit && !ring->sched.ready) { 1945 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1946 return -EINVAL; 1947 } 1948 1949 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1950 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1951 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1952 1953 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1954 if (r) 1955 return r; 1956 1957 if (vm_needs_flush) { 1958 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1959 adev->gmc.pdb0_bo : adev->gart.bo); 1960 job->vm_needs_flush = true; 1961 } 1962 if (resv) { 1963 r = amdgpu_sync_resv(adev, &job->sync, resv, 1964 AMDGPU_SYNC_ALWAYS, 1965 AMDGPU_FENCE_OWNER_UNDEFINED); 1966 if (r) { 1967 DRM_ERROR("sync failed (%d).\n", r); 1968 goto error_free; 1969 } 1970 } 1971 1972 for (i = 0; i < num_loops; i++) { 1973 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1974 1975 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1976 dst_offset, cur_size_in_bytes, tmz); 1977 1978 src_offset += cur_size_in_bytes; 1979 dst_offset += cur_size_in_bytes; 1980 byte_count -= cur_size_in_bytes; 1981 } 1982 1983 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1984 WARN_ON(job->ibs[0].length_dw > num_dw); 1985 if (direct_submit) 1986 r = amdgpu_job_submit_direct(job, ring, fence); 1987 else 1988 r = amdgpu_job_submit(job, &adev->mman.entity, 1989 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1990 if (r) 1991 goto error_free; 1992 1993 return r; 1994 1995 error_free: 1996 amdgpu_job_free(job); 1997 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1998 return r; 1999 } 2000 2001 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2002 uint32_t src_data, 2003 struct dma_resv *resv, 2004 struct dma_fence **fence) 2005 { 2006 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2007 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2008 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2009 2010 struct amdgpu_res_cursor cursor; 2011 unsigned int num_loops, num_dw; 2012 uint64_t num_bytes; 2013 2014 struct amdgpu_job *job; 2015 int r; 2016 2017 if (!adev->mman.buffer_funcs_enabled) { 2018 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2019 return -EINVAL; 2020 } 2021 2022 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) { 2023 DRM_ERROR("Trying to clear preemptible memory.\n"); 2024 return -EINVAL; 2025 } 2026 2027 if (bo->tbo.resource->mem_type == TTM_PL_TT) { 2028 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2029 if (r) 2030 return r; 2031 } 2032 2033 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; 2034 num_loops = 0; 2035 2036 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2037 while (cursor.remaining) { 2038 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 2039 amdgpu_res_next(&cursor, cursor.size); 2040 } 2041 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2042 2043 /* for IB padding */ 2044 num_dw += 64; 2045 2046 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2047 &job); 2048 if (r) 2049 return r; 2050 2051 if (resv) { 2052 r = amdgpu_sync_resv(adev, &job->sync, resv, 2053 AMDGPU_SYNC_ALWAYS, 2054 AMDGPU_FENCE_OWNER_UNDEFINED); 2055 if (r) { 2056 DRM_ERROR("sync failed (%d).\n", r); 2057 goto error_free; 2058 } 2059 } 2060 2061 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2062 while (cursor.remaining) { 2063 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2064 uint64_t dst_addr = cursor.start; 2065 2066 dst_addr += amdgpu_ttm_domain_start(adev, 2067 bo->tbo.resource->mem_type); 2068 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2069 cur_size); 2070 2071 amdgpu_res_next(&cursor, cur_size); 2072 } 2073 2074 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2075 WARN_ON(job->ibs[0].length_dw > num_dw); 2076 r = amdgpu_job_submit(job, &adev->mman.entity, 2077 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2078 if (r) 2079 goto error_free; 2080 2081 return 0; 2082 2083 error_free: 2084 amdgpu_job_free(job); 2085 return r; 2086 } 2087 2088 /** 2089 * amdgpu_ttm_evict_resources - evict memory buffers 2090 * @adev: amdgpu device object 2091 * @mem_type: evicted BO's memory type 2092 * 2093 * Evicts all @mem_type buffers on the lru list of the memory type. 2094 * 2095 * Returns: 2096 * 0 for success or a negative error code on failure. 2097 */ 2098 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2099 { 2100 struct ttm_resource_manager *man; 2101 2102 switch (mem_type) { 2103 case TTM_PL_VRAM: 2104 case TTM_PL_TT: 2105 case AMDGPU_PL_GWS: 2106 case AMDGPU_PL_GDS: 2107 case AMDGPU_PL_OA: 2108 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2109 break; 2110 default: 2111 DRM_ERROR("Trying to evict invalid memory type\n"); 2112 return -EINVAL; 2113 } 2114 2115 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2116 } 2117 2118 #if defined(CONFIG_DEBUG_FS) 2119 2120 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2121 { 2122 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2123 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2124 TTM_PL_VRAM); 2125 struct drm_printer p = drm_seq_file_printer(m); 2126 2127 man->func->debug(man, &p); 2128 return 0; 2129 } 2130 2131 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2132 { 2133 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2134 2135 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2136 } 2137 2138 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2139 { 2140 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2141 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2142 TTM_PL_TT); 2143 struct drm_printer p = drm_seq_file_printer(m); 2144 2145 man->func->debug(man, &p); 2146 return 0; 2147 } 2148 2149 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2150 { 2151 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2152 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2153 AMDGPU_PL_GDS); 2154 struct drm_printer p = drm_seq_file_printer(m); 2155 2156 man->func->debug(man, &p); 2157 return 0; 2158 } 2159 2160 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2161 { 2162 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2163 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2164 AMDGPU_PL_GWS); 2165 struct drm_printer p = drm_seq_file_printer(m); 2166 2167 man->func->debug(man, &p); 2168 return 0; 2169 } 2170 2171 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2172 { 2173 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2174 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2175 AMDGPU_PL_OA); 2176 struct drm_printer p = drm_seq_file_printer(m); 2177 2178 man->func->debug(man, &p); 2179 return 0; 2180 } 2181 2182 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2183 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2184 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2185 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2186 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2187 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2188 2189 /* 2190 * amdgpu_ttm_vram_read - Linear read access to VRAM 2191 * 2192 * Accesses VRAM via MMIO for debugging purposes. 2193 */ 2194 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2195 size_t size, loff_t *pos) 2196 { 2197 struct amdgpu_device *adev = file_inode(f)->i_private; 2198 ssize_t result = 0; 2199 2200 if (size & 0x3 || *pos & 0x3) 2201 return -EINVAL; 2202 2203 if (*pos >= adev->gmc.mc_vram_size) 2204 return -ENXIO; 2205 2206 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2207 while (size) { 2208 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2209 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2210 2211 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2212 if (copy_to_user(buf, value, bytes)) 2213 return -EFAULT; 2214 2215 result += bytes; 2216 buf += bytes; 2217 *pos += bytes; 2218 size -= bytes; 2219 } 2220 2221 return result; 2222 } 2223 2224 /* 2225 * amdgpu_ttm_vram_write - Linear write access to VRAM 2226 * 2227 * Accesses VRAM via MMIO for debugging purposes. 2228 */ 2229 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2230 size_t size, loff_t *pos) 2231 { 2232 struct amdgpu_device *adev = file_inode(f)->i_private; 2233 ssize_t result = 0; 2234 int r; 2235 2236 if (size & 0x3 || *pos & 0x3) 2237 return -EINVAL; 2238 2239 if (*pos >= adev->gmc.mc_vram_size) 2240 return -ENXIO; 2241 2242 while (size) { 2243 uint32_t value; 2244 2245 if (*pos >= adev->gmc.mc_vram_size) 2246 return result; 2247 2248 r = get_user(value, (uint32_t *)buf); 2249 if (r) 2250 return r; 2251 2252 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2253 2254 result += 4; 2255 buf += 4; 2256 *pos += 4; 2257 size -= 4; 2258 } 2259 2260 return result; 2261 } 2262 2263 static const struct file_operations amdgpu_ttm_vram_fops = { 2264 .owner = THIS_MODULE, 2265 .read = amdgpu_ttm_vram_read, 2266 .write = amdgpu_ttm_vram_write, 2267 .llseek = default_llseek, 2268 }; 2269 2270 /* 2271 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2272 * 2273 * This function is used to read memory that has been mapped to the 2274 * GPU and the known addresses are not physical addresses but instead 2275 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2276 */ 2277 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2278 size_t size, loff_t *pos) 2279 { 2280 struct amdgpu_device *adev = file_inode(f)->i_private; 2281 struct iommu_domain *dom; 2282 ssize_t result = 0; 2283 int r; 2284 2285 /* retrieve the IOMMU domain if any for this device */ 2286 dom = iommu_get_domain_for_dev(adev->dev); 2287 2288 while (size) { 2289 phys_addr_t addr = *pos & PAGE_MASK; 2290 loff_t off = *pos & ~PAGE_MASK; 2291 size_t bytes = PAGE_SIZE - off; 2292 unsigned long pfn; 2293 struct page *p; 2294 void *ptr; 2295 2296 bytes = bytes < size ? bytes : size; 2297 2298 /* Translate the bus address to a physical address. If 2299 * the domain is NULL it means there is no IOMMU active 2300 * and the address translation is the identity 2301 */ 2302 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2303 2304 pfn = addr >> PAGE_SHIFT; 2305 if (!pfn_valid(pfn)) 2306 return -EPERM; 2307 2308 p = pfn_to_page(pfn); 2309 if (p->mapping != adev->mman.bdev.dev_mapping) 2310 return -EPERM; 2311 2312 ptr = kmap(p); 2313 r = copy_to_user(buf, ptr + off, bytes); 2314 kunmap(p); 2315 if (r) 2316 return -EFAULT; 2317 2318 size -= bytes; 2319 *pos += bytes; 2320 result += bytes; 2321 } 2322 2323 return result; 2324 } 2325 2326 /* 2327 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2328 * 2329 * This function is used to write memory that has been mapped to the 2330 * GPU and the known addresses are not physical addresses but instead 2331 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2332 */ 2333 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2334 size_t size, loff_t *pos) 2335 { 2336 struct amdgpu_device *adev = file_inode(f)->i_private; 2337 struct iommu_domain *dom; 2338 ssize_t result = 0; 2339 int r; 2340 2341 dom = iommu_get_domain_for_dev(adev->dev); 2342 2343 while (size) { 2344 phys_addr_t addr = *pos & PAGE_MASK; 2345 loff_t off = *pos & ~PAGE_MASK; 2346 size_t bytes = PAGE_SIZE - off; 2347 unsigned long pfn; 2348 struct page *p; 2349 void *ptr; 2350 2351 bytes = bytes < size ? bytes : size; 2352 2353 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2354 2355 pfn = addr >> PAGE_SHIFT; 2356 if (!pfn_valid(pfn)) 2357 return -EPERM; 2358 2359 p = pfn_to_page(pfn); 2360 if (p->mapping != adev->mman.bdev.dev_mapping) 2361 return -EPERM; 2362 2363 ptr = kmap(p); 2364 r = copy_from_user(ptr + off, buf, bytes); 2365 kunmap(p); 2366 if (r) 2367 return -EFAULT; 2368 2369 size -= bytes; 2370 *pos += bytes; 2371 result += bytes; 2372 } 2373 2374 return result; 2375 } 2376 2377 static const struct file_operations amdgpu_ttm_iomem_fops = { 2378 .owner = THIS_MODULE, 2379 .read = amdgpu_iomem_read, 2380 .write = amdgpu_iomem_write, 2381 .llseek = default_llseek 2382 }; 2383 2384 #endif 2385 2386 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2387 { 2388 #if defined(CONFIG_DEBUG_FS) 2389 struct drm_minor *minor = adev_to_drm(adev)->primary; 2390 struct dentry *root = minor->debugfs_root; 2391 2392 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2393 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2394 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2395 &amdgpu_ttm_iomem_fops); 2396 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2397 &amdgpu_mm_vram_table_fops); 2398 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2399 &amdgpu_mm_tt_table_fops); 2400 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2401 &amdgpu_mm_gds_table_fops); 2402 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2403 &amdgpu_mm_gws_table_fops); 2404 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2405 &amdgpu_mm_oa_table_fops); 2406 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2407 &amdgpu_ttm_page_pool_fops); 2408 #endif 2409 } 2410