1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 50 #include <drm/amdgpu_drm.h> 51 52 #include "amdgpu.h" 53 #include "amdgpu_object.h" 54 #include "amdgpu_trace.h" 55 #include "amdgpu_amdkfd.h" 56 #include "amdgpu_sdma.h" 57 #include "amdgpu_ras.h" 58 #include "amdgpu_atomfirmware.h" 59 #include "amdgpu_res_cursor.h" 60 #include "bif/bif_4_1_d.h" 61 62 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 63 64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 65 struct ttm_tt *ttm, 66 struct ttm_resource *bo_mem); 67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 68 struct ttm_tt *ttm); 69 70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 71 unsigned int type, 72 uint64_t size_in_page) 73 { 74 return ttm_range_man_init(&adev->mman.bdev, type, 75 false, size_in_page); 76 } 77 78 /** 79 * amdgpu_evict_flags - Compute placement flags 80 * 81 * @bo: The buffer object to evict 82 * @placement: Possible destination(s) for evicted BO 83 * 84 * Fill in placement data when ttm_bo_evict() is called 85 */ 86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 87 struct ttm_placement *placement) 88 { 89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 90 struct amdgpu_bo *abo; 91 static const struct ttm_place placements = { 92 .fpfn = 0, 93 .lpfn = 0, 94 .mem_type = TTM_PL_SYSTEM, 95 .flags = 0 96 }; 97 98 /* Don't handle scatter gather BOs */ 99 if (bo->type == ttm_bo_type_sg) { 100 placement->num_placement = 0; 101 placement->num_busy_placement = 0; 102 return; 103 } 104 105 /* Object isn't an AMDGPU object so ignore */ 106 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 107 placement->placement = &placements; 108 placement->busy_placement = &placements; 109 placement->num_placement = 1; 110 placement->num_busy_placement = 1; 111 return; 112 } 113 114 abo = ttm_to_amdgpu_bo(bo); 115 switch (bo->mem.mem_type) { 116 case AMDGPU_PL_GDS: 117 case AMDGPU_PL_GWS: 118 case AMDGPU_PL_OA: 119 placement->num_placement = 0; 120 placement->num_busy_placement = 0; 121 return; 122 123 case TTM_PL_VRAM: 124 if (!adev->mman.buffer_funcs_enabled) { 125 /* Move to system memory */ 126 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 127 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 128 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 129 amdgpu_bo_in_cpu_visible_vram(abo)) { 130 131 /* Try evicting to the CPU inaccessible part of VRAM 132 * first, but only set GTT as busy placement, so this 133 * BO will be evicted to GTT rather than causing other 134 * BOs to be evicted from VRAM 135 */ 136 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 137 AMDGPU_GEM_DOMAIN_GTT); 138 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 139 abo->placements[0].lpfn = 0; 140 abo->placement.busy_placement = &abo->placements[1]; 141 abo->placement.num_busy_placement = 1; 142 } else { 143 /* Move to GTT memory */ 144 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 145 } 146 break; 147 case TTM_PL_TT: 148 default: 149 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 150 break; 151 } 152 *placement = abo->placement; 153 } 154 155 /** 156 * amdgpu_verify_access - Verify access for a mmap call 157 * 158 * @bo: The buffer object to map 159 * @filp: The file pointer from the process performing the mmap 160 * 161 * This is called by ttm_bo_mmap() to verify whether a process 162 * has the right to mmap a BO to their process space. 163 */ 164 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 165 { 166 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 167 168 /* 169 * Don't verify access for KFD BOs. They don't have a GEM 170 * object associated with them. 171 */ 172 if (abo->kfd_bo) 173 return 0; 174 175 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 176 return -EPERM; 177 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 178 filp->private_data); 179 } 180 181 /** 182 * amdgpu_ttm_map_buffer - Map memory into the GART windows 183 * @bo: buffer object to map 184 * @mem: memory object to map 185 * @mm_cur: range to map 186 * @num_pages: number of pages to map 187 * @window: which GART window to use 188 * @ring: DMA ring to use for the copy 189 * @tmz: if we should setup a TMZ enabled mapping 190 * @addr: resulting address inside the MC address space 191 * 192 * Setup one of the GART windows to access a specific piece of memory or return 193 * the physical address for local memory. 194 */ 195 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 196 struct ttm_resource *mem, 197 struct amdgpu_res_cursor *mm_cur, 198 unsigned num_pages, unsigned window, 199 struct amdgpu_ring *ring, bool tmz, 200 uint64_t *addr) 201 { 202 struct amdgpu_device *adev = ring->adev; 203 struct amdgpu_job *job; 204 unsigned num_dw, num_bytes; 205 struct dma_fence *fence; 206 uint64_t src_addr, dst_addr; 207 void *cpu_addr; 208 uint64_t flags; 209 unsigned int i; 210 int r; 211 212 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 213 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 214 215 /* Map only what can't be accessed directly */ 216 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 217 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 218 mm_cur->start; 219 return 0; 220 } 221 222 *addr = adev->gmc.gart_start; 223 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 224 AMDGPU_GPU_PAGE_SIZE; 225 *addr += mm_cur->start & ~PAGE_MASK; 226 227 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 228 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 229 230 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 231 AMDGPU_IB_POOL_DELAYED, &job); 232 if (r) 233 return r; 234 235 src_addr = num_dw * 4; 236 src_addr += job->ibs[0].gpu_addr; 237 238 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 239 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 240 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 241 dst_addr, num_bytes, false); 242 243 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 244 WARN_ON(job->ibs[0].length_dw > num_dw); 245 246 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 247 if (tmz) 248 flags |= AMDGPU_PTE_TMZ; 249 250 cpu_addr = &job->ibs[0].ptr[num_dw]; 251 252 if (mem->mem_type == TTM_PL_TT) { 253 dma_addr_t *dma_addr; 254 255 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 256 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 257 cpu_addr); 258 if (r) 259 goto error_free; 260 } else { 261 dma_addr_t dma_address; 262 263 dma_address = mm_cur->start; 264 dma_address += adev->vm_manager.vram_base_offset; 265 266 for (i = 0; i < num_pages; ++i) { 267 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 268 &dma_address, flags, cpu_addr); 269 if (r) 270 goto error_free; 271 272 dma_address += PAGE_SIZE; 273 } 274 } 275 276 r = amdgpu_job_submit(job, &adev->mman.entity, 277 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 278 if (r) 279 goto error_free; 280 281 dma_fence_put(fence); 282 283 return r; 284 285 error_free: 286 amdgpu_job_free(job); 287 return r; 288 } 289 290 /** 291 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 292 * @adev: amdgpu device 293 * @src: buffer/address where to read from 294 * @dst: buffer/address where to write to 295 * @size: number of bytes to copy 296 * @tmz: if a secure copy should be used 297 * @resv: resv object to sync to 298 * @f: Returns the last fence if multiple jobs are submitted. 299 * 300 * The function copies @size bytes from {src->mem + src->offset} to 301 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 302 * move and different for a BO to BO copy. 303 * 304 */ 305 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 306 const struct amdgpu_copy_mem *src, 307 const struct amdgpu_copy_mem *dst, 308 uint64_t size, bool tmz, 309 struct dma_resv *resv, 310 struct dma_fence **f) 311 { 312 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 313 AMDGPU_GPU_PAGE_SIZE); 314 315 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 316 struct amdgpu_res_cursor src_mm, dst_mm; 317 struct dma_fence *fence = NULL; 318 int r = 0; 319 320 if (!adev->mman.buffer_funcs_enabled) { 321 DRM_ERROR("Trying to move memory with ring turned off.\n"); 322 return -EINVAL; 323 } 324 325 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 326 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 327 328 mutex_lock(&adev->mman.gtt_window_lock); 329 while (src_mm.remaining) { 330 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 331 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 332 struct dma_fence *next; 333 uint32_t cur_size; 334 uint64_t from, to; 335 336 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 337 * begins at an offset, then adjust the size accordingly 338 */ 339 cur_size = max(src_page_offset, dst_page_offset); 340 cur_size = min(min3(src_mm.size, dst_mm.size, size), 341 (uint64_t)(GTT_MAX_BYTES - cur_size)); 342 343 /* Map src to window 0 and dst to window 1. */ 344 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 345 PFN_UP(cur_size + src_page_offset), 346 0, ring, tmz, &from); 347 if (r) 348 goto error; 349 350 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 351 PFN_UP(cur_size + dst_page_offset), 352 1, ring, tmz, &to); 353 if (r) 354 goto error; 355 356 r = amdgpu_copy_buffer(ring, from, to, cur_size, 357 resv, &next, false, true, tmz); 358 if (r) 359 goto error; 360 361 dma_fence_put(fence); 362 fence = next; 363 364 amdgpu_res_next(&src_mm, cur_size); 365 amdgpu_res_next(&dst_mm, cur_size); 366 } 367 error: 368 mutex_unlock(&adev->mman.gtt_window_lock); 369 if (f) 370 *f = dma_fence_get(fence); 371 dma_fence_put(fence); 372 return r; 373 } 374 375 /* 376 * amdgpu_move_blit - Copy an entire buffer to another buffer 377 * 378 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 379 * help move buffers to and from VRAM. 380 */ 381 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 382 bool evict, 383 struct ttm_resource *new_mem, 384 struct ttm_resource *old_mem) 385 { 386 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 387 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 388 struct amdgpu_copy_mem src, dst; 389 struct dma_fence *fence = NULL; 390 int r; 391 392 src.bo = bo; 393 dst.bo = bo; 394 src.mem = old_mem; 395 dst.mem = new_mem; 396 src.offset = 0; 397 dst.offset = 0; 398 399 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 400 new_mem->num_pages << PAGE_SHIFT, 401 amdgpu_bo_encrypted(abo), 402 bo->base.resv, &fence); 403 if (r) 404 goto error; 405 406 /* clear the space being freed */ 407 if (old_mem->mem_type == TTM_PL_VRAM && 408 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 409 struct dma_fence *wipe_fence = NULL; 410 411 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 412 NULL, &wipe_fence); 413 if (r) { 414 goto error; 415 } else if (wipe_fence) { 416 dma_fence_put(fence); 417 fence = wipe_fence; 418 } 419 } 420 421 /* Always block for VM page tables before committing the new location */ 422 if (bo->type == ttm_bo_type_kernel) 423 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 424 else 425 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 426 dma_fence_put(fence); 427 return r; 428 429 error: 430 if (fence) 431 dma_fence_wait(fence, false); 432 dma_fence_put(fence); 433 return r; 434 } 435 436 /* 437 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 438 * 439 * Called by amdgpu_bo_move() 440 */ 441 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 442 struct ttm_resource *mem) 443 { 444 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 445 struct amdgpu_res_cursor cursor; 446 447 if (mem->mem_type == TTM_PL_SYSTEM || 448 mem->mem_type == TTM_PL_TT) 449 return true; 450 if (mem->mem_type != TTM_PL_VRAM) 451 return false; 452 453 amdgpu_res_first(mem, 0, mem_size, &cursor); 454 455 /* ttm_resource_ioremap only supports contiguous memory */ 456 if (cursor.size != mem_size) 457 return false; 458 459 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 460 } 461 462 /* 463 * amdgpu_bo_move - Move a buffer object to a new memory location 464 * 465 * Called by ttm_bo_handle_move_mem() 466 */ 467 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 468 struct ttm_operation_ctx *ctx, 469 struct ttm_resource *new_mem, 470 struct ttm_place *hop) 471 { 472 struct amdgpu_device *adev; 473 struct amdgpu_bo *abo; 474 struct ttm_resource *old_mem = &bo->mem; 475 int r; 476 477 if (new_mem->mem_type == TTM_PL_TT) { 478 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 479 if (r) 480 return r; 481 } 482 483 /* Can't move a pinned BO */ 484 abo = ttm_to_amdgpu_bo(bo); 485 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 486 return -EINVAL; 487 488 adev = amdgpu_ttm_adev(bo->bdev); 489 490 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 491 ttm_bo_move_null(bo, new_mem); 492 goto out; 493 } 494 if (old_mem->mem_type == TTM_PL_SYSTEM && 495 new_mem->mem_type == TTM_PL_TT) { 496 ttm_bo_move_null(bo, new_mem); 497 goto out; 498 } 499 if (old_mem->mem_type == TTM_PL_TT && 500 new_mem->mem_type == TTM_PL_SYSTEM) { 501 r = ttm_bo_wait_ctx(bo, ctx); 502 if (r) 503 return r; 504 505 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 506 ttm_resource_free(bo, &bo->mem); 507 ttm_bo_assign_mem(bo, new_mem); 508 goto out; 509 } 510 511 if (old_mem->mem_type == AMDGPU_PL_GDS || 512 old_mem->mem_type == AMDGPU_PL_GWS || 513 old_mem->mem_type == AMDGPU_PL_OA || 514 new_mem->mem_type == AMDGPU_PL_GDS || 515 new_mem->mem_type == AMDGPU_PL_GWS || 516 new_mem->mem_type == AMDGPU_PL_OA) { 517 /* Nothing to save here */ 518 ttm_bo_move_null(bo, new_mem); 519 goto out; 520 } 521 522 if (adev->mman.buffer_funcs_enabled) { 523 if (((old_mem->mem_type == TTM_PL_SYSTEM && 524 new_mem->mem_type == TTM_PL_VRAM) || 525 (old_mem->mem_type == TTM_PL_VRAM && 526 new_mem->mem_type == TTM_PL_SYSTEM))) { 527 hop->fpfn = 0; 528 hop->lpfn = 0; 529 hop->mem_type = TTM_PL_TT; 530 hop->flags = 0; 531 return -EMULTIHOP; 532 } 533 534 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 535 } else { 536 r = -ENODEV; 537 } 538 539 if (r) { 540 /* Check that all memory is CPU accessible */ 541 if (!amdgpu_mem_visible(adev, old_mem) || 542 !amdgpu_mem_visible(adev, new_mem)) { 543 pr_err("Move buffer fallback to memcpy unavailable\n"); 544 return r; 545 } 546 547 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 548 if (r) 549 return r; 550 } 551 552 if (bo->type == ttm_bo_type_device && 553 new_mem->mem_type == TTM_PL_VRAM && 554 old_mem->mem_type != TTM_PL_VRAM) { 555 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 556 * accesses the BO after it's moved. 557 */ 558 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 559 } 560 561 out: 562 /* update statistics */ 563 atomic64_add(bo->base.size, &adev->num_bytes_moved); 564 amdgpu_bo_move_notify(bo, evict, new_mem); 565 return 0; 566 } 567 568 /* 569 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 570 * 571 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 572 */ 573 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem) 574 { 575 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 576 struct drm_mm_node *mm_node = mem->mm_node; 577 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 578 579 switch (mem->mem_type) { 580 case TTM_PL_SYSTEM: 581 /* system memory */ 582 return 0; 583 case TTM_PL_TT: 584 break; 585 case TTM_PL_VRAM: 586 mem->bus.offset = mem->start << PAGE_SHIFT; 587 /* check if it's visible */ 588 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 589 return -EINVAL; 590 /* Only physically contiguous buffers apply. In a contiguous 591 * buffer, size of the first mm_node would match the number of 592 * pages in ttm_resource. 593 */ 594 if (adev->mman.aper_base_kaddr && 595 (mm_node->size == mem->num_pages)) 596 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 597 mem->bus.offset; 598 599 mem->bus.offset += adev->gmc.aper_base; 600 mem->bus.is_iomem = true; 601 if (adev->gmc.xgmi.connected_to_cpu) 602 mem->bus.caching = ttm_cached; 603 else 604 mem->bus.caching = ttm_write_combined; 605 break; 606 default: 607 return -EINVAL; 608 } 609 return 0; 610 } 611 612 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 613 unsigned long page_offset) 614 { 615 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 616 struct amdgpu_res_cursor cursor; 617 618 amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor); 619 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 620 } 621 622 /** 623 * amdgpu_ttm_domain_start - Returns GPU start address 624 * @adev: amdgpu device object 625 * @type: type of the memory 626 * 627 * Returns: 628 * GPU start address of a memory domain 629 */ 630 631 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 632 { 633 switch (type) { 634 case TTM_PL_TT: 635 return adev->gmc.gart_start; 636 case TTM_PL_VRAM: 637 return adev->gmc.vram_start; 638 } 639 640 return 0; 641 } 642 643 /* 644 * TTM backend functions. 645 */ 646 struct amdgpu_ttm_tt { 647 struct ttm_tt ttm; 648 struct drm_gem_object *gobj; 649 u64 offset; 650 uint64_t userptr; 651 struct task_struct *usertask; 652 uint32_t userflags; 653 bool bound; 654 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 655 struct hmm_range *range; 656 #endif 657 }; 658 659 #ifdef CONFIG_DRM_AMDGPU_USERPTR 660 /* 661 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 662 * memory and start HMM tracking CPU page table update 663 * 664 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 665 * once afterwards to stop HMM tracking 666 */ 667 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 668 { 669 struct ttm_tt *ttm = bo->tbo.ttm; 670 struct amdgpu_ttm_tt *gtt = (void *)ttm; 671 unsigned long start = gtt->userptr; 672 struct vm_area_struct *vma; 673 struct hmm_range *range; 674 unsigned long timeout; 675 struct mm_struct *mm; 676 unsigned long i; 677 int r = 0; 678 679 mm = bo->notifier.mm; 680 if (unlikely(!mm)) { 681 DRM_DEBUG_DRIVER("BO is not registered?\n"); 682 return -EFAULT; 683 } 684 685 /* Another get_user_pages is running at the same time?? */ 686 if (WARN_ON(gtt->range)) 687 return -EFAULT; 688 689 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 690 return -ESRCH; 691 692 range = kzalloc(sizeof(*range), GFP_KERNEL); 693 if (unlikely(!range)) { 694 r = -ENOMEM; 695 goto out; 696 } 697 range->notifier = &bo->notifier; 698 range->start = bo->notifier.interval_tree.start; 699 range->end = bo->notifier.interval_tree.last + 1; 700 range->default_flags = HMM_PFN_REQ_FAULT; 701 if (!amdgpu_ttm_tt_is_readonly(ttm)) 702 range->default_flags |= HMM_PFN_REQ_WRITE; 703 704 range->hmm_pfns = kvmalloc_array(ttm->num_pages, 705 sizeof(*range->hmm_pfns), GFP_KERNEL); 706 if (unlikely(!range->hmm_pfns)) { 707 r = -ENOMEM; 708 goto out_free_ranges; 709 } 710 711 mmap_read_lock(mm); 712 vma = vma_lookup(mm, start); 713 if (unlikely(!vma)) { 714 r = -EFAULT; 715 goto out_unlock; 716 } 717 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 718 vma->vm_file)) { 719 r = -EPERM; 720 goto out_unlock; 721 } 722 mmap_read_unlock(mm); 723 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 724 725 retry: 726 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 727 728 mmap_read_lock(mm); 729 r = hmm_range_fault(range); 730 mmap_read_unlock(mm); 731 if (unlikely(r)) { 732 /* 733 * FIXME: This timeout should encompass the retry from 734 * mmu_interval_read_retry() as well. 735 */ 736 if (r == -EBUSY && !time_after(jiffies, timeout)) 737 goto retry; 738 goto out_free_pfns; 739 } 740 741 /* 742 * Due to default_flags, all pages are HMM_PFN_VALID or 743 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside 744 * the notifier_lock, and mmu_interval_read_retry() must be done first. 745 */ 746 for (i = 0; i < ttm->num_pages; i++) 747 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); 748 749 gtt->range = range; 750 mmput(mm); 751 752 return 0; 753 754 out_unlock: 755 mmap_read_unlock(mm); 756 out_free_pfns: 757 kvfree(range->hmm_pfns); 758 out_free_ranges: 759 kfree(range); 760 out: 761 mmput(mm); 762 return r; 763 } 764 765 /* 766 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 767 * Check if the pages backing this ttm range have been invalidated 768 * 769 * Returns: true if pages are still valid 770 */ 771 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 772 { 773 struct amdgpu_ttm_tt *gtt = (void *)ttm; 774 bool r = false; 775 776 if (!gtt || !gtt->userptr) 777 return false; 778 779 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 780 gtt->userptr, ttm->num_pages); 781 782 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 783 "No user pages to check\n"); 784 785 if (gtt->range) { 786 /* 787 * FIXME: Must always hold notifier_lock for this, and must 788 * not ignore the return code. 789 */ 790 r = mmu_interval_read_retry(gtt->range->notifier, 791 gtt->range->notifier_seq); 792 kvfree(gtt->range->hmm_pfns); 793 kfree(gtt->range); 794 gtt->range = NULL; 795 } 796 797 return !r; 798 } 799 #endif 800 801 /* 802 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 803 * 804 * Called by amdgpu_cs_list_validate(). This creates the page list 805 * that backs user memory and will ultimately be mapped into the device 806 * address space. 807 */ 808 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 809 { 810 unsigned long i; 811 812 for (i = 0; i < ttm->num_pages; ++i) 813 ttm->pages[i] = pages ? pages[i] : NULL; 814 } 815 816 /* 817 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 818 * 819 * Called by amdgpu_ttm_backend_bind() 820 **/ 821 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 822 struct ttm_tt *ttm) 823 { 824 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 825 struct amdgpu_ttm_tt *gtt = (void *)ttm; 826 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 827 enum dma_data_direction direction = write ? 828 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 829 int r; 830 831 /* Allocate an SG array and squash pages into it */ 832 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 833 (u64)ttm->num_pages << PAGE_SHIFT, 834 GFP_KERNEL); 835 if (r) 836 goto release_sg; 837 838 /* Map SG to device */ 839 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 840 if (r) 841 goto release_sg; 842 843 /* convert SG to linear array of pages and dma addresses */ 844 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 845 ttm->num_pages); 846 847 return 0; 848 849 release_sg: 850 kfree(ttm->sg); 851 ttm->sg = NULL; 852 return r; 853 } 854 855 /* 856 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 857 */ 858 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 859 struct ttm_tt *ttm) 860 { 861 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 862 struct amdgpu_ttm_tt *gtt = (void *)ttm; 863 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 864 enum dma_data_direction direction = write ? 865 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 866 867 /* double check that we don't free the table twice */ 868 if (!ttm->sg || !ttm->sg->sgl) 869 return; 870 871 /* unmap the pages mapped to the device */ 872 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 873 sg_free_table(ttm->sg); 874 875 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 876 if (gtt->range) { 877 unsigned long i; 878 879 for (i = 0; i < ttm->num_pages; i++) { 880 if (ttm->pages[i] != 881 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 882 break; 883 } 884 885 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 886 } 887 #endif 888 } 889 890 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 891 struct ttm_buffer_object *tbo, 892 uint64_t flags) 893 { 894 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 895 struct ttm_tt *ttm = tbo->ttm; 896 struct amdgpu_ttm_tt *gtt = (void *)ttm; 897 int r; 898 899 if (amdgpu_bo_encrypted(abo)) 900 flags |= AMDGPU_PTE_TMZ; 901 902 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 903 uint64_t page_idx = 1; 904 905 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 906 ttm->pages, gtt->ttm.dma_address, flags); 907 if (r) 908 goto gart_bind_fail; 909 910 /* The memory type of the first page defaults to UC. Now 911 * modify the memory type to NC from the second page of 912 * the BO onward. 913 */ 914 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 915 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 916 917 r = amdgpu_gart_bind(adev, 918 gtt->offset + (page_idx << PAGE_SHIFT), 919 ttm->num_pages - page_idx, 920 &ttm->pages[page_idx], 921 &(gtt->ttm.dma_address[page_idx]), flags); 922 } else { 923 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 924 ttm->pages, gtt->ttm.dma_address, flags); 925 } 926 927 gart_bind_fail: 928 if (r) 929 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 930 ttm->num_pages, gtt->offset); 931 932 return r; 933 } 934 935 /* 936 * amdgpu_ttm_backend_bind - Bind GTT memory 937 * 938 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 939 * This handles binding GTT memory to the device address space. 940 */ 941 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 942 struct ttm_tt *ttm, 943 struct ttm_resource *bo_mem) 944 { 945 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 946 struct amdgpu_ttm_tt *gtt = (void*)ttm; 947 uint64_t flags; 948 int r = 0; 949 950 if (!bo_mem) 951 return -EINVAL; 952 953 if (gtt->bound) 954 return 0; 955 956 if (gtt->userptr) { 957 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 958 if (r) { 959 DRM_ERROR("failed to pin userptr\n"); 960 return r; 961 } 962 } 963 if (!ttm->num_pages) { 964 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 965 ttm->num_pages, bo_mem, ttm); 966 } 967 968 if (bo_mem->mem_type == AMDGPU_PL_GDS || 969 bo_mem->mem_type == AMDGPU_PL_GWS || 970 bo_mem->mem_type == AMDGPU_PL_OA) 971 return -EINVAL; 972 973 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 974 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 975 return 0; 976 } 977 978 /* compute PTE flags relevant to this BO memory */ 979 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 980 981 /* bind pages into GART page tables */ 982 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 983 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 984 ttm->pages, gtt->ttm.dma_address, flags); 985 986 if (r) 987 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 988 ttm->num_pages, gtt->offset); 989 gtt->bound = true; 990 return r; 991 } 992 993 /* 994 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 995 * through AGP or GART aperture. 996 * 997 * If bo is accessible through AGP aperture, then use AGP aperture 998 * to access bo; otherwise allocate logical space in GART aperture 999 * and map bo to GART aperture. 1000 */ 1001 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1002 { 1003 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1004 struct ttm_operation_ctx ctx = { false, false }; 1005 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 1006 struct ttm_resource tmp; 1007 struct ttm_placement placement; 1008 struct ttm_place placements; 1009 uint64_t addr, flags; 1010 int r; 1011 1012 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1013 return 0; 1014 1015 addr = amdgpu_gmc_agp_addr(bo); 1016 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1017 bo->mem.start = addr >> PAGE_SHIFT; 1018 } else { 1019 1020 /* allocate GART space */ 1021 tmp = bo->mem; 1022 tmp.mm_node = NULL; 1023 placement.num_placement = 1; 1024 placement.placement = &placements; 1025 placement.num_busy_placement = 1; 1026 placement.busy_placement = &placements; 1027 placements.fpfn = 0; 1028 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1029 placements.mem_type = TTM_PL_TT; 1030 placements.flags = bo->mem.placement; 1031 1032 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1033 if (unlikely(r)) 1034 return r; 1035 1036 /* compute PTE flags for this buffer object */ 1037 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1038 1039 /* Bind pages */ 1040 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1041 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1042 if (unlikely(r)) { 1043 ttm_resource_free(bo, &tmp); 1044 return r; 1045 } 1046 1047 ttm_resource_free(bo, &bo->mem); 1048 bo->mem = tmp; 1049 } 1050 1051 return 0; 1052 } 1053 1054 /* 1055 * amdgpu_ttm_recover_gart - Rebind GTT pages 1056 * 1057 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1058 * rebind GTT pages during a GPU reset. 1059 */ 1060 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1061 { 1062 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1063 uint64_t flags; 1064 int r; 1065 1066 if (!tbo->ttm) 1067 return 0; 1068 1069 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1070 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1071 1072 return r; 1073 } 1074 1075 /* 1076 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1077 * 1078 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1079 * ttm_tt_destroy(). 1080 */ 1081 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1082 struct ttm_tt *ttm) 1083 { 1084 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1085 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1086 int r; 1087 1088 /* if the pages have userptr pinning then clear that first */ 1089 if (gtt->userptr) 1090 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1091 1092 if (!gtt->bound) 1093 return; 1094 1095 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1096 return; 1097 1098 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1099 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1100 if (r) 1101 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1102 gtt->ttm.num_pages, gtt->offset); 1103 gtt->bound = false; 1104 } 1105 1106 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1107 struct ttm_tt *ttm) 1108 { 1109 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1110 1111 amdgpu_ttm_backend_unbind(bdev, ttm); 1112 ttm_tt_destroy_common(bdev, ttm); 1113 if (gtt->usertask) 1114 put_task_struct(gtt->usertask); 1115 1116 ttm_tt_fini(>t->ttm); 1117 kfree(gtt); 1118 } 1119 1120 /** 1121 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1122 * 1123 * @bo: The buffer object to create a GTT ttm_tt object around 1124 * @page_flags: Page flags to be added to the ttm_tt object 1125 * 1126 * Called by ttm_tt_create(). 1127 */ 1128 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1129 uint32_t page_flags) 1130 { 1131 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1132 struct amdgpu_ttm_tt *gtt; 1133 enum ttm_caching caching; 1134 1135 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1136 if (gtt == NULL) { 1137 return NULL; 1138 } 1139 gtt->gobj = &bo->base; 1140 1141 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1142 caching = ttm_write_combined; 1143 else 1144 caching = ttm_cached; 1145 1146 /* allocate space for the uninitialized page entries */ 1147 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1148 kfree(gtt); 1149 return NULL; 1150 } 1151 return >t->ttm; 1152 } 1153 1154 /* 1155 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1156 * 1157 * Map the pages of a ttm_tt object to an address space visible 1158 * to the underlying device. 1159 */ 1160 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1161 struct ttm_tt *ttm, 1162 struct ttm_operation_ctx *ctx) 1163 { 1164 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1165 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1166 1167 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1168 if (gtt && gtt->userptr) { 1169 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1170 if (!ttm->sg) 1171 return -ENOMEM; 1172 1173 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1174 return 0; 1175 } 1176 1177 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1178 if (!ttm->sg) { 1179 struct dma_buf_attachment *attach; 1180 struct sg_table *sgt; 1181 1182 attach = gtt->gobj->import_attach; 1183 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1184 if (IS_ERR(sgt)) 1185 return PTR_ERR(sgt); 1186 1187 ttm->sg = sgt; 1188 } 1189 1190 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 1191 ttm->num_pages); 1192 return 0; 1193 } 1194 1195 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1196 } 1197 1198 /* 1199 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1200 * 1201 * Unmaps pages of a ttm_tt object from the device address space and 1202 * unpopulates the page array backing it. 1203 */ 1204 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1205 struct ttm_tt *ttm) 1206 { 1207 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1208 struct amdgpu_device *adev; 1209 1210 if (gtt && gtt->userptr) { 1211 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1212 kfree(ttm->sg); 1213 ttm->sg = NULL; 1214 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1215 return; 1216 } 1217 1218 if (ttm->sg && gtt->gobj->import_attach) { 1219 struct dma_buf_attachment *attach; 1220 1221 attach = gtt->gobj->import_attach; 1222 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1223 ttm->sg = NULL; 1224 return; 1225 } 1226 1227 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1228 return; 1229 1230 adev = amdgpu_ttm_adev(bdev); 1231 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1232 } 1233 1234 /** 1235 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1236 * task 1237 * 1238 * @bo: The ttm_buffer_object to bind this userptr to 1239 * @addr: The address in the current tasks VM space to use 1240 * @flags: Requirements of userptr object. 1241 * 1242 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1243 * to current task 1244 */ 1245 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1246 uint64_t addr, uint32_t flags) 1247 { 1248 struct amdgpu_ttm_tt *gtt; 1249 1250 if (!bo->ttm) { 1251 /* TODO: We want a separate TTM object type for userptrs */ 1252 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1253 if (bo->ttm == NULL) 1254 return -ENOMEM; 1255 } 1256 1257 gtt = (void *)bo->ttm; 1258 gtt->userptr = addr; 1259 gtt->userflags = flags; 1260 1261 if (gtt->usertask) 1262 put_task_struct(gtt->usertask); 1263 gtt->usertask = current->group_leader; 1264 get_task_struct(gtt->usertask); 1265 1266 return 0; 1267 } 1268 1269 /* 1270 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1271 */ 1272 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1273 { 1274 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1275 1276 if (gtt == NULL) 1277 return NULL; 1278 1279 if (gtt->usertask == NULL) 1280 return NULL; 1281 1282 return gtt->usertask->mm; 1283 } 1284 1285 /* 1286 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1287 * address range for the current task. 1288 * 1289 */ 1290 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1291 unsigned long end) 1292 { 1293 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1294 unsigned long size; 1295 1296 if (gtt == NULL || !gtt->userptr) 1297 return false; 1298 1299 /* Return false if no part of the ttm_tt object lies within 1300 * the range 1301 */ 1302 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1303 if (gtt->userptr > end || gtt->userptr + size <= start) 1304 return false; 1305 1306 return true; 1307 } 1308 1309 /* 1310 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1311 */ 1312 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1313 { 1314 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1315 1316 if (gtt == NULL || !gtt->userptr) 1317 return false; 1318 1319 return true; 1320 } 1321 1322 /* 1323 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1324 */ 1325 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1326 { 1327 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1328 1329 if (gtt == NULL) 1330 return false; 1331 1332 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1333 } 1334 1335 /** 1336 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1337 * 1338 * @ttm: The ttm_tt object to compute the flags for 1339 * @mem: The memory registry backing this ttm_tt object 1340 * 1341 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1342 */ 1343 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1344 { 1345 uint64_t flags = 0; 1346 1347 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1348 flags |= AMDGPU_PTE_VALID; 1349 1350 if (mem && mem->mem_type == TTM_PL_TT) { 1351 flags |= AMDGPU_PTE_SYSTEM; 1352 1353 if (ttm->caching == ttm_cached) 1354 flags |= AMDGPU_PTE_SNOOPED; 1355 } 1356 1357 if (mem && mem->mem_type == TTM_PL_VRAM && 1358 mem->bus.caching == ttm_cached) 1359 flags |= AMDGPU_PTE_SNOOPED; 1360 1361 return flags; 1362 } 1363 1364 /** 1365 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1366 * 1367 * @adev: amdgpu_device pointer 1368 * @ttm: The ttm_tt object to compute the flags for 1369 * @mem: The memory registry backing this ttm_tt object 1370 * 1371 * Figure out the flags to use for a VM PTE (Page Table Entry). 1372 */ 1373 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1374 struct ttm_resource *mem) 1375 { 1376 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1377 1378 flags |= adev->gart.gart_pte_flags; 1379 flags |= AMDGPU_PTE_READABLE; 1380 1381 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1382 flags |= AMDGPU_PTE_WRITEABLE; 1383 1384 return flags; 1385 } 1386 1387 /* 1388 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1389 * object. 1390 * 1391 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1392 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1393 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1394 * used to clean out a memory space. 1395 */ 1396 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1397 const struct ttm_place *place) 1398 { 1399 unsigned long num_pages = bo->mem.num_pages; 1400 struct amdgpu_res_cursor cursor; 1401 struct dma_resv_list *flist; 1402 struct dma_fence *f; 1403 int i; 1404 1405 if (bo->type == ttm_bo_type_kernel && 1406 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1407 return false; 1408 1409 /* If bo is a KFD BO, check if the bo belongs to the current process. 1410 * If true, then return false as any KFD process needs all its BOs to 1411 * be resident to run successfully 1412 */ 1413 flist = dma_resv_get_list(bo->base.resv); 1414 if (flist) { 1415 for (i = 0; i < flist->shared_count; ++i) { 1416 f = rcu_dereference_protected(flist->shared[i], 1417 dma_resv_held(bo->base.resv)); 1418 if (amdkfd_fence_check_mm(f, current->mm)) 1419 return false; 1420 } 1421 } 1422 1423 switch (bo->mem.mem_type) { 1424 case TTM_PL_TT: 1425 if (amdgpu_bo_is_amdgpu_bo(bo) && 1426 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1427 return false; 1428 return true; 1429 1430 case TTM_PL_VRAM: 1431 /* Check each drm MM node individually */ 1432 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT, 1433 &cursor); 1434 while (cursor.remaining) { 1435 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1436 && !(place->lpfn && 1437 place->lpfn <= PFN_DOWN(cursor.start))) 1438 return true; 1439 1440 amdgpu_res_next(&cursor, cursor.size); 1441 } 1442 return false; 1443 1444 default: 1445 break; 1446 } 1447 1448 return ttm_bo_eviction_valuable(bo, place); 1449 } 1450 1451 /** 1452 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1453 * 1454 * @bo: The buffer object to read/write 1455 * @offset: Offset into buffer object 1456 * @buf: Secondary buffer to write/read from 1457 * @len: Length in bytes of access 1458 * @write: true if writing 1459 * 1460 * This is used to access VRAM that backs a buffer object via MMIO 1461 * access for debugging purposes. 1462 */ 1463 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1464 unsigned long offset, void *buf, int len, 1465 int write) 1466 { 1467 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1468 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1469 struct amdgpu_res_cursor cursor; 1470 unsigned long flags; 1471 uint32_t value = 0; 1472 int ret = 0; 1473 1474 if (bo->mem.mem_type != TTM_PL_VRAM) 1475 return -EIO; 1476 1477 amdgpu_res_first(&bo->mem, offset, len, &cursor); 1478 while (cursor.remaining) { 1479 uint64_t aligned_pos = cursor.start & ~(uint64_t)3; 1480 uint64_t bytes = 4 - (cursor.start & 3); 1481 uint32_t shift = (cursor.start & 3) * 8; 1482 uint32_t mask = 0xffffffff << shift; 1483 1484 if (cursor.size < bytes) { 1485 mask &= 0xffffffff >> (bytes - cursor.size) * 8; 1486 bytes = cursor.size; 1487 } 1488 1489 if (mask != 0xffffffff) { 1490 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1491 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1492 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1493 value = RREG32_NO_KIQ(mmMM_DATA); 1494 if (write) { 1495 value &= ~mask; 1496 value |= (*(uint32_t *)buf << shift) & mask; 1497 WREG32_NO_KIQ(mmMM_DATA, value); 1498 } 1499 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1500 if (!write) { 1501 value = (value & mask) >> shift; 1502 memcpy(buf, &value, bytes); 1503 } 1504 } else { 1505 bytes = cursor.size & ~0x3ULL; 1506 amdgpu_device_vram_access(adev, cursor.start, 1507 (uint32_t *)buf, bytes, 1508 write); 1509 } 1510 1511 ret += bytes; 1512 buf = (uint8_t *)buf + bytes; 1513 amdgpu_res_next(&cursor, bytes); 1514 } 1515 1516 return ret; 1517 } 1518 1519 static void 1520 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1521 { 1522 amdgpu_bo_move_notify(bo, false, NULL); 1523 } 1524 1525 static struct ttm_device_funcs amdgpu_bo_driver = { 1526 .ttm_tt_create = &amdgpu_ttm_tt_create, 1527 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1528 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1529 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1530 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1531 .evict_flags = &amdgpu_evict_flags, 1532 .move = &amdgpu_bo_move, 1533 .verify_access = &amdgpu_verify_access, 1534 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1535 .release_notify = &amdgpu_bo_release_notify, 1536 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1537 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1538 .access_memory = &amdgpu_ttm_access_memory, 1539 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1540 }; 1541 1542 /* 1543 * Firmware Reservation functions 1544 */ 1545 /** 1546 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1547 * 1548 * @adev: amdgpu_device pointer 1549 * 1550 * free fw reserved vram if it has been reserved. 1551 */ 1552 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1553 { 1554 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1555 NULL, &adev->mman.fw_vram_usage_va); 1556 } 1557 1558 /** 1559 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1560 * 1561 * @adev: amdgpu_device pointer 1562 * 1563 * create bo vram reservation from fw. 1564 */ 1565 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1566 { 1567 uint64_t vram_size = adev->gmc.visible_vram_size; 1568 1569 adev->mman.fw_vram_usage_va = NULL; 1570 adev->mman.fw_vram_usage_reserved_bo = NULL; 1571 1572 if (adev->mman.fw_vram_usage_size == 0 || 1573 adev->mman.fw_vram_usage_size > vram_size) 1574 return 0; 1575 1576 return amdgpu_bo_create_kernel_at(adev, 1577 adev->mman.fw_vram_usage_start_offset, 1578 adev->mman.fw_vram_usage_size, 1579 AMDGPU_GEM_DOMAIN_VRAM, 1580 &adev->mman.fw_vram_usage_reserved_bo, 1581 &adev->mman.fw_vram_usage_va); 1582 } 1583 1584 /* 1585 * Memoy training reservation functions 1586 */ 1587 1588 /** 1589 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1590 * 1591 * @adev: amdgpu_device pointer 1592 * 1593 * free memory training reserved vram if it has been reserved. 1594 */ 1595 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1596 { 1597 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1598 1599 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1600 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1601 ctx->c2p_bo = NULL; 1602 1603 return 0; 1604 } 1605 1606 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1607 { 1608 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1609 1610 memset(ctx, 0, sizeof(*ctx)); 1611 1612 ctx->c2p_train_data_offset = 1613 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1614 ctx->p2c_train_data_offset = 1615 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1616 ctx->train_data_size = 1617 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1618 1619 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1620 ctx->train_data_size, 1621 ctx->p2c_train_data_offset, 1622 ctx->c2p_train_data_offset); 1623 } 1624 1625 /* 1626 * reserve TMR memory at the top of VRAM which holds 1627 * IP Discovery data and is protected by PSP. 1628 */ 1629 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1630 { 1631 int ret; 1632 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1633 bool mem_train_support = false; 1634 1635 if (!amdgpu_sriov_vf(adev)) { 1636 ret = amdgpu_mem_train_support(adev); 1637 if (ret == 1) 1638 mem_train_support = true; 1639 else if (ret == -1) 1640 return -EINVAL; 1641 else 1642 DRM_DEBUG("memory training does not support!\n"); 1643 } 1644 1645 /* 1646 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1647 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1648 * 1649 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1650 * discovery data and G6 memory training data respectively 1651 */ 1652 adev->mman.discovery_tmr_size = 1653 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1654 if (!adev->mman.discovery_tmr_size) 1655 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1656 1657 if (mem_train_support) { 1658 /* reserve vram for mem train according to TMR location */ 1659 amdgpu_ttm_training_data_block_init(adev); 1660 ret = amdgpu_bo_create_kernel_at(adev, 1661 ctx->c2p_train_data_offset, 1662 ctx->train_data_size, 1663 AMDGPU_GEM_DOMAIN_VRAM, 1664 &ctx->c2p_bo, 1665 NULL); 1666 if (ret) { 1667 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1668 amdgpu_ttm_training_reserve_vram_fini(adev); 1669 return ret; 1670 } 1671 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1672 } 1673 1674 ret = amdgpu_bo_create_kernel_at(adev, 1675 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1676 adev->mman.discovery_tmr_size, 1677 AMDGPU_GEM_DOMAIN_VRAM, 1678 &adev->mman.discovery_memory, 1679 NULL); 1680 if (ret) { 1681 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1682 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1683 return ret; 1684 } 1685 1686 return 0; 1687 } 1688 1689 /* 1690 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1691 * gtt/vram related fields. 1692 * 1693 * This initializes all of the memory space pools that the TTM layer 1694 * will need such as the GTT space (system memory mapped to the device), 1695 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1696 * can be mapped per VMID. 1697 */ 1698 int amdgpu_ttm_init(struct amdgpu_device *adev) 1699 { 1700 uint64_t gtt_size; 1701 int r; 1702 u64 vis_vram_limit; 1703 1704 mutex_init(&adev->mman.gtt_window_lock); 1705 1706 /* No others user of address space so set it to 0 */ 1707 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1708 adev_to_drm(adev)->anon_inode->i_mapping, 1709 adev_to_drm(adev)->vma_offset_manager, 1710 adev->need_swiotlb, 1711 dma_addressing_limited(adev->dev)); 1712 if (r) { 1713 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1714 return r; 1715 } 1716 adev->mman.initialized = true; 1717 1718 /* Initialize VRAM pool with all of VRAM divided into pages */ 1719 r = amdgpu_vram_mgr_init(adev); 1720 if (r) { 1721 DRM_ERROR("Failed initializing VRAM heap.\n"); 1722 return r; 1723 } 1724 1725 /* Reduce size of CPU-visible VRAM if requested */ 1726 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1727 if (amdgpu_vis_vram_limit > 0 && 1728 vis_vram_limit <= adev->gmc.visible_vram_size) 1729 adev->gmc.visible_vram_size = vis_vram_limit; 1730 1731 /* Change the size here instead of the init above so only lpfn is affected */ 1732 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1733 #ifdef CONFIG_64BIT 1734 #ifdef CONFIG_X86 1735 if (adev->gmc.xgmi.connected_to_cpu) 1736 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1737 adev->gmc.visible_vram_size); 1738 1739 else 1740 #endif 1741 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1742 adev->gmc.visible_vram_size); 1743 #endif 1744 1745 /* 1746 *The reserved vram for firmware must be pinned to the specified 1747 *place on the VRAM, so reserve it early. 1748 */ 1749 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1750 if (r) { 1751 return r; 1752 } 1753 1754 /* 1755 * only NAVI10 and onwards ASIC support for IP discovery. 1756 * If IP discovery enabled, a block of memory should be 1757 * reserved for IP discovey. 1758 */ 1759 if (adev->mman.discovery_bin) { 1760 r = amdgpu_ttm_reserve_tmr(adev); 1761 if (r) 1762 return r; 1763 } 1764 1765 /* allocate memory as required for VGA 1766 * This is used for VGA emulation and pre-OS scanout buffers to 1767 * avoid display artifacts while transitioning between pre-OS 1768 * and driver. */ 1769 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1770 AMDGPU_GEM_DOMAIN_VRAM, 1771 &adev->mman.stolen_vga_memory, 1772 NULL); 1773 if (r) 1774 return r; 1775 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1776 adev->mman.stolen_extended_size, 1777 AMDGPU_GEM_DOMAIN_VRAM, 1778 &adev->mman.stolen_extended_memory, 1779 NULL); 1780 if (r) 1781 return r; 1782 1783 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1784 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1785 1786 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1787 * or whatever the user passed on module init */ 1788 if (amdgpu_gtt_size == -1) { 1789 struct sysinfo si; 1790 1791 si_meminfo(&si); 1792 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1793 adev->gmc.mc_vram_size), 1794 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1795 } 1796 else 1797 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1798 1799 /* Initialize GTT memory pool */ 1800 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1801 if (r) { 1802 DRM_ERROR("Failed initializing GTT heap.\n"); 1803 return r; 1804 } 1805 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1806 (unsigned)(gtt_size / (1024 * 1024))); 1807 1808 /* Initialize various on-chip memory pools */ 1809 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1810 if (r) { 1811 DRM_ERROR("Failed initializing GDS heap.\n"); 1812 return r; 1813 } 1814 1815 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1816 if (r) { 1817 DRM_ERROR("Failed initializing gws heap.\n"); 1818 return r; 1819 } 1820 1821 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1822 if (r) { 1823 DRM_ERROR("Failed initializing oa heap.\n"); 1824 return r; 1825 } 1826 1827 return 0; 1828 } 1829 1830 /* 1831 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1832 */ 1833 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1834 { 1835 if (!adev->mman.initialized) 1836 return; 1837 1838 amdgpu_ttm_training_reserve_vram_fini(adev); 1839 /* return the stolen vga memory back to VRAM */ 1840 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1841 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1842 /* return the IP Discovery TMR memory back to VRAM */ 1843 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1844 amdgpu_ttm_fw_reserve_vram_fini(adev); 1845 1846 if (adev->mman.aper_base_kaddr) 1847 iounmap(adev->mman.aper_base_kaddr); 1848 adev->mman.aper_base_kaddr = NULL; 1849 1850 amdgpu_vram_mgr_fini(adev); 1851 amdgpu_gtt_mgr_fini(adev); 1852 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1853 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1854 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1855 ttm_device_fini(&adev->mman.bdev); 1856 adev->mman.initialized = false; 1857 DRM_INFO("amdgpu: ttm finalized\n"); 1858 } 1859 1860 /** 1861 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1862 * 1863 * @adev: amdgpu_device pointer 1864 * @enable: true when we can use buffer functions. 1865 * 1866 * Enable/disable use of buffer functions during suspend/resume. This should 1867 * only be called at bootup or when userspace isn't running. 1868 */ 1869 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1870 { 1871 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1872 uint64_t size; 1873 int r; 1874 1875 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1876 adev->mman.buffer_funcs_enabled == enable) 1877 return; 1878 1879 if (enable) { 1880 struct amdgpu_ring *ring; 1881 struct drm_gpu_scheduler *sched; 1882 1883 ring = adev->mman.buffer_funcs_ring; 1884 sched = &ring->sched; 1885 r = drm_sched_entity_init(&adev->mman.entity, 1886 DRM_SCHED_PRIORITY_KERNEL, &sched, 1887 1, NULL); 1888 if (r) { 1889 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1890 r); 1891 return; 1892 } 1893 } else { 1894 drm_sched_entity_destroy(&adev->mman.entity); 1895 dma_fence_put(man->move); 1896 man->move = NULL; 1897 } 1898 1899 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1900 if (enable) 1901 size = adev->gmc.real_vram_size; 1902 else 1903 size = adev->gmc.visible_vram_size; 1904 man->size = size >> PAGE_SHIFT; 1905 adev->mman.buffer_funcs_enabled = enable; 1906 } 1907 1908 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) 1909 { 1910 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 1911 vm_fault_t ret; 1912 1913 ret = ttm_bo_vm_reserve(bo, vmf); 1914 if (ret) 1915 return ret; 1916 1917 ret = amdgpu_bo_fault_reserve_notify(bo); 1918 if (ret) 1919 goto unlock; 1920 1921 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 1922 TTM_BO_VM_NUM_PREFAULT, 1); 1923 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 1924 return ret; 1925 1926 unlock: 1927 dma_resv_unlock(bo->base.resv); 1928 return ret; 1929 } 1930 1931 static const struct vm_operations_struct amdgpu_ttm_vm_ops = { 1932 .fault = amdgpu_ttm_fault, 1933 .open = ttm_bo_vm_open, 1934 .close = ttm_bo_vm_close, 1935 .access = ttm_bo_vm_access 1936 }; 1937 1938 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1939 { 1940 struct drm_file *file_priv = filp->private_data; 1941 struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); 1942 int r; 1943 1944 r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1945 if (unlikely(r != 0)) 1946 return r; 1947 1948 vma->vm_ops = &amdgpu_ttm_vm_ops; 1949 return 0; 1950 } 1951 1952 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1953 uint64_t dst_offset, uint32_t byte_count, 1954 struct dma_resv *resv, 1955 struct dma_fence **fence, bool direct_submit, 1956 bool vm_needs_flush, bool tmz) 1957 { 1958 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1959 AMDGPU_IB_POOL_DELAYED; 1960 struct amdgpu_device *adev = ring->adev; 1961 struct amdgpu_job *job; 1962 1963 uint32_t max_bytes; 1964 unsigned num_loops, num_dw; 1965 unsigned i; 1966 int r; 1967 1968 if (direct_submit && !ring->sched.ready) { 1969 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1970 return -EINVAL; 1971 } 1972 1973 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1974 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1975 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1976 1977 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1978 if (r) 1979 return r; 1980 1981 if (vm_needs_flush) { 1982 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1983 adev->gmc.pdb0_bo : adev->gart.bo); 1984 job->vm_needs_flush = true; 1985 } 1986 if (resv) { 1987 r = amdgpu_sync_resv(adev, &job->sync, resv, 1988 AMDGPU_SYNC_ALWAYS, 1989 AMDGPU_FENCE_OWNER_UNDEFINED); 1990 if (r) { 1991 DRM_ERROR("sync failed (%d).\n", r); 1992 goto error_free; 1993 } 1994 } 1995 1996 for (i = 0; i < num_loops; i++) { 1997 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1998 1999 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2000 dst_offset, cur_size_in_bytes, tmz); 2001 2002 src_offset += cur_size_in_bytes; 2003 dst_offset += cur_size_in_bytes; 2004 byte_count -= cur_size_in_bytes; 2005 } 2006 2007 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2008 WARN_ON(job->ibs[0].length_dw > num_dw); 2009 if (direct_submit) 2010 r = amdgpu_job_submit_direct(job, ring, fence); 2011 else 2012 r = amdgpu_job_submit(job, &adev->mman.entity, 2013 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2014 if (r) 2015 goto error_free; 2016 2017 return r; 2018 2019 error_free: 2020 amdgpu_job_free(job); 2021 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2022 return r; 2023 } 2024 2025 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2026 uint32_t src_data, 2027 struct dma_resv *resv, 2028 struct dma_fence **fence) 2029 { 2030 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2031 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2032 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2033 2034 struct amdgpu_res_cursor cursor; 2035 unsigned int num_loops, num_dw; 2036 uint64_t num_bytes; 2037 2038 struct amdgpu_job *job; 2039 int r; 2040 2041 if (!adev->mman.buffer_funcs_enabled) { 2042 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2043 return -EINVAL; 2044 } 2045 2046 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2047 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2048 if (r) 2049 return r; 2050 } 2051 2052 num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT; 2053 num_loops = 0; 2054 2055 amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); 2056 while (cursor.remaining) { 2057 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 2058 amdgpu_res_next(&cursor, cursor.size); 2059 } 2060 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2061 2062 /* for IB padding */ 2063 num_dw += 64; 2064 2065 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2066 &job); 2067 if (r) 2068 return r; 2069 2070 if (resv) { 2071 r = amdgpu_sync_resv(adev, &job->sync, resv, 2072 AMDGPU_SYNC_ALWAYS, 2073 AMDGPU_FENCE_OWNER_UNDEFINED); 2074 if (r) { 2075 DRM_ERROR("sync failed (%d).\n", r); 2076 goto error_free; 2077 } 2078 } 2079 2080 amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); 2081 while (cursor.remaining) { 2082 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2083 uint64_t dst_addr = cursor.start; 2084 2085 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 2086 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2087 cur_size); 2088 2089 amdgpu_res_next(&cursor, cur_size); 2090 } 2091 2092 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2093 WARN_ON(job->ibs[0].length_dw > num_dw); 2094 r = amdgpu_job_submit(job, &adev->mman.entity, 2095 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2096 if (r) 2097 goto error_free; 2098 2099 return 0; 2100 2101 error_free: 2102 amdgpu_job_free(job); 2103 return r; 2104 } 2105 2106 #if defined(CONFIG_DEBUG_FS) 2107 2108 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2109 { 2110 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2111 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2112 TTM_PL_VRAM); 2113 struct drm_printer p = drm_seq_file_printer(m); 2114 2115 man->func->debug(man, &p); 2116 return 0; 2117 } 2118 2119 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2120 { 2121 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2122 2123 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2124 } 2125 2126 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2127 { 2128 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2129 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2130 TTM_PL_TT); 2131 struct drm_printer p = drm_seq_file_printer(m); 2132 2133 man->func->debug(man, &p); 2134 return 0; 2135 } 2136 2137 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2138 { 2139 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2140 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2141 AMDGPU_PL_GDS); 2142 struct drm_printer p = drm_seq_file_printer(m); 2143 2144 man->func->debug(man, &p); 2145 return 0; 2146 } 2147 2148 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2149 { 2150 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2151 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2152 AMDGPU_PL_GWS); 2153 struct drm_printer p = drm_seq_file_printer(m); 2154 2155 man->func->debug(man, &p); 2156 return 0; 2157 } 2158 2159 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2160 { 2161 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2162 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2163 AMDGPU_PL_OA); 2164 struct drm_printer p = drm_seq_file_printer(m); 2165 2166 man->func->debug(man, &p); 2167 return 0; 2168 } 2169 2170 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2171 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2172 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2173 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2174 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2175 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2176 2177 /* 2178 * amdgpu_ttm_vram_read - Linear read access to VRAM 2179 * 2180 * Accesses VRAM via MMIO for debugging purposes. 2181 */ 2182 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2183 size_t size, loff_t *pos) 2184 { 2185 struct amdgpu_device *adev = file_inode(f)->i_private; 2186 ssize_t result = 0; 2187 2188 if (size & 0x3 || *pos & 0x3) 2189 return -EINVAL; 2190 2191 if (*pos >= adev->gmc.mc_vram_size) 2192 return -ENXIO; 2193 2194 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2195 while (size) { 2196 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2197 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2198 2199 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2200 if (copy_to_user(buf, value, bytes)) 2201 return -EFAULT; 2202 2203 result += bytes; 2204 buf += bytes; 2205 *pos += bytes; 2206 size -= bytes; 2207 } 2208 2209 return result; 2210 } 2211 2212 /* 2213 * amdgpu_ttm_vram_write - Linear write access to VRAM 2214 * 2215 * Accesses VRAM via MMIO for debugging purposes. 2216 */ 2217 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2218 size_t size, loff_t *pos) 2219 { 2220 struct amdgpu_device *adev = file_inode(f)->i_private; 2221 ssize_t result = 0; 2222 int r; 2223 2224 if (size & 0x3 || *pos & 0x3) 2225 return -EINVAL; 2226 2227 if (*pos >= adev->gmc.mc_vram_size) 2228 return -ENXIO; 2229 2230 while (size) { 2231 unsigned long flags; 2232 uint32_t value; 2233 2234 if (*pos >= adev->gmc.mc_vram_size) 2235 return result; 2236 2237 r = get_user(value, (uint32_t *)buf); 2238 if (r) 2239 return r; 2240 2241 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2242 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2243 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2244 WREG32_NO_KIQ(mmMM_DATA, value); 2245 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2246 2247 result += 4; 2248 buf += 4; 2249 *pos += 4; 2250 size -= 4; 2251 } 2252 2253 return result; 2254 } 2255 2256 static const struct file_operations amdgpu_ttm_vram_fops = { 2257 .owner = THIS_MODULE, 2258 .read = amdgpu_ttm_vram_read, 2259 .write = amdgpu_ttm_vram_write, 2260 .llseek = default_llseek, 2261 }; 2262 2263 /* 2264 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2265 * 2266 * This function is used to read memory that has been mapped to the 2267 * GPU and the known addresses are not physical addresses but instead 2268 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2269 */ 2270 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2271 size_t size, loff_t *pos) 2272 { 2273 struct amdgpu_device *adev = file_inode(f)->i_private; 2274 struct iommu_domain *dom; 2275 ssize_t result = 0; 2276 int r; 2277 2278 /* retrieve the IOMMU domain if any for this device */ 2279 dom = iommu_get_domain_for_dev(adev->dev); 2280 2281 while (size) { 2282 phys_addr_t addr = *pos & PAGE_MASK; 2283 loff_t off = *pos & ~PAGE_MASK; 2284 size_t bytes = PAGE_SIZE - off; 2285 unsigned long pfn; 2286 struct page *p; 2287 void *ptr; 2288 2289 bytes = bytes < size ? bytes : size; 2290 2291 /* Translate the bus address to a physical address. If 2292 * the domain is NULL it means there is no IOMMU active 2293 * and the address translation is the identity 2294 */ 2295 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2296 2297 pfn = addr >> PAGE_SHIFT; 2298 if (!pfn_valid(pfn)) 2299 return -EPERM; 2300 2301 p = pfn_to_page(pfn); 2302 if (p->mapping != adev->mman.bdev.dev_mapping) 2303 return -EPERM; 2304 2305 ptr = kmap(p); 2306 r = copy_to_user(buf, ptr + off, bytes); 2307 kunmap(p); 2308 if (r) 2309 return -EFAULT; 2310 2311 size -= bytes; 2312 *pos += bytes; 2313 result += bytes; 2314 } 2315 2316 return result; 2317 } 2318 2319 /* 2320 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2321 * 2322 * This function is used to write memory that has been mapped to the 2323 * GPU and the known addresses are not physical addresses but instead 2324 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2325 */ 2326 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2327 size_t size, loff_t *pos) 2328 { 2329 struct amdgpu_device *adev = file_inode(f)->i_private; 2330 struct iommu_domain *dom; 2331 ssize_t result = 0; 2332 int r; 2333 2334 dom = iommu_get_domain_for_dev(adev->dev); 2335 2336 while (size) { 2337 phys_addr_t addr = *pos & PAGE_MASK; 2338 loff_t off = *pos & ~PAGE_MASK; 2339 size_t bytes = PAGE_SIZE - off; 2340 unsigned long pfn; 2341 struct page *p; 2342 void *ptr; 2343 2344 bytes = bytes < size ? bytes : size; 2345 2346 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2347 2348 pfn = addr >> PAGE_SHIFT; 2349 if (!pfn_valid(pfn)) 2350 return -EPERM; 2351 2352 p = pfn_to_page(pfn); 2353 if (p->mapping != adev->mman.bdev.dev_mapping) 2354 return -EPERM; 2355 2356 ptr = kmap(p); 2357 r = copy_from_user(ptr + off, buf, bytes); 2358 kunmap(p); 2359 if (r) 2360 return -EFAULT; 2361 2362 size -= bytes; 2363 *pos += bytes; 2364 result += bytes; 2365 } 2366 2367 return result; 2368 } 2369 2370 static const struct file_operations amdgpu_ttm_iomem_fops = { 2371 .owner = THIS_MODULE, 2372 .read = amdgpu_iomem_read, 2373 .write = amdgpu_iomem_write, 2374 .llseek = default_llseek 2375 }; 2376 2377 #endif 2378 2379 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2380 { 2381 #if defined(CONFIG_DEBUG_FS) 2382 struct drm_minor *minor = adev_to_drm(adev)->primary; 2383 struct dentry *root = minor->debugfs_root; 2384 2385 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2386 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2387 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2388 &amdgpu_ttm_iomem_fops); 2389 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2390 &amdgpu_mm_vram_table_fops); 2391 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2392 &amdgpu_mm_tt_table_fops); 2393 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2394 &amdgpu_mm_gds_table_fops); 2395 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2396 &amdgpu_mm_gws_table_fops); 2397 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2398 &amdgpu_mm_oa_table_fops); 2399 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2400 &amdgpu_ttm_page_pool_fops); 2401 #endif 2402 } 2403