1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/dma-buf.h> 42 #include <linux/sizes.h> 43 #include <linux/module.h> 44 45 #include <drm/drm_drv.h> 46 #include <drm/ttm/ttm_bo.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <drm/ttm/ttm_range_manager.h> 49 #include <drm/ttm/ttm_tt.h> 50 51 #include <drm/amdgpu_drm.h> 52 #include <drm/drm_drv.h> 53 54 #include "amdgpu.h" 55 #include "amdgpu_object.h" 56 #include "amdgpu_trace.h" 57 #include "amdgpu_amdkfd.h" 58 #include "amdgpu_sdma.h" 59 #include "amdgpu_ras.h" 60 #include "amdgpu_hmm.h" 61 #include "amdgpu_atomfirmware.h" 62 #include "amdgpu_res_cursor.h" 63 #include "bif/bif_4_1_d.h" 64 65 MODULE_IMPORT_NS(DMA_BUF); 66 67 #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) 68 69 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 70 struct ttm_tt *ttm, 71 struct ttm_resource *bo_mem); 72 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 73 struct ttm_tt *ttm); 74 75 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 76 unsigned int type, 77 uint64_t size_in_page) 78 { 79 return ttm_range_man_init(&adev->mman.bdev, type, 80 false, size_in_page); 81 } 82 83 /** 84 * amdgpu_evict_flags - Compute placement flags 85 * 86 * @bo: The buffer object to evict 87 * @placement: Possible destination(s) for evicted BO 88 * 89 * Fill in placement data when ttm_bo_evict() is called 90 */ 91 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 92 struct ttm_placement *placement) 93 { 94 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 95 struct amdgpu_bo *abo; 96 static const struct ttm_place placements = { 97 .fpfn = 0, 98 .lpfn = 0, 99 .mem_type = TTM_PL_SYSTEM, 100 .flags = 0 101 }; 102 103 /* Don't handle scatter gather BOs */ 104 if (bo->type == ttm_bo_type_sg) { 105 placement->num_placement = 0; 106 placement->num_busy_placement = 0; 107 return; 108 } 109 110 /* Object isn't an AMDGPU object so ignore */ 111 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 112 placement->placement = &placements; 113 placement->busy_placement = &placements; 114 placement->num_placement = 1; 115 placement->num_busy_placement = 1; 116 return; 117 } 118 119 abo = ttm_to_amdgpu_bo(bo); 120 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 121 placement->num_placement = 0; 122 placement->num_busy_placement = 0; 123 return; 124 } 125 126 switch (bo->resource->mem_type) { 127 case AMDGPU_PL_GDS: 128 case AMDGPU_PL_GWS: 129 case AMDGPU_PL_OA: 130 placement->num_placement = 0; 131 placement->num_busy_placement = 0; 132 return; 133 134 case TTM_PL_VRAM: 135 if (!adev->mman.buffer_funcs_enabled) { 136 /* Move to system memory */ 137 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 139 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 140 amdgpu_bo_in_cpu_visible_vram(abo)) { 141 142 /* Try evicting to the CPU inaccessible part of VRAM 143 * first, but only set GTT as busy placement, so this 144 * BO will be evicted to GTT rather than causing other 145 * BOs to be evicted from VRAM 146 */ 147 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 148 AMDGPU_GEM_DOMAIN_GTT | 149 AMDGPU_GEM_DOMAIN_CPU); 150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 151 abo->placements[0].lpfn = 0; 152 abo->placement.busy_placement = &abo->placements[1]; 153 abo->placement.num_busy_placement = 1; 154 } else { 155 /* Move to GTT memory */ 156 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 157 AMDGPU_GEM_DOMAIN_CPU); 158 } 159 break; 160 case TTM_PL_TT: 161 case AMDGPU_PL_PREEMPT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 /** 170 * amdgpu_ttm_map_buffer - Map memory into the GART windows 171 * @bo: buffer object to map 172 * @mem: memory object to map 173 * @mm_cur: range to map 174 * @window: which GART window to use 175 * @ring: DMA ring to use for the copy 176 * @tmz: if we should setup a TMZ enabled mapping 177 * @size: in number of bytes to map, out number of bytes mapped 178 * @addr: resulting address inside the MC address space 179 * 180 * Setup one of the GART windows to access a specific piece of memory or return 181 * the physical address for local memory. 182 */ 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 184 struct ttm_resource *mem, 185 struct amdgpu_res_cursor *mm_cur, 186 unsigned int window, struct amdgpu_ring *ring, 187 bool tmz, uint64_t *size, uint64_t *addr) 188 { 189 struct amdgpu_device *adev = ring->adev; 190 unsigned int offset, num_pages, num_dw, num_bytes; 191 uint64_t src_addr, dst_addr; 192 struct amdgpu_job *job; 193 void *cpu_addr; 194 uint64_t flags; 195 unsigned int i; 196 int r; 197 198 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 199 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 200 201 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT)) 202 return -EINVAL; 203 204 /* Map only what can't be accessed directly */ 205 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 206 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 207 mm_cur->start; 208 return 0; 209 } 210 211 212 /* 213 * If start begins at an offset inside the page, then adjust the size 214 * and addr accordingly 215 */ 216 offset = mm_cur->start & ~PAGE_MASK; 217 218 num_pages = PFN_UP(*size + offset); 219 num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE); 220 221 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 222 223 *addr = adev->gmc.gart_start; 224 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 225 AMDGPU_GPU_PAGE_SIZE; 226 *addr += offset; 227 228 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 229 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 230 231 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity, 232 AMDGPU_FENCE_OWNER_UNDEFINED, 233 num_dw * 4 + num_bytes, 234 AMDGPU_IB_POOL_DELAYED, &job); 235 if (r) 236 return r; 237 238 src_addr = num_dw * 4; 239 src_addr += job->ibs[0].gpu_addr; 240 241 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 242 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 243 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 244 dst_addr, num_bytes, false); 245 246 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 247 WARN_ON(job->ibs[0].length_dw > num_dw); 248 249 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 250 if (tmz) 251 flags |= AMDGPU_PTE_TMZ; 252 253 cpu_addr = &job->ibs[0].ptr[num_dw]; 254 255 if (mem->mem_type == TTM_PL_TT) { 256 dma_addr_t *dma_addr; 257 258 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 259 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 260 } else { 261 dma_addr_t dma_address; 262 263 dma_address = mm_cur->start; 264 dma_address += adev->vm_manager.vram_base_offset; 265 266 for (i = 0; i < num_pages; ++i) { 267 amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address, 268 flags, cpu_addr); 269 dma_address += PAGE_SIZE; 270 } 271 } 272 273 dma_fence_put(amdgpu_job_submit(job)); 274 return 0; 275 } 276 277 /** 278 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 279 * @adev: amdgpu device 280 * @src: buffer/address where to read from 281 * @dst: buffer/address where to write to 282 * @size: number of bytes to copy 283 * @tmz: if a secure copy should be used 284 * @resv: resv object to sync to 285 * @f: Returns the last fence if multiple jobs are submitted. 286 * 287 * The function copies @size bytes from {src->mem + src->offset} to 288 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 289 * move and different for a BO to BO copy. 290 * 291 */ 292 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 293 const struct amdgpu_copy_mem *src, 294 const struct amdgpu_copy_mem *dst, 295 uint64_t size, bool tmz, 296 struct dma_resv *resv, 297 struct dma_fence **f) 298 { 299 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 300 struct amdgpu_res_cursor src_mm, dst_mm; 301 struct dma_fence *fence = NULL; 302 int r = 0; 303 304 if (!adev->mman.buffer_funcs_enabled) { 305 DRM_ERROR("Trying to move memory with ring turned off.\n"); 306 return -EINVAL; 307 } 308 309 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 310 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 311 312 mutex_lock(&adev->mman.gtt_window_lock); 313 while (src_mm.remaining) { 314 uint64_t from, to, cur_size; 315 struct dma_fence *next; 316 317 /* Never copy more than 256MiB at once to avoid a timeout */ 318 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 319 320 /* Map src to window 0 and dst to window 1. */ 321 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 322 0, ring, tmz, &cur_size, &from); 323 if (r) 324 goto error; 325 326 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 327 1, ring, tmz, &cur_size, &to); 328 if (r) 329 goto error; 330 331 r = amdgpu_copy_buffer(ring, from, to, cur_size, 332 resv, &next, false, true, tmz); 333 if (r) 334 goto error; 335 336 dma_fence_put(fence); 337 fence = next; 338 339 amdgpu_res_next(&src_mm, cur_size); 340 amdgpu_res_next(&dst_mm, cur_size); 341 } 342 error: 343 mutex_unlock(&adev->mman.gtt_window_lock); 344 if (f) 345 *f = dma_fence_get(fence); 346 dma_fence_put(fence); 347 return r; 348 } 349 350 /* 351 * amdgpu_move_blit - Copy an entire buffer to another buffer 352 * 353 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 354 * help move buffers to and from VRAM. 355 */ 356 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 357 bool evict, 358 struct ttm_resource *new_mem, 359 struct ttm_resource *old_mem) 360 { 361 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 362 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 363 struct amdgpu_copy_mem src, dst; 364 struct dma_fence *fence = NULL; 365 int r; 366 367 src.bo = bo; 368 dst.bo = bo; 369 src.mem = old_mem; 370 dst.mem = new_mem; 371 src.offset = 0; 372 dst.offset = 0; 373 374 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 375 new_mem->size, 376 amdgpu_bo_encrypted(abo), 377 bo->base.resv, &fence); 378 if (r) 379 goto error; 380 381 /* clear the space being freed */ 382 if (old_mem->mem_type == TTM_PL_VRAM && 383 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 384 struct dma_fence *wipe_fence = NULL; 385 386 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence); 387 if (r) { 388 goto error; 389 } else if (wipe_fence) { 390 dma_fence_put(fence); 391 fence = wipe_fence; 392 } 393 } 394 395 /* Always block for VM page tables before committing the new location */ 396 if (bo->type == ttm_bo_type_kernel) 397 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 398 else 399 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 400 dma_fence_put(fence); 401 return r; 402 403 error: 404 if (fence) 405 dma_fence_wait(fence, false); 406 dma_fence_put(fence); 407 return r; 408 } 409 410 /* 411 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 412 * 413 * Called by amdgpu_bo_move() 414 */ 415 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 416 struct ttm_resource *mem) 417 { 418 u64 mem_size = (u64)mem->size; 419 struct amdgpu_res_cursor cursor; 420 u64 end; 421 422 if (mem->mem_type == TTM_PL_SYSTEM || 423 mem->mem_type == TTM_PL_TT) 424 return true; 425 if (mem->mem_type != TTM_PL_VRAM) 426 return false; 427 428 amdgpu_res_first(mem, 0, mem_size, &cursor); 429 end = cursor.start + cursor.size; 430 while (cursor.remaining) { 431 amdgpu_res_next(&cursor, cursor.size); 432 433 if (!cursor.remaining) 434 break; 435 436 /* ttm_resource_ioremap only supports contiguous memory */ 437 if (end != cursor.start) 438 return false; 439 440 end = cursor.start + cursor.size; 441 } 442 443 return end <= adev->gmc.visible_vram_size; 444 } 445 446 /* 447 * amdgpu_bo_move - Move a buffer object to a new memory location 448 * 449 * Called by ttm_bo_handle_move_mem() 450 */ 451 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 452 struct ttm_operation_ctx *ctx, 453 struct ttm_resource *new_mem, 454 struct ttm_place *hop) 455 { 456 struct amdgpu_device *adev; 457 struct amdgpu_bo *abo; 458 struct ttm_resource *old_mem = bo->resource; 459 int r; 460 461 if (new_mem->mem_type == TTM_PL_TT || 462 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 463 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 464 if (r) 465 return r; 466 } 467 468 abo = ttm_to_amdgpu_bo(bo); 469 adev = amdgpu_ttm_adev(bo->bdev); 470 471 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 472 bo->ttm == NULL)) { 473 ttm_bo_move_null(bo, new_mem); 474 goto out; 475 } 476 if (old_mem->mem_type == TTM_PL_SYSTEM && 477 (new_mem->mem_type == TTM_PL_TT || 478 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 479 ttm_bo_move_null(bo, new_mem); 480 goto out; 481 } 482 if ((old_mem->mem_type == TTM_PL_TT || 483 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 484 new_mem->mem_type == TTM_PL_SYSTEM) { 485 r = ttm_bo_wait_ctx(bo, ctx); 486 if (r) 487 return r; 488 489 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 490 ttm_resource_free(bo, &bo->resource); 491 ttm_bo_assign_mem(bo, new_mem); 492 goto out; 493 } 494 495 if (old_mem->mem_type == AMDGPU_PL_GDS || 496 old_mem->mem_type == AMDGPU_PL_GWS || 497 old_mem->mem_type == AMDGPU_PL_OA || 498 new_mem->mem_type == AMDGPU_PL_GDS || 499 new_mem->mem_type == AMDGPU_PL_GWS || 500 new_mem->mem_type == AMDGPU_PL_OA) { 501 /* Nothing to save here */ 502 ttm_bo_move_null(bo, new_mem); 503 goto out; 504 } 505 506 if (bo->type == ttm_bo_type_device && 507 new_mem->mem_type == TTM_PL_VRAM && 508 old_mem->mem_type != TTM_PL_VRAM) { 509 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 510 * accesses the BO after it's moved. 511 */ 512 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 513 } 514 515 if (adev->mman.buffer_funcs_enabled) { 516 if (((old_mem->mem_type == TTM_PL_SYSTEM && 517 new_mem->mem_type == TTM_PL_VRAM) || 518 (old_mem->mem_type == TTM_PL_VRAM && 519 new_mem->mem_type == TTM_PL_SYSTEM))) { 520 hop->fpfn = 0; 521 hop->lpfn = 0; 522 hop->mem_type = TTM_PL_TT; 523 hop->flags = TTM_PL_FLAG_TEMPORARY; 524 return -EMULTIHOP; 525 } 526 527 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 528 } else { 529 r = -ENODEV; 530 } 531 532 if (r) { 533 /* Check that all memory is CPU accessible */ 534 if (!amdgpu_mem_visible(adev, old_mem) || 535 !amdgpu_mem_visible(adev, new_mem)) { 536 pr_err("Move buffer fallback to memcpy unavailable\n"); 537 return r; 538 } 539 540 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 541 if (r) 542 return r; 543 } 544 545 out: 546 /* update statistics */ 547 atomic64_add(bo->base.size, &adev->num_bytes_moved); 548 amdgpu_bo_move_notify(bo, evict, new_mem); 549 return 0; 550 } 551 552 /* 553 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 554 * 555 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 556 */ 557 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 558 struct ttm_resource *mem) 559 { 560 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 561 size_t bus_size = (size_t)mem->size; 562 563 switch (mem->mem_type) { 564 case TTM_PL_SYSTEM: 565 /* system memory */ 566 return 0; 567 case TTM_PL_TT: 568 case AMDGPU_PL_PREEMPT: 569 break; 570 case TTM_PL_VRAM: 571 mem->bus.offset = mem->start << PAGE_SHIFT; 572 /* check if it's visible */ 573 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 574 return -EINVAL; 575 576 if (adev->mman.aper_base_kaddr && 577 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 578 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 579 mem->bus.offset; 580 581 mem->bus.offset += adev->gmc.aper_base; 582 mem->bus.is_iomem = true; 583 break; 584 default: 585 return -EINVAL; 586 } 587 return 0; 588 } 589 590 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 591 unsigned long page_offset) 592 { 593 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 594 struct amdgpu_res_cursor cursor; 595 596 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 597 &cursor); 598 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 599 } 600 601 /** 602 * amdgpu_ttm_domain_start - Returns GPU start address 603 * @adev: amdgpu device object 604 * @type: type of the memory 605 * 606 * Returns: 607 * GPU start address of a memory domain 608 */ 609 610 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 611 { 612 switch (type) { 613 case TTM_PL_TT: 614 return adev->gmc.gart_start; 615 case TTM_PL_VRAM: 616 return adev->gmc.vram_start; 617 } 618 619 return 0; 620 } 621 622 /* 623 * TTM backend functions. 624 */ 625 struct amdgpu_ttm_tt { 626 struct ttm_tt ttm; 627 struct drm_gem_object *gobj; 628 u64 offset; 629 uint64_t userptr; 630 struct task_struct *usertask; 631 uint32_t userflags; 632 bool bound; 633 int32_t pool_id; 634 }; 635 636 #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) 637 638 #ifdef CONFIG_DRM_AMDGPU_USERPTR 639 /* 640 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 641 * memory and start HMM tracking CPU page table update 642 * 643 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 644 * once afterwards to stop HMM tracking 645 */ 646 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, 647 struct hmm_range **range) 648 { 649 struct ttm_tt *ttm = bo->tbo.ttm; 650 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 651 unsigned long start = gtt->userptr; 652 struct vm_area_struct *vma; 653 struct mm_struct *mm; 654 bool readonly; 655 int r = 0; 656 657 /* Make sure get_user_pages_done() can cleanup gracefully */ 658 *range = NULL; 659 660 mm = bo->notifier.mm; 661 if (unlikely(!mm)) { 662 DRM_DEBUG_DRIVER("BO is not registered?\n"); 663 return -EFAULT; 664 } 665 666 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 667 return -ESRCH; 668 669 mmap_read_lock(mm); 670 vma = vma_lookup(mm, start); 671 if (unlikely(!vma)) { 672 r = -EFAULT; 673 goto out_unlock; 674 } 675 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 676 vma->vm_file)) { 677 r = -EPERM; 678 goto out_unlock; 679 } 680 681 readonly = amdgpu_ttm_tt_is_readonly(ttm); 682 r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages, 683 readonly, NULL, pages, range); 684 out_unlock: 685 mmap_read_unlock(mm); 686 if (r) 687 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 688 689 mmput(mm); 690 691 return r; 692 } 693 694 /* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations 695 */ 696 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 697 struct hmm_range *range) 698 { 699 struct amdgpu_ttm_tt *gtt = (void *)ttm; 700 701 if (gtt && gtt->userptr && range) 702 amdgpu_hmm_range_get_pages_done(range); 703 } 704 705 /* 706 * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change 707 * Check if the pages backing this ttm range have been invalidated 708 * 709 * Returns: true if pages are still valid 710 */ 711 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 712 struct hmm_range *range) 713 { 714 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 715 716 if (!gtt || !gtt->userptr || !range) 717 return false; 718 719 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 720 gtt->userptr, ttm->num_pages); 721 722 WARN_ONCE(!range->hmm_pfns, "No user pages to check\n"); 723 724 return !amdgpu_hmm_range_get_pages_done(range); 725 } 726 #endif 727 728 /* 729 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 730 * 731 * Called by amdgpu_cs_list_validate(). This creates the page list 732 * that backs user memory and will ultimately be mapped into the device 733 * address space. 734 */ 735 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 736 { 737 unsigned long i; 738 739 for (i = 0; i < ttm->num_pages; ++i) 740 ttm->pages[i] = pages ? pages[i] : NULL; 741 } 742 743 /* 744 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 745 * 746 * Called by amdgpu_ttm_backend_bind() 747 **/ 748 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 749 struct ttm_tt *ttm) 750 { 751 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 752 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 753 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 754 enum dma_data_direction direction = write ? 755 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 756 int r; 757 758 /* Allocate an SG array and squash pages into it */ 759 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 760 (u64)ttm->num_pages << PAGE_SHIFT, 761 GFP_KERNEL); 762 if (r) 763 goto release_sg; 764 765 /* Map SG to device */ 766 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 767 if (r) 768 goto release_sg; 769 770 /* convert SG to linear array of pages and dma addresses */ 771 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 772 ttm->num_pages); 773 774 return 0; 775 776 release_sg: 777 kfree(ttm->sg); 778 ttm->sg = NULL; 779 return r; 780 } 781 782 /* 783 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 784 */ 785 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 786 struct ttm_tt *ttm) 787 { 788 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 789 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 790 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 791 enum dma_data_direction direction = write ? 792 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 793 794 /* double check that we don't free the table twice */ 795 if (!ttm->sg || !ttm->sg->sgl) 796 return; 797 798 /* unmap the pages mapped to the device */ 799 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 800 sg_free_table(ttm->sg); 801 } 802 803 /* 804 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ... 805 * MQDn+CtrlStackn where n is the number of XCCs per partition. 806 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD 807 * and uses memory type default, UC. The rest of pages_per_xcc are 808 * Ctrl stack and modify their memory type to NC. 809 */ 810 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, 811 struct ttm_tt *ttm, uint64_t flags) 812 { 813 struct amdgpu_ttm_tt *gtt = (void *)ttm; 814 uint64_t total_pages = ttm->num_pages; 815 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); 816 uint64_t page_idx, pages_per_xcc; 817 int i; 818 uint64_t ctrl_flags = (flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 819 AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 820 821 pages_per_xcc = total_pages; 822 do_div(pages_per_xcc, num_xcc); 823 824 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { 825 /* MQD page: use default flags */ 826 amdgpu_gart_bind(adev, 827 gtt->offset + (page_idx << PAGE_SHIFT), 828 1, >t->ttm.dma_address[page_idx], flags); 829 /* 830 * Ctrl pages - modify the memory type to NC (ctrl_flags) from 831 * the second page of the BO onward. 832 */ 833 amdgpu_gart_bind(adev, 834 gtt->offset + ((page_idx + 1) << PAGE_SHIFT), 835 pages_per_xcc - 1, 836 >t->ttm.dma_address[page_idx + 1], 837 ctrl_flags); 838 } 839 } 840 841 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 842 struct ttm_buffer_object *tbo, 843 uint64_t flags) 844 { 845 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 846 struct ttm_tt *ttm = tbo->ttm; 847 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 848 849 if (amdgpu_bo_encrypted(abo)) 850 flags |= AMDGPU_PTE_TMZ; 851 852 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 853 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags); 854 } else { 855 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 856 gtt->ttm.dma_address, flags); 857 } 858 } 859 860 /* 861 * amdgpu_ttm_backend_bind - Bind GTT memory 862 * 863 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 864 * This handles binding GTT memory to the device address space. 865 */ 866 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 867 struct ttm_tt *ttm, 868 struct ttm_resource *bo_mem) 869 { 870 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 871 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 872 uint64_t flags; 873 int r; 874 875 if (!bo_mem) 876 return -EINVAL; 877 878 if (gtt->bound) 879 return 0; 880 881 if (gtt->userptr) { 882 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 883 if (r) { 884 DRM_ERROR("failed to pin userptr\n"); 885 return r; 886 } 887 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 888 if (!ttm->sg) { 889 struct dma_buf_attachment *attach; 890 struct sg_table *sgt; 891 892 attach = gtt->gobj->import_attach; 893 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 894 if (IS_ERR(sgt)) 895 return PTR_ERR(sgt); 896 897 ttm->sg = sgt; 898 } 899 900 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 901 ttm->num_pages); 902 } 903 904 if (!ttm->num_pages) { 905 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 906 ttm->num_pages, bo_mem, ttm); 907 } 908 909 if (bo_mem->mem_type != TTM_PL_TT || 910 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 911 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 912 return 0; 913 } 914 915 /* compute PTE flags relevant to this BO memory */ 916 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 917 918 /* bind pages into GART page tables */ 919 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 920 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 921 gtt->ttm.dma_address, flags); 922 gtt->bound = true; 923 return 0; 924 } 925 926 /* 927 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 928 * through AGP or GART aperture. 929 * 930 * If bo is accessible through AGP aperture, then use AGP aperture 931 * to access bo; otherwise allocate logical space in GART aperture 932 * and map bo to GART aperture. 933 */ 934 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 935 { 936 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 937 struct ttm_operation_ctx ctx = { false, false }; 938 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 939 struct ttm_placement placement; 940 struct ttm_place placements; 941 struct ttm_resource *tmp; 942 uint64_t addr, flags; 943 int r; 944 945 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 946 return 0; 947 948 addr = amdgpu_gmc_agp_addr(bo); 949 if (addr != AMDGPU_BO_INVALID_OFFSET) { 950 bo->resource->start = addr >> PAGE_SHIFT; 951 return 0; 952 } 953 954 /* allocate GART space */ 955 placement.num_placement = 1; 956 placement.placement = &placements; 957 placement.num_busy_placement = 1; 958 placement.busy_placement = &placements; 959 placements.fpfn = 0; 960 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 961 placements.mem_type = TTM_PL_TT; 962 placements.flags = bo->resource->placement; 963 964 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 965 if (unlikely(r)) 966 return r; 967 968 /* compute PTE flags for this buffer object */ 969 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 970 971 /* Bind pages */ 972 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 973 amdgpu_ttm_gart_bind(adev, bo, flags); 974 amdgpu_gart_invalidate_tlb(adev); 975 ttm_resource_free(bo, &bo->resource); 976 ttm_bo_assign_mem(bo, tmp); 977 978 return 0; 979 } 980 981 /* 982 * amdgpu_ttm_recover_gart - Rebind GTT pages 983 * 984 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 985 * rebind GTT pages during a GPU reset. 986 */ 987 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 988 { 989 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 990 uint64_t flags; 991 992 if (!tbo->ttm) 993 return; 994 995 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 996 amdgpu_ttm_gart_bind(adev, tbo, flags); 997 } 998 999 /* 1000 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1001 * 1002 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1003 * ttm_tt_destroy(). 1004 */ 1005 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1006 struct ttm_tt *ttm) 1007 { 1008 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1009 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1010 1011 /* if the pages have userptr pinning then clear that first */ 1012 if (gtt->userptr) { 1013 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1014 } else if (ttm->sg && gtt->gobj->import_attach) { 1015 struct dma_buf_attachment *attach; 1016 1017 attach = gtt->gobj->import_attach; 1018 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1019 ttm->sg = NULL; 1020 } 1021 1022 if (!gtt->bound) 1023 return; 1024 1025 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1026 return; 1027 1028 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1029 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1030 gtt->bound = false; 1031 } 1032 1033 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1034 struct ttm_tt *ttm) 1035 { 1036 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1037 1038 if (gtt->usertask) 1039 put_task_struct(gtt->usertask); 1040 1041 ttm_tt_fini(>t->ttm); 1042 kfree(gtt); 1043 } 1044 1045 /** 1046 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1047 * 1048 * @bo: The buffer object to create a GTT ttm_tt object around 1049 * @page_flags: Page flags to be added to the ttm_tt object 1050 * 1051 * Called by ttm_tt_create(). 1052 */ 1053 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1054 uint32_t page_flags) 1055 { 1056 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1057 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1058 struct amdgpu_ttm_tt *gtt; 1059 enum ttm_caching caching; 1060 1061 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1062 if (!gtt) 1063 return NULL; 1064 1065 gtt->gobj = &bo->base; 1066 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) 1067 gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 1068 else 1069 gtt->pool_id = abo->xcp_id; 1070 1071 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1072 caching = ttm_write_combined; 1073 else 1074 caching = ttm_cached; 1075 1076 /* allocate space for the uninitialized page entries */ 1077 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1078 kfree(gtt); 1079 return NULL; 1080 } 1081 return >t->ttm; 1082 } 1083 1084 /* 1085 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1086 * 1087 * Map the pages of a ttm_tt object to an address space visible 1088 * to the underlying device. 1089 */ 1090 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1091 struct ttm_tt *ttm, 1092 struct ttm_operation_ctx *ctx) 1093 { 1094 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1095 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1096 struct ttm_pool *pool; 1097 pgoff_t i; 1098 int ret; 1099 1100 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1101 if (gtt->userptr) { 1102 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1103 if (!ttm->sg) 1104 return -ENOMEM; 1105 return 0; 1106 } 1107 1108 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1109 return 0; 1110 1111 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1112 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1113 else 1114 pool = &adev->mman.bdev.pool; 1115 ret = ttm_pool_alloc(pool, ttm, ctx); 1116 if (ret) 1117 return ret; 1118 1119 for (i = 0; i < ttm->num_pages; ++i) 1120 ttm->pages[i]->mapping = bdev->dev_mapping; 1121 1122 return 0; 1123 } 1124 1125 /* 1126 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1127 * 1128 * Unmaps pages of a ttm_tt object from the device address space and 1129 * unpopulates the page array backing it. 1130 */ 1131 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1132 struct ttm_tt *ttm) 1133 { 1134 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1135 struct amdgpu_device *adev; 1136 struct ttm_pool *pool; 1137 pgoff_t i; 1138 1139 amdgpu_ttm_backend_unbind(bdev, ttm); 1140 1141 if (gtt->userptr) { 1142 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1143 kfree(ttm->sg); 1144 ttm->sg = NULL; 1145 return; 1146 } 1147 1148 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1149 return; 1150 1151 for (i = 0; i < ttm->num_pages; ++i) 1152 ttm->pages[i]->mapping = NULL; 1153 1154 adev = amdgpu_ttm_adev(bdev); 1155 1156 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1157 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1158 else 1159 pool = &adev->mman.bdev.pool; 1160 1161 return ttm_pool_free(pool, ttm); 1162 } 1163 1164 /** 1165 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current 1166 * task 1167 * 1168 * @tbo: The ttm_buffer_object that contains the userptr 1169 * @user_addr: The returned value 1170 */ 1171 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 1172 uint64_t *user_addr) 1173 { 1174 struct amdgpu_ttm_tt *gtt; 1175 1176 if (!tbo->ttm) 1177 return -EINVAL; 1178 1179 gtt = (void *)tbo->ttm; 1180 *user_addr = gtt->userptr; 1181 return 0; 1182 } 1183 1184 /** 1185 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1186 * task 1187 * 1188 * @bo: The ttm_buffer_object to bind this userptr to 1189 * @addr: The address in the current tasks VM space to use 1190 * @flags: Requirements of userptr object. 1191 * 1192 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to 1193 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to 1194 * initialize GPU VM for a KFD process. 1195 */ 1196 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1197 uint64_t addr, uint32_t flags) 1198 { 1199 struct amdgpu_ttm_tt *gtt; 1200 1201 if (!bo->ttm) { 1202 /* TODO: We want a separate TTM object type for userptrs */ 1203 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1204 if (bo->ttm == NULL) 1205 return -ENOMEM; 1206 } 1207 1208 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1209 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1210 1211 gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 1212 gtt->userptr = addr; 1213 gtt->userflags = flags; 1214 1215 if (gtt->usertask) 1216 put_task_struct(gtt->usertask); 1217 gtt->usertask = current->group_leader; 1218 get_task_struct(gtt->usertask); 1219 1220 return 0; 1221 } 1222 1223 /* 1224 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1225 */ 1226 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1227 { 1228 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1229 1230 if (gtt == NULL) 1231 return NULL; 1232 1233 if (gtt->usertask == NULL) 1234 return NULL; 1235 1236 return gtt->usertask->mm; 1237 } 1238 1239 /* 1240 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1241 * address range for the current task. 1242 * 1243 */ 1244 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1245 unsigned long end, unsigned long *userptr) 1246 { 1247 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1248 unsigned long size; 1249 1250 if (gtt == NULL || !gtt->userptr) 1251 return false; 1252 1253 /* Return false if no part of the ttm_tt object lies within 1254 * the range 1255 */ 1256 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1257 if (gtt->userptr > end || gtt->userptr + size <= start) 1258 return false; 1259 1260 if (userptr) 1261 *userptr = gtt->userptr; 1262 return true; 1263 } 1264 1265 /* 1266 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1267 */ 1268 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1269 { 1270 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1271 1272 if (gtt == NULL || !gtt->userptr) 1273 return false; 1274 1275 return true; 1276 } 1277 1278 /* 1279 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1280 */ 1281 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1282 { 1283 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1284 1285 if (gtt == NULL) 1286 return false; 1287 1288 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1289 } 1290 1291 /** 1292 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1293 * 1294 * @ttm: The ttm_tt object to compute the flags for 1295 * @mem: The memory registry backing this ttm_tt object 1296 * 1297 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1298 */ 1299 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1300 { 1301 uint64_t flags = 0; 1302 1303 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1304 flags |= AMDGPU_PTE_VALID; 1305 1306 if (mem && (mem->mem_type == TTM_PL_TT || 1307 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1308 flags |= AMDGPU_PTE_SYSTEM; 1309 1310 if (ttm->caching == ttm_cached) 1311 flags |= AMDGPU_PTE_SNOOPED; 1312 } 1313 1314 if (mem && mem->mem_type == TTM_PL_VRAM && 1315 mem->bus.caching == ttm_cached) 1316 flags |= AMDGPU_PTE_SNOOPED; 1317 1318 return flags; 1319 } 1320 1321 /** 1322 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1323 * 1324 * @adev: amdgpu_device pointer 1325 * @ttm: The ttm_tt object to compute the flags for 1326 * @mem: The memory registry backing this ttm_tt object 1327 * 1328 * Figure out the flags to use for a VM PTE (Page Table Entry). 1329 */ 1330 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1331 struct ttm_resource *mem) 1332 { 1333 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1334 1335 flags |= adev->gart.gart_pte_flags; 1336 flags |= AMDGPU_PTE_READABLE; 1337 1338 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1339 flags |= AMDGPU_PTE_WRITEABLE; 1340 1341 return flags; 1342 } 1343 1344 /* 1345 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1346 * object. 1347 * 1348 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1349 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1350 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1351 * used to clean out a memory space. 1352 */ 1353 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1354 const struct ttm_place *place) 1355 { 1356 struct dma_resv_iter resv_cursor; 1357 struct dma_fence *f; 1358 1359 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1360 return ttm_bo_eviction_valuable(bo, place); 1361 1362 /* Swapout? */ 1363 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1364 return true; 1365 1366 if (bo->type == ttm_bo_type_kernel && 1367 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1368 return false; 1369 1370 /* If bo is a KFD BO, check if the bo belongs to the current process. 1371 * If true, then return false as any KFD process needs all its BOs to 1372 * be resident to run successfully 1373 */ 1374 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, 1375 DMA_RESV_USAGE_BOOKKEEP, f) { 1376 if (amdkfd_fence_check_mm(f, current->mm)) 1377 return false; 1378 } 1379 1380 /* Preemptible BOs don't own system resources managed by the 1381 * driver (pages, VRAM, GART space). They point to resources 1382 * owned by someone else (e.g. pageable memory in user mode 1383 * or a DMABuf). They are used in a preemptible context so we 1384 * can guarantee no deadlocks and good QoS in case of MMU 1385 * notifiers or DMABuf move notifiers from the resource owner. 1386 */ 1387 if (bo->resource->mem_type == AMDGPU_PL_PREEMPT) 1388 return false; 1389 1390 if (bo->resource->mem_type == TTM_PL_TT && 1391 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1392 return false; 1393 1394 return ttm_bo_eviction_valuable(bo, place); 1395 } 1396 1397 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1398 void *buf, size_t size, bool write) 1399 { 1400 while (size) { 1401 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1402 uint64_t bytes = 4 - (pos & 0x3); 1403 uint32_t shift = (pos & 0x3) * 8; 1404 uint32_t mask = 0xffffffff << shift; 1405 uint32_t value = 0; 1406 1407 if (size < bytes) { 1408 mask &= 0xffffffff >> (bytes - size) * 8; 1409 bytes = size; 1410 } 1411 1412 if (mask != 0xffffffff) { 1413 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1414 if (write) { 1415 value &= ~mask; 1416 value |= (*(uint32_t *)buf << shift) & mask; 1417 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1418 } else { 1419 value = (value & mask) >> shift; 1420 memcpy(buf, &value, bytes); 1421 } 1422 } else { 1423 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1424 } 1425 1426 pos += bytes; 1427 buf += bytes; 1428 size -= bytes; 1429 } 1430 } 1431 1432 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1433 unsigned long offset, void *buf, 1434 int len, int write) 1435 { 1436 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1437 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1438 struct amdgpu_res_cursor src_mm; 1439 struct amdgpu_job *job; 1440 struct dma_fence *fence; 1441 uint64_t src_addr, dst_addr; 1442 unsigned int num_dw; 1443 int r, idx; 1444 1445 if (len != PAGE_SIZE) 1446 return -EINVAL; 1447 1448 if (!adev->mman.sdma_access_ptr) 1449 return -EACCES; 1450 1451 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1452 return -ENODEV; 1453 1454 if (write) 1455 memcpy(adev->mman.sdma_access_ptr, buf, len); 1456 1457 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1458 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity, 1459 AMDGPU_FENCE_OWNER_UNDEFINED, 1460 num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1461 &job); 1462 if (r) 1463 goto out; 1464 1465 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1466 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + 1467 src_mm.start; 1468 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1469 if (write) 1470 swap(src_addr, dst_addr); 1471 1472 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, 1473 PAGE_SIZE, false); 1474 1475 amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); 1476 WARN_ON(job->ibs[0].length_dw > num_dw); 1477 1478 fence = amdgpu_job_submit(job); 1479 1480 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1481 r = -ETIMEDOUT; 1482 dma_fence_put(fence); 1483 1484 if (!(r || write)) 1485 memcpy(buf, adev->mman.sdma_access_ptr, len); 1486 out: 1487 drm_dev_exit(idx); 1488 return r; 1489 } 1490 1491 /** 1492 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1493 * 1494 * @bo: The buffer object to read/write 1495 * @offset: Offset into buffer object 1496 * @buf: Secondary buffer to write/read from 1497 * @len: Length in bytes of access 1498 * @write: true if writing 1499 * 1500 * This is used to access VRAM that backs a buffer object via MMIO 1501 * access for debugging purposes. 1502 */ 1503 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1504 unsigned long offset, void *buf, int len, 1505 int write) 1506 { 1507 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1508 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1509 struct amdgpu_res_cursor cursor; 1510 int ret = 0; 1511 1512 if (bo->resource->mem_type != TTM_PL_VRAM) 1513 return -EIO; 1514 1515 if (amdgpu_device_has_timeouts_enabled(adev) && 1516 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1517 return len; 1518 1519 amdgpu_res_first(bo->resource, offset, len, &cursor); 1520 while (cursor.remaining) { 1521 size_t count, size = cursor.size; 1522 loff_t pos = cursor.start; 1523 1524 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1525 size -= count; 1526 if (size) { 1527 /* using MM to access rest vram and handle un-aligned address */ 1528 pos += count; 1529 buf += count; 1530 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1531 } 1532 1533 ret += cursor.size; 1534 buf += cursor.size; 1535 amdgpu_res_next(&cursor, cursor.size); 1536 } 1537 1538 return ret; 1539 } 1540 1541 static void 1542 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1543 { 1544 amdgpu_bo_move_notify(bo, false, NULL); 1545 } 1546 1547 static struct ttm_device_funcs amdgpu_bo_driver = { 1548 .ttm_tt_create = &amdgpu_ttm_tt_create, 1549 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1550 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1551 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1552 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1553 .evict_flags = &amdgpu_evict_flags, 1554 .move = &amdgpu_bo_move, 1555 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1556 .release_notify = &amdgpu_bo_release_notify, 1557 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1558 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1559 .access_memory = &amdgpu_ttm_access_memory, 1560 }; 1561 1562 /* 1563 * Firmware Reservation functions 1564 */ 1565 /** 1566 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1567 * 1568 * @adev: amdgpu_device pointer 1569 * 1570 * free fw reserved vram if it has been reserved. 1571 */ 1572 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1573 { 1574 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1575 NULL, &adev->mman.fw_vram_usage_va); 1576 } 1577 1578 /* 1579 * Driver Reservation functions 1580 */ 1581 /** 1582 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram 1583 * 1584 * @adev: amdgpu_device pointer 1585 * 1586 * free drv reserved vram if it has been reserved. 1587 */ 1588 static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev) 1589 { 1590 amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo, 1591 NULL, 1592 &adev->mman.drv_vram_usage_va); 1593 } 1594 1595 /** 1596 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1597 * 1598 * @adev: amdgpu_device pointer 1599 * 1600 * create bo vram reservation from fw. 1601 */ 1602 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1603 { 1604 uint64_t vram_size = adev->gmc.visible_vram_size; 1605 1606 adev->mman.fw_vram_usage_va = NULL; 1607 adev->mman.fw_vram_usage_reserved_bo = NULL; 1608 1609 if (adev->mman.fw_vram_usage_size == 0 || 1610 adev->mman.fw_vram_usage_size > vram_size) 1611 return 0; 1612 1613 return amdgpu_bo_create_kernel_at(adev, 1614 adev->mman.fw_vram_usage_start_offset, 1615 adev->mman.fw_vram_usage_size, 1616 &adev->mman.fw_vram_usage_reserved_bo, 1617 &adev->mman.fw_vram_usage_va); 1618 } 1619 1620 /** 1621 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver 1622 * 1623 * @adev: amdgpu_device pointer 1624 * 1625 * create bo vram reservation from drv. 1626 */ 1627 static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev) 1628 { 1629 u64 vram_size = adev->gmc.visible_vram_size; 1630 1631 adev->mman.drv_vram_usage_va = NULL; 1632 adev->mman.drv_vram_usage_reserved_bo = NULL; 1633 1634 if (adev->mman.drv_vram_usage_size == 0 || 1635 adev->mman.drv_vram_usage_size > vram_size) 1636 return 0; 1637 1638 return amdgpu_bo_create_kernel_at(adev, 1639 adev->mman.drv_vram_usage_start_offset, 1640 adev->mman.drv_vram_usage_size, 1641 &adev->mman.drv_vram_usage_reserved_bo, 1642 &adev->mman.drv_vram_usage_va); 1643 } 1644 1645 /* 1646 * Memoy training reservation functions 1647 */ 1648 1649 /** 1650 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1651 * 1652 * @adev: amdgpu_device pointer 1653 * 1654 * free memory training reserved vram if it has been reserved. 1655 */ 1656 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1657 { 1658 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1659 1660 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1661 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1662 ctx->c2p_bo = NULL; 1663 1664 return 0; 1665 } 1666 1667 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev, 1668 uint32_t reserve_size) 1669 { 1670 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1671 1672 memset(ctx, 0, sizeof(*ctx)); 1673 1674 ctx->c2p_train_data_offset = 1675 ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1676 ctx->p2c_train_data_offset = 1677 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1678 ctx->train_data_size = 1679 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1680 1681 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1682 ctx->train_data_size, 1683 ctx->p2c_train_data_offset, 1684 ctx->c2p_train_data_offset); 1685 } 1686 1687 /* 1688 * reserve TMR memory at the top of VRAM which holds 1689 * IP Discovery data and is protected by PSP. 1690 */ 1691 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1692 { 1693 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1694 bool mem_train_support = false; 1695 uint32_t reserve_size = 0; 1696 int ret; 1697 1698 if (!amdgpu_sriov_vf(adev)) { 1699 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1700 mem_train_support = true; 1701 else 1702 DRM_DEBUG("memory training does not support!\n"); 1703 } 1704 1705 /* 1706 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1707 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1708 * 1709 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1710 * discovery data and G6 memory training data respectively 1711 */ 1712 if (adev->bios) 1713 reserve_size = 1714 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1715 if (!reserve_size) 1716 reserve_size = DISCOVERY_TMR_OFFSET; 1717 1718 if (mem_train_support) { 1719 /* reserve vram for mem train according to TMR location */ 1720 amdgpu_ttm_training_data_block_init(adev, reserve_size); 1721 ret = amdgpu_bo_create_kernel_at(adev, 1722 ctx->c2p_train_data_offset, 1723 ctx->train_data_size, 1724 &ctx->c2p_bo, 1725 NULL); 1726 if (ret) { 1727 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1728 amdgpu_ttm_training_reserve_vram_fini(adev); 1729 return ret; 1730 } 1731 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1732 } 1733 1734 if (!adev->gmc.is_app_apu) { 1735 ret = amdgpu_bo_create_kernel_at( 1736 adev, adev->gmc.real_vram_size - reserve_size, 1737 reserve_size, &adev->mman.fw_reserved_memory, NULL); 1738 if (ret) { 1739 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1740 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, 1741 NULL, NULL); 1742 return ret; 1743 } 1744 } else { 1745 DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n"); 1746 } 1747 1748 return 0; 1749 } 1750 1751 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) 1752 { 1753 int i; 1754 1755 if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions) 1756 return 0; 1757 1758 adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions, 1759 sizeof(*adev->mman.ttm_pools), 1760 GFP_KERNEL); 1761 if (!adev->mman.ttm_pools) 1762 return -ENOMEM; 1763 1764 for (i = 0; i < adev->gmc.num_mem_partitions; i++) { 1765 ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev, 1766 adev->gmc.mem_partitions[i].numa.node, 1767 false, false); 1768 } 1769 return 0; 1770 } 1771 1772 static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) 1773 { 1774 int i; 1775 1776 if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools) 1777 return; 1778 1779 for (i = 0; i < adev->gmc.num_mem_partitions; i++) 1780 ttm_pool_fini(&adev->mman.ttm_pools[i]); 1781 1782 kfree(adev->mman.ttm_pools); 1783 adev->mman.ttm_pools = NULL; 1784 } 1785 1786 /* 1787 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1788 * gtt/vram related fields. 1789 * 1790 * This initializes all of the memory space pools that the TTM layer 1791 * will need such as the GTT space (system memory mapped to the device), 1792 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1793 * can be mapped per VMID. 1794 */ 1795 int amdgpu_ttm_init(struct amdgpu_device *adev) 1796 { 1797 uint64_t gtt_size; 1798 int r; 1799 1800 mutex_init(&adev->mman.gtt_window_lock); 1801 1802 /* No others user of address space so set it to 0 */ 1803 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1804 adev_to_drm(adev)->anon_inode->i_mapping, 1805 adev_to_drm(adev)->vma_offset_manager, 1806 adev->need_swiotlb, 1807 dma_addressing_limited(adev->dev)); 1808 if (r) { 1809 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1810 return r; 1811 } 1812 1813 r = amdgpu_ttm_pools_init(adev); 1814 if (r) { 1815 DRM_ERROR("failed to init ttm pools(%d).\n", r); 1816 return r; 1817 } 1818 adev->mman.initialized = true; 1819 1820 /* Initialize VRAM pool with all of VRAM divided into pages */ 1821 r = amdgpu_vram_mgr_init(adev); 1822 if (r) { 1823 DRM_ERROR("Failed initializing VRAM heap.\n"); 1824 return r; 1825 } 1826 1827 /* Change the size here instead of the init above so only lpfn is affected */ 1828 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1829 #ifdef CONFIG_64BIT 1830 #ifdef CONFIG_X86 1831 if (adev->gmc.xgmi.connected_to_cpu) 1832 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1833 adev->gmc.visible_vram_size); 1834 1835 else if (adev->gmc.is_app_apu) 1836 DRM_DEBUG_DRIVER( 1837 "No need to ioremap when real vram size is 0\n"); 1838 else 1839 #endif 1840 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1841 adev->gmc.visible_vram_size); 1842 #endif 1843 1844 /* 1845 *The reserved vram for firmware must be pinned to the specified 1846 *place on the VRAM, so reserve it early. 1847 */ 1848 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1849 if (r) 1850 return r; 1851 1852 /* 1853 *The reserved vram for driver must be pinned to the specified 1854 *place on the VRAM, so reserve it early. 1855 */ 1856 r = amdgpu_ttm_drv_reserve_vram_init(adev); 1857 if (r) 1858 return r; 1859 1860 /* 1861 * only NAVI10 and onwards ASIC support for IP discovery. 1862 * If IP discovery enabled, a block of memory should be 1863 * reserved for IP discovey. 1864 */ 1865 if (adev->mman.discovery_bin) { 1866 r = amdgpu_ttm_reserve_tmr(adev); 1867 if (r) 1868 return r; 1869 } 1870 1871 /* allocate memory as required for VGA 1872 * This is used for VGA emulation and pre-OS scanout buffers to 1873 * avoid display artifacts while transitioning between pre-OS 1874 * and driver. 1875 */ 1876 if (!adev->gmc.is_app_apu) { 1877 r = amdgpu_bo_create_kernel_at(adev, 0, 1878 adev->mman.stolen_vga_size, 1879 &adev->mman.stolen_vga_memory, 1880 NULL); 1881 if (r) 1882 return r; 1883 1884 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1885 adev->mman.stolen_extended_size, 1886 &adev->mman.stolen_extended_memory, 1887 NULL); 1888 1889 if (r) 1890 return r; 1891 1892 r = amdgpu_bo_create_kernel_at(adev, 1893 adev->mman.stolen_reserved_offset, 1894 adev->mman.stolen_reserved_size, 1895 &adev->mman.stolen_reserved_memory, 1896 NULL); 1897 if (r) 1898 return r; 1899 } else { 1900 DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n"); 1901 } 1902 1903 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1904 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024))); 1905 1906 /* Compute GTT size, either based on TTM limit 1907 * or whatever the user passed on module init. 1908 */ 1909 if (amdgpu_gtt_size == -1) 1910 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT; 1911 else 1912 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1913 1914 /* Initialize GTT memory pool */ 1915 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1916 if (r) { 1917 DRM_ERROR("Failed initializing GTT heap.\n"); 1918 return r; 1919 } 1920 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1921 (unsigned int)(gtt_size / (1024 * 1024))); 1922 1923 /* Initialize preemptible memory pool */ 1924 r = amdgpu_preempt_mgr_init(adev); 1925 if (r) { 1926 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1927 return r; 1928 } 1929 1930 /* Initialize various on-chip memory pools */ 1931 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1932 if (r) { 1933 DRM_ERROR("Failed initializing GDS heap.\n"); 1934 return r; 1935 } 1936 1937 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1938 if (r) { 1939 DRM_ERROR("Failed initializing gws heap.\n"); 1940 return r; 1941 } 1942 1943 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1944 if (r) { 1945 DRM_ERROR("Failed initializing oa heap.\n"); 1946 return r; 1947 } 1948 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1949 AMDGPU_GEM_DOMAIN_GTT, 1950 &adev->mman.sdma_access_bo, NULL, 1951 &adev->mman.sdma_access_ptr)) 1952 DRM_WARN("Debug VRAM access will use slowpath MM access\n"); 1953 1954 return 0; 1955 } 1956 1957 /* 1958 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1959 */ 1960 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1961 { 1962 int idx; 1963 1964 if (!adev->mman.initialized) 1965 return; 1966 1967 amdgpu_ttm_pools_fini(adev); 1968 1969 amdgpu_ttm_training_reserve_vram_fini(adev); 1970 /* return the stolen vga memory back to VRAM */ 1971 if (!adev->gmc.is_app_apu) { 1972 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1973 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1974 /* return the FW reserved memory back to VRAM */ 1975 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, 1976 NULL); 1977 if (adev->mman.stolen_reserved_size) 1978 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1979 NULL, NULL); 1980 } 1981 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 1982 &adev->mman.sdma_access_ptr); 1983 amdgpu_ttm_fw_reserve_vram_fini(adev); 1984 amdgpu_ttm_drv_reserve_vram_fini(adev); 1985 1986 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1987 1988 if (adev->mman.aper_base_kaddr) 1989 iounmap(adev->mman.aper_base_kaddr); 1990 adev->mman.aper_base_kaddr = NULL; 1991 1992 drm_dev_exit(idx); 1993 } 1994 1995 amdgpu_vram_mgr_fini(adev); 1996 amdgpu_gtt_mgr_fini(adev); 1997 amdgpu_preempt_mgr_fini(adev); 1998 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1999 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2000 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2001 ttm_device_fini(&adev->mman.bdev); 2002 adev->mman.initialized = false; 2003 DRM_INFO("amdgpu: ttm finalized\n"); 2004 } 2005 2006 /** 2007 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2008 * 2009 * @adev: amdgpu_device pointer 2010 * @enable: true when we can use buffer functions. 2011 * 2012 * Enable/disable use of buffer functions during suspend/resume. This should 2013 * only be called at bootup or when userspace isn't running. 2014 */ 2015 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2016 { 2017 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2018 uint64_t size; 2019 int r; 2020 2021 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 2022 adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu) 2023 return; 2024 2025 if (enable) { 2026 struct amdgpu_ring *ring; 2027 struct drm_gpu_scheduler *sched; 2028 2029 ring = adev->mman.buffer_funcs_ring; 2030 sched = &ring->sched; 2031 r = drm_sched_entity_init(&adev->mman.entity, 2032 DRM_SCHED_PRIORITY_KERNEL, &sched, 2033 1, NULL); 2034 if (r) { 2035 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2036 r); 2037 return; 2038 } 2039 } else { 2040 drm_sched_entity_destroy(&adev->mman.entity); 2041 dma_fence_put(man->move); 2042 man->move = NULL; 2043 } 2044 2045 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2046 if (enable) 2047 size = adev->gmc.real_vram_size; 2048 else 2049 size = adev->gmc.visible_vram_size; 2050 man->size = size; 2051 adev->mman.buffer_funcs_enabled = enable; 2052 } 2053 2054 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, 2055 bool direct_submit, 2056 unsigned int num_dw, 2057 struct dma_resv *resv, 2058 bool vm_needs_flush, 2059 struct amdgpu_job **job) 2060 { 2061 enum amdgpu_ib_pool_type pool = direct_submit ? 2062 AMDGPU_IB_POOL_DIRECT : 2063 AMDGPU_IB_POOL_DELAYED; 2064 int r; 2065 2066 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity, 2067 AMDGPU_FENCE_OWNER_UNDEFINED, 2068 num_dw * 4, pool, job); 2069 if (r) 2070 return r; 2071 2072 if (vm_needs_flush) { 2073 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 2074 adev->gmc.pdb0_bo : 2075 adev->gart.bo); 2076 (*job)->vm_needs_flush = true; 2077 } 2078 if (!resv) 2079 return 0; 2080 2081 return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, 2082 DMA_RESV_USAGE_BOOKKEEP); 2083 } 2084 2085 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2086 uint64_t dst_offset, uint32_t byte_count, 2087 struct dma_resv *resv, 2088 struct dma_fence **fence, bool direct_submit, 2089 bool vm_needs_flush, bool tmz) 2090 { 2091 struct amdgpu_device *adev = ring->adev; 2092 unsigned int num_loops, num_dw; 2093 struct amdgpu_job *job; 2094 uint32_t max_bytes; 2095 unsigned int i; 2096 int r; 2097 2098 if (!direct_submit && !ring->sched.ready) { 2099 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2100 return -EINVAL; 2101 } 2102 2103 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2104 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2105 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2106 r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, 2107 resv, vm_needs_flush, &job); 2108 if (r) 2109 return r; 2110 2111 for (i = 0; i < num_loops; i++) { 2112 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2113 2114 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2115 dst_offset, cur_size_in_bytes, tmz); 2116 2117 src_offset += cur_size_in_bytes; 2118 dst_offset += cur_size_in_bytes; 2119 byte_count -= cur_size_in_bytes; 2120 } 2121 2122 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2123 WARN_ON(job->ibs[0].length_dw > num_dw); 2124 if (direct_submit) 2125 r = amdgpu_job_submit_direct(job, ring, fence); 2126 else 2127 *fence = amdgpu_job_submit(job); 2128 if (r) 2129 goto error_free; 2130 2131 return r; 2132 2133 error_free: 2134 amdgpu_job_free(job); 2135 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2136 return r; 2137 } 2138 2139 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, 2140 uint64_t dst_addr, uint32_t byte_count, 2141 struct dma_resv *resv, 2142 struct dma_fence **fence, 2143 bool vm_needs_flush) 2144 { 2145 struct amdgpu_device *adev = ring->adev; 2146 unsigned int num_loops, num_dw; 2147 struct amdgpu_job *job; 2148 uint32_t max_bytes; 2149 unsigned int i; 2150 int r; 2151 2152 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2153 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); 2154 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); 2155 r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, 2156 &job); 2157 if (r) 2158 return r; 2159 2160 for (i = 0; i < num_loops; i++) { 2161 uint32_t cur_size = min(byte_count, max_bytes); 2162 2163 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2164 cur_size); 2165 2166 dst_addr += cur_size; 2167 byte_count -= cur_size; 2168 } 2169 2170 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2171 WARN_ON(job->ibs[0].length_dw > num_dw); 2172 *fence = amdgpu_job_submit(job); 2173 return 0; 2174 } 2175 2176 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2177 uint32_t src_data, 2178 struct dma_resv *resv, 2179 struct dma_fence **f) 2180 { 2181 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2182 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2183 struct dma_fence *fence = NULL; 2184 struct amdgpu_res_cursor dst; 2185 int r; 2186 2187 if (!adev->mman.buffer_funcs_enabled) { 2188 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2189 return -EINVAL; 2190 } 2191 2192 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); 2193 2194 mutex_lock(&adev->mman.gtt_window_lock); 2195 while (dst.remaining) { 2196 struct dma_fence *next; 2197 uint64_t cur_size, to; 2198 2199 /* Never fill more than 256MiB at once to avoid timeouts */ 2200 cur_size = min(dst.size, 256ULL << 20); 2201 2202 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst, 2203 1, ring, false, &cur_size, &to); 2204 if (r) 2205 goto error; 2206 2207 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, 2208 &next, true); 2209 if (r) 2210 goto error; 2211 2212 dma_fence_put(fence); 2213 fence = next; 2214 2215 amdgpu_res_next(&dst, cur_size); 2216 } 2217 error: 2218 mutex_unlock(&adev->mman.gtt_window_lock); 2219 if (f) 2220 *f = dma_fence_get(fence); 2221 dma_fence_put(fence); 2222 return r; 2223 } 2224 2225 /** 2226 * amdgpu_ttm_evict_resources - evict memory buffers 2227 * @adev: amdgpu device object 2228 * @mem_type: evicted BO's memory type 2229 * 2230 * Evicts all @mem_type buffers on the lru list of the memory type. 2231 * 2232 * Returns: 2233 * 0 for success or a negative error code on failure. 2234 */ 2235 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2236 { 2237 struct ttm_resource_manager *man; 2238 2239 switch (mem_type) { 2240 case TTM_PL_VRAM: 2241 case TTM_PL_TT: 2242 case AMDGPU_PL_GWS: 2243 case AMDGPU_PL_GDS: 2244 case AMDGPU_PL_OA: 2245 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2246 break; 2247 default: 2248 DRM_ERROR("Trying to evict invalid memory type\n"); 2249 return -EINVAL; 2250 } 2251 2252 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2253 } 2254 2255 #if defined(CONFIG_DEBUG_FS) 2256 2257 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2258 { 2259 struct amdgpu_device *adev = m->private; 2260 2261 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2262 } 2263 2264 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2265 2266 /* 2267 * amdgpu_ttm_vram_read - Linear read access to VRAM 2268 * 2269 * Accesses VRAM via MMIO for debugging purposes. 2270 */ 2271 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2272 size_t size, loff_t *pos) 2273 { 2274 struct amdgpu_device *adev = file_inode(f)->i_private; 2275 ssize_t result = 0; 2276 2277 if (size & 0x3 || *pos & 0x3) 2278 return -EINVAL; 2279 2280 if (*pos >= adev->gmc.mc_vram_size) 2281 return -ENXIO; 2282 2283 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2284 while (size) { 2285 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2286 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2287 2288 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2289 if (copy_to_user(buf, value, bytes)) 2290 return -EFAULT; 2291 2292 result += bytes; 2293 buf += bytes; 2294 *pos += bytes; 2295 size -= bytes; 2296 } 2297 2298 return result; 2299 } 2300 2301 /* 2302 * amdgpu_ttm_vram_write - Linear write access to VRAM 2303 * 2304 * Accesses VRAM via MMIO for debugging purposes. 2305 */ 2306 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2307 size_t size, loff_t *pos) 2308 { 2309 struct amdgpu_device *adev = file_inode(f)->i_private; 2310 ssize_t result = 0; 2311 int r; 2312 2313 if (size & 0x3 || *pos & 0x3) 2314 return -EINVAL; 2315 2316 if (*pos >= adev->gmc.mc_vram_size) 2317 return -ENXIO; 2318 2319 while (size) { 2320 uint32_t value; 2321 2322 if (*pos >= adev->gmc.mc_vram_size) 2323 return result; 2324 2325 r = get_user(value, (uint32_t *)buf); 2326 if (r) 2327 return r; 2328 2329 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2330 2331 result += 4; 2332 buf += 4; 2333 *pos += 4; 2334 size -= 4; 2335 } 2336 2337 return result; 2338 } 2339 2340 static const struct file_operations amdgpu_ttm_vram_fops = { 2341 .owner = THIS_MODULE, 2342 .read = amdgpu_ttm_vram_read, 2343 .write = amdgpu_ttm_vram_write, 2344 .llseek = default_llseek, 2345 }; 2346 2347 /* 2348 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2349 * 2350 * This function is used to read memory that has been mapped to the 2351 * GPU and the known addresses are not physical addresses but instead 2352 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2353 */ 2354 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2355 size_t size, loff_t *pos) 2356 { 2357 struct amdgpu_device *adev = file_inode(f)->i_private; 2358 struct iommu_domain *dom; 2359 ssize_t result = 0; 2360 int r; 2361 2362 /* retrieve the IOMMU domain if any for this device */ 2363 dom = iommu_get_domain_for_dev(adev->dev); 2364 2365 while (size) { 2366 phys_addr_t addr = *pos & PAGE_MASK; 2367 loff_t off = *pos & ~PAGE_MASK; 2368 size_t bytes = PAGE_SIZE - off; 2369 unsigned long pfn; 2370 struct page *p; 2371 void *ptr; 2372 2373 bytes = bytes < size ? bytes : size; 2374 2375 /* Translate the bus address to a physical address. If 2376 * the domain is NULL it means there is no IOMMU active 2377 * and the address translation is the identity 2378 */ 2379 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2380 2381 pfn = addr >> PAGE_SHIFT; 2382 if (!pfn_valid(pfn)) 2383 return -EPERM; 2384 2385 p = pfn_to_page(pfn); 2386 if (p->mapping != adev->mman.bdev.dev_mapping) 2387 return -EPERM; 2388 2389 ptr = kmap_local_page(p); 2390 r = copy_to_user(buf, ptr + off, bytes); 2391 kunmap_local(ptr); 2392 if (r) 2393 return -EFAULT; 2394 2395 size -= bytes; 2396 *pos += bytes; 2397 result += bytes; 2398 } 2399 2400 return result; 2401 } 2402 2403 /* 2404 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2405 * 2406 * This function is used to write memory that has been mapped to the 2407 * GPU and the known addresses are not physical addresses but instead 2408 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2409 */ 2410 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2411 size_t size, loff_t *pos) 2412 { 2413 struct amdgpu_device *adev = file_inode(f)->i_private; 2414 struct iommu_domain *dom; 2415 ssize_t result = 0; 2416 int r; 2417 2418 dom = iommu_get_domain_for_dev(adev->dev); 2419 2420 while (size) { 2421 phys_addr_t addr = *pos & PAGE_MASK; 2422 loff_t off = *pos & ~PAGE_MASK; 2423 size_t bytes = PAGE_SIZE - off; 2424 unsigned long pfn; 2425 struct page *p; 2426 void *ptr; 2427 2428 bytes = bytes < size ? bytes : size; 2429 2430 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2431 2432 pfn = addr >> PAGE_SHIFT; 2433 if (!pfn_valid(pfn)) 2434 return -EPERM; 2435 2436 p = pfn_to_page(pfn); 2437 if (p->mapping != adev->mman.bdev.dev_mapping) 2438 return -EPERM; 2439 2440 ptr = kmap_local_page(p); 2441 r = copy_from_user(ptr + off, buf, bytes); 2442 kunmap_local(ptr); 2443 if (r) 2444 return -EFAULT; 2445 2446 size -= bytes; 2447 *pos += bytes; 2448 result += bytes; 2449 } 2450 2451 return result; 2452 } 2453 2454 static const struct file_operations amdgpu_ttm_iomem_fops = { 2455 .owner = THIS_MODULE, 2456 .read = amdgpu_iomem_read, 2457 .write = amdgpu_iomem_write, 2458 .llseek = default_llseek 2459 }; 2460 2461 #endif 2462 2463 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2464 { 2465 #if defined(CONFIG_DEBUG_FS) 2466 struct drm_minor *minor = adev_to_drm(adev)->primary; 2467 struct dentry *root = minor->debugfs_root; 2468 2469 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2470 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2471 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2472 &amdgpu_ttm_iomem_fops); 2473 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2474 &amdgpu_ttm_page_pool_fops); 2475 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2476 TTM_PL_VRAM), 2477 root, "amdgpu_vram_mm"); 2478 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2479 TTM_PL_TT), 2480 root, "amdgpu_gtt_mm"); 2481 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2482 AMDGPU_PL_GDS), 2483 root, "amdgpu_gds_mm"); 2484 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2485 AMDGPU_PL_GWS), 2486 root, "amdgpu_gws_mm"); 2487 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2488 AMDGPU_PL_OA), 2489 root, "amdgpu_oa_mm"); 2490 2491 #endif 2492 } 2493