1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 #include <linux/module.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_range_manager.h> 50 51 #include <drm/amdgpu_drm.h> 52 53 #include "amdgpu.h" 54 #include "amdgpu_object.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_sdma.h" 58 #include "amdgpu_ras.h" 59 #include "amdgpu_atomfirmware.h" 60 #include "amdgpu_res_cursor.h" 61 #include "bif/bif_4_1_d.h" 62 63 MODULE_IMPORT_NS(DMA_BUF); 64 65 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 66 67 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 68 struct ttm_tt *ttm, 69 struct ttm_resource *bo_mem); 70 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 71 struct ttm_tt *ttm); 72 73 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 74 unsigned int type, 75 uint64_t size_in_page) 76 { 77 return ttm_range_man_init(&adev->mman.bdev, type, 78 false, size_in_page); 79 } 80 81 /** 82 * amdgpu_evict_flags - Compute placement flags 83 * 84 * @bo: The buffer object to evict 85 * @placement: Possible destination(s) for evicted BO 86 * 87 * Fill in placement data when ttm_bo_evict() is called 88 */ 89 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 90 struct ttm_placement *placement) 91 { 92 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 93 struct amdgpu_bo *abo; 94 static const struct ttm_place placements = { 95 .fpfn = 0, 96 .lpfn = 0, 97 .mem_type = TTM_PL_SYSTEM, 98 .flags = 0 99 }; 100 101 /* Don't handle scatter gather BOs */ 102 if (bo->type == ttm_bo_type_sg) { 103 placement->num_placement = 0; 104 placement->num_busy_placement = 0; 105 return; 106 } 107 108 /* Object isn't an AMDGPU object so ignore */ 109 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 110 placement->placement = &placements; 111 placement->busy_placement = &placements; 112 placement->num_placement = 1; 113 placement->num_busy_placement = 1; 114 return; 115 } 116 117 abo = ttm_to_amdgpu_bo(bo); 118 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 119 struct dma_fence *fence; 120 struct dma_resv *resv = &bo->base._resv; 121 122 rcu_read_lock(); 123 fence = rcu_dereference(resv->fence_excl); 124 if (fence && !fence->ops->signaled) 125 dma_fence_enable_sw_signaling(fence); 126 127 placement->num_placement = 0; 128 placement->num_busy_placement = 0; 129 rcu_read_unlock(); 130 return; 131 } 132 133 switch (bo->resource->mem_type) { 134 case AMDGPU_PL_GDS: 135 case AMDGPU_PL_GWS: 136 case AMDGPU_PL_OA: 137 placement->num_placement = 0; 138 placement->num_busy_placement = 0; 139 return; 140 141 case TTM_PL_VRAM: 142 if (!adev->mman.buffer_funcs_enabled) { 143 /* Move to system memory */ 144 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 145 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 146 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 147 amdgpu_bo_in_cpu_visible_vram(abo)) { 148 149 /* Try evicting to the CPU inaccessible part of VRAM 150 * first, but only set GTT as busy placement, so this 151 * BO will be evicted to GTT rather than causing other 152 * BOs to be evicted from VRAM 153 */ 154 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 155 AMDGPU_GEM_DOMAIN_GTT | 156 AMDGPU_GEM_DOMAIN_CPU); 157 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 158 abo->placements[0].lpfn = 0; 159 abo->placement.busy_placement = &abo->placements[1]; 160 abo->placement.num_busy_placement = 1; 161 } else { 162 /* Move to GTT memory */ 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 164 AMDGPU_GEM_DOMAIN_CPU); 165 } 166 break; 167 case TTM_PL_TT: 168 case AMDGPU_PL_PREEMPT: 169 default: 170 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 171 break; 172 } 173 *placement = abo->placement; 174 } 175 176 /** 177 * amdgpu_ttm_map_buffer - Map memory into the GART windows 178 * @bo: buffer object to map 179 * @mem: memory object to map 180 * @mm_cur: range to map 181 * @num_pages: number of pages to map 182 * @window: which GART window to use 183 * @ring: DMA ring to use for the copy 184 * @tmz: if we should setup a TMZ enabled mapping 185 * @addr: resulting address inside the MC address space 186 * 187 * Setup one of the GART windows to access a specific piece of memory or return 188 * the physical address for local memory. 189 */ 190 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 191 struct ttm_resource *mem, 192 struct amdgpu_res_cursor *mm_cur, 193 unsigned num_pages, unsigned window, 194 struct amdgpu_ring *ring, bool tmz, 195 uint64_t *addr) 196 { 197 struct amdgpu_device *adev = ring->adev; 198 struct amdgpu_job *job; 199 unsigned num_dw, num_bytes; 200 struct dma_fence *fence; 201 uint64_t src_addr, dst_addr; 202 void *cpu_addr; 203 uint64_t flags; 204 unsigned int i; 205 int r; 206 207 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 208 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 209 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); 210 211 /* Map only what can't be accessed directly */ 212 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 213 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 214 mm_cur->start; 215 return 0; 216 } 217 218 *addr = adev->gmc.gart_start; 219 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 220 AMDGPU_GPU_PAGE_SIZE; 221 *addr += mm_cur->start & ~PAGE_MASK; 222 223 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 224 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 225 226 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 227 AMDGPU_IB_POOL_DELAYED, &job); 228 if (r) 229 return r; 230 231 src_addr = num_dw * 4; 232 src_addr += job->ibs[0].gpu_addr; 233 234 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 235 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 236 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 237 dst_addr, num_bytes, false); 238 239 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 240 WARN_ON(job->ibs[0].length_dw > num_dw); 241 242 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 243 if (tmz) 244 flags |= AMDGPU_PTE_TMZ; 245 246 cpu_addr = &job->ibs[0].ptr[num_dw]; 247 248 if (mem->mem_type == TTM_PL_TT) { 249 dma_addr_t *dma_addr; 250 251 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 252 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 253 cpu_addr); 254 if (r) 255 goto error_free; 256 } else { 257 dma_addr_t dma_address; 258 259 dma_address = mm_cur->start; 260 dma_address += adev->vm_manager.vram_base_offset; 261 262 for (i = 0; i < num_pages; ++i) { 263 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 264 &dma_address, flags, cpu_addr); 265 if (r) 266 goto error_free; 267 268 dma_address += PAGE_SIZE; 269 } 270 } 271 272 r = amdgpu_job_submit(job, &adev->mman.entity, 273 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 274 if (r) 275 goto error_free; 276 277 dma_fence_put(fence); 278 279 return r; 280 281 error_free: 282 amdgpu_job_free(job); 283 return r; 284 } 285 286 /** 287 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 288 * @adev: amdgpu device 289 * @src: buffer/address where to read from 290 * @dst: buffer/address where to write to 291 * @size: number of bytes to copy 292 * @tmz: if a secure copy should be used 293 * @resv: resv object to sync to 294 * @f: Returns the last fence if multiple jobs are submitted. 295 * 296 * The function copies @size bytes from {src->mem + src->offset} to 297 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 298 * move and different for a BO to BO copy. 299 * 300 */ 301 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 302 const struct amdgpu_copy_mem *src, 303 const struct amdgpu_copy_mem *dst, 304 uint64_t size, bool tmz, 305 struct dma_resv *resv, 306 struct dma_fence **f) 307 { 308 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 309 AMDGPU_GPU_PAGE_SIZE); 310 311 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 312 struct amdgpu_res_cursor src_mm, dst_mm; 313 struct dma_fence *fence = NULL; 314 int r = 0; 315 316 if (!adev->mman.buffer_funcs_enabled) { 317 DRM_ERROR("Trying to move memory with ring turned off.\n"); 318 return -EINVAL; 319 } 320 321 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 322 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 323 324 mutex_lock(&adev->mman.gtt_window_lock); 325 while (src_mm.remaining) { 326 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 327 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 328 struct dma_fence *next; 329 uint32_t cur_size; 330 uint64_t from, to; 331 332 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 333 * begins at an offset, then adjust the size accordingly 334 */ 335 cur_size = max(src_page_offset, dst_page_offset); 336 cur_size = min(min3(src_mm.size, dst_mm.size, size), 337 (uint64_t)(GTT_MAX_BYTES - cur_size)); 338 339 /* Map src to window 0 and dst to window 1. */ 340 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 341 PFN_UP(cur_size + src_page_offset), 342 0, ring, tmz, &from); 343 if (r) 344 goto error; 345 346 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 347 PFN_UP(cur_size + dst_page_offset), 348 1, ring, tmz, &to); 349 if (r) 350 goto error; 351 352 r = amdgpu_copy_buffer(ring, from, to, cur_size, 353 resv, &next, false, true, tmz); 354 if (r) 355 goto error; 356 357 dma_fence_put(fence); 358 fence = next; 359 360 amdgpu_res_next(&src_mm, cur_size); 361 amdgpu_res_next(&dst_mm, cur_size); 362 } 363 error: 364 mutex_unlock(&adev->mman.gtt_window_lock); 365 if (f) 366 *f = dma_fence_get(fence); 367 dma_fence_put(fence); 368 return r; 369 } 370 371 /* 372 * amdgpu_move_blit - Copy an entire buffer to another buffer 373 * 374 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 375 * help move buffers to and from VRAM. 376 */ 377 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 378 bool evict, 379 struct ttm_resource *new_mem, 380 struct ttm_resource *old_mem) 381 { 382 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 383 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 384 struct amdgpu_copy_mem src, dst; 385 struct dma_fence *fence = NULL; 386 int r; 387 388 src.bo = bo; 389 dst.bo = bo; 390 src.mem = old_mem; 391 dst.mem = new_mem; 392 src.offset = 0; 393 dst.offset = 0; 394 395 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 396 new_mem->num_pages << PAGE_SHIFT, 397 amdgpu_bo_encrypted(abo), 398 bo->base.resv, &fence); 399 if (r) 400 goto error; 401 402 /* clear the space being freed */ 403 if (old_mem->mem_type == TTM_PL_VRAM && 404 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 405 struct dma_fence *wipe_fence = NULL; 406 407 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 408 NULL, &wipe_fence); 409 if (r) { 410 goto error; 411 } else if (wipe_fence) { 412 dma_fence_put(fence); 413 fence = wipe_fence; 414 } 415 } 416 417 /* Always block for VM page tables before committing the new location */ 418 if (bo->type == ttm_bo_type_kernel) 419 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 420 else 421 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 422 dma_fence_put(fence); 423 return r; 424 425 error: 426 if (fence) 427 dma_fence_wait(fence, false); 428 dma_fence_put(fence); 429 return r; 430 } 431 432 /* 433 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 434 * 435 * Called by amdgpu_bo_move() 436 */ 437 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 438 struct ttm_resource *mem) 439 { 440 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 441 struct amdgpu_res_cursor cursor; 442 443 if (mem->mem_type == TTM_PL_SYSTEM || 444 mem->mem_type == TTM_PL_TT) 445 return true; 446 if (mem->mem_type != TTM_PL_VRAM) 447 return false; 448 449 amdgpu_res_first(mem, 0, mem_size, &cursor); 450 451 /* ttm_resource_ioremap only supports contiguous memory */ 452 if (cursor.size != mem_size) 453 return false; 454 455 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 456 } 457 458 /* 459 * amdgpu_bo_move - Move a buffer object to a new memory location 460 * 461 * Called by ttm_bo_handle_move_mem() 462 */ 463 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 464 struct ttm_operation_ctx *ctx, 465 struct ttm_resource *new_mem, 466 struct ttm_place *hop) 467 { 468 struct amdgpu_device *adev; 469 struct amdgpu_bo *abo; 470 struct ttm_resource *old_mem = bo->resource; 471 int r; 472 473 if (new_mem->mem_type == TTM_PL_TT || 474 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 475 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 476 if (r) 477 return r; 478 } 479 480 /* Can't move a pinned BO */ 481 abo = ttm_to_amdgpu_bo(bo); 482 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 483 return -EINVAL; 484 485 adev = amdgpu_ttm_adev(bo->bdev); 486 487 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 488 ttm_bo_move_null(bo, new_mem); 489 goto out; 490 } 491 if (old_mem->mem_type == TTM_PL_SYSTEM && 492 (new_mem->mem_type == TTM_PL_TT || 493 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 494 ttm_bo_move_null(bo, new_mem); 495 goto out; 496 } 497 if ((old_mem->mem_type == TTM_PL_TT || 498 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 499 new_mem->mem_type == TTM_PL_SYSTEM) { 500 r = ttm_bo_wait_ctx(bo, ctx); 501 if (r) 502 return r; 503 504 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 505 ttm_resource_free(bo, &bo->resource); 506 ttm_bo_assign_mem(bo, new_mem); 507 goto out; 508 } 509 510 if (old_mem->mem_type == AMDGPU_PL_GDS || 511 old_mem->mem_type == AMDGPU_PL_GWS || 512 old_mem->mem_type == AMDGPU_PL_OA || 513 new_mem->mem_type == AMDGPU_PL_GDS || 514 new_mem->mem_type == AMDGPU_PL_GWS || 515 new_mem->mem_type == AMDGPU_PL_OA) { 516 /* Nothing to save here */ 517 ttm_bo_move_null(bo, new_mem); 518 goto out; 519 } 520 521 if (bo->type == ttm_bo_type_device && 522 new_mem->mem_type == TTM_PL_VRAM && 523 old_mem->mem_type != TTM_PL_VRAM) { 524 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 525 * accesses the BO after it's moved. 526 */ 527 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 528 } 529 530 if (adev->mman.buffer_funcs_enabled) { 531 if (((old_mem->mem_type == TTM_PL_SYSTEM && 532 new_mem->mem_type == TTM_PL_VRAM) || 533 (old_mem->mem_type == TTM_PL_VRAM && 534 new_mem->mem_type == TTM_PL_SYSTEM))) { 535 hop->fpfn = 0; 536 hop->lpfn = 0; 537 hop->mem_type = TTM_PL_TT; 538 hop->flags = TTM_PL_FLAG_TEMPORARY; 539 return -EMULTIHOP; 540 } 541 542 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 543 } else { 544 r = -ENODEV; 545 } 546 547 if (r) { 548 /* Check that all memory is CPU accessible */ 549 if (!amdgpu_mem_visible(adev, old_mem) || 550 !amdgpu_mem_visible(adev, new_mem)) { 551 pr_err("Move buffer fallback to memcpy unavailable\n"); 552 return r; 553 } 554 555 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 556 if (r) 557 return r; 558 } 559 560 out: 561 /* update statistics */ 562 atomic64_add(bo->base.size, &adev->num_bytes_moved); 563 amdgpu_bo_move_notify(bo, evict, new_mem); 564 return 0; 565 } 566 567 /* 568 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 569 * 570 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 571 */ 572 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 573 struct ttm_resource *mem) 574 { 575 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 576 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 577 578 switch (mem->mem_type) { 579 case TTM_PL_SYSTEM: 580 /* system memory */ 581 return 0; 582 case TTM_PL_TT: 583 case AMDGPU_PL_PREEMPT: 584 break; 585 case TTM_PL_VRAM: 586 mem->bus.offset = mem->start << PAGE_SHIFT; 587 /* check if it's visible */ 588 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 589 return -EINVAL; 590 591 if (adev->mman.aper_base_kaddr && 592 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 593 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 594 mem->bus.offset; 595 596 mem->bus.offset += adev->gmc.aper_base; 597 mem->bus.is_iomem = true; 598 break; 599 default: 600 return -EINVAL; 601 } 602 return 0; 603 } 604 605 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 606 unsigned long page_offset) 607 { 608 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 609 struct amdgpu_res_cursor cursor; 610 611 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 612 &cursor); 613 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 614 } 615 616 /** 617 * amdgpu_ttm_domain_start - Returns GPU start address 618 * @adev: amdgpu device object 619 * @type: type of the memory 620 * 621 * Returns: 622 * GPU start address of a memory domain 623 */ 624 625 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 626 { 627 switch (type) { 628 case TTM_PL_TT: 629 return adev->gmc.gart_start; 630 case TTM_PL_VRAM: 631 return adev->gmc.vram_start; 632 } 633 634 return 0; 635 } 636 637 /* 638 * TTM backend functions. 639 */ 640 struct amdgpu_ttm_tt { 641 struct ttm_tt ttm; 642 struct drm_gem_object *gobj; 643 u64 offset; 644 uint64_t userptr; 645 struct task_struct *usertask; 646 uint32_t userflags; 647 bool bound; 648 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 649 struct hmm_range *range; 650 #endif 651 }; 652 653 #ifdef CONFIG_DRM_AMDGPU_USERPTR 654 /* 655 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 656 * memory and start HMM tracking CPU page table update 657 * 658 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 659 * once afterwards to stop HMM tracking 660 */ 661 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 662 { 663 struct ttm_tt *ttm = bo->tbo.ttm; 664 struct amdgpu_ttm_tt *gtt = (void *)ttm; 665 unsigned long start = gtt->userptr; 666 struct vm_area_struct *vma; 667 struct mm_struct *mm; 668 bool readonly; 669 int r = 0; 670 671 mm = bo->notifier.mm; 672 if (unlikely(!mm)) { 673 DRM_DEBUG_DRIVER("BO is not registered?\n"); 674 return -EFAULT; 675 } 676 677 /* Another get_user_pages is running at the same time?? */ 678 if (WARN_ON(gtt->range)) 679 return -EFAULT; 680 681 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 682 return -ESRCH; 683 684 mmap_read_lock(mm); 685 vma = vma_lookup(mm, start); 686 if (unlikely(!vma)) { 687 r = -EFAULT; 688 goto out_unlock; 689 } 690 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 691 vma->vm_file)) { 692 r = -EPERM; 693 goto out_unlock; 694 } 695 696 readonly = amdgpu_ttm_tt_is_readonly(ttm); 697 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 698 ttm->num_pages, >t->range, readonly, 699 true, NULL); 700 out_unlock: 701 mmap_read_unlock(mm); 702 if (r) 703 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 704 705 mmput(mm); 706 707 return r; 708 } 709 710 /* 711 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 712 * Check if the pages backing this ttm range have been invalidated 713 * 714 * Returns: true if pages are still valid 715 */ 716 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 717 { 718 struct amdgpu_ttm_tt *gtt = (void *)ttm; 719 bool r = false; 720 721 if (!gtt || !gtt->userptr) 722 return false; 723 724 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 725 gtt->userptr, ttm->num_pages); 726 727 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 728 "No user pages to check\n"); 729 730 if (gtt->range) { 731 /* 732 * FIXME: Must always hold notifier_lock for this, and must 733 * not ignore the return code. 734 */ 735 r = amdgpu_hmm_range_get_pages_done(gtt->range); 736 gtt->range = NULL; 737 } 738 739 return !r; 740 } 741 #endif 742 743 /* 744 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 745 * 746 * Called by amdgpu_cs_list_validate(). This creates the page list 747 * that backs user memory and will ultimately be mapped into the device 748 * address space. 749 */ 750 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 751 { 752 unsigned long i; 753 754 for (i = 0; i < ttm->num_pages; ++i) 755 ttm->pages[i] = pages ? pages[i] : NULL; 756 } 757 758 /* 759 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 760 * 761 * Called by amdgpu_ttm_backend_bind() 762 **/ 763 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 764 struct ttm_tt *ttm) 765 { 766 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 767 struct amdgpu_ttm_tt *gtt = (void *)ttm; 768 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 769 enum dma_data_direction direction = write ? 770 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 771 int r; 772 773 /* Allocate an SG array and squash pages into it */ 774 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 775 (u64)ttm->num_pages << PAGE_SHIFT, 776 GFP_KERNEL); 777 if (r) 778 goto release_sg; 779 780 /* Map SG to device */ 781 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 782 if (r) 783 goto release_sg; 784 785 /* convert SG to linear array of pages and dma addresses */ 786 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 787 ttm->num_pages); 788 789 return 0; 790 791 release_sg: 792 kfree(ttm->sg); 793 ttm->sg = NULL; 794 return r; 795 } 796 797 /* 798 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 799 */ 800 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 801 struct ttm_tt *ttm) 802 { 803 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 804 struct amdgpu_ttm_tt *gtt = (void *)ttm; 805 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 806 enum dma_data_direction direction = write ? 807 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 808 809 /* double check that we don't free the table twice */ 810 if (!ttm->sg || !ttm->sg->sgl) 811 return; 812 813 /* unmap the pages mapped to the device */ 814 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 815 sg_free_table(ttm->sg); 816 817 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 818 if (gtt->range) { 819 unsigned long i; 820 821 for (i = 0; i < ttm->num_pages; i++) { 822 if (ttm->pages[i] != 823 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 824 break; 825 } 826 827 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 828 } 829 #endif 830 } 831 832 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 833 struct ttm_buffer_object *tbo, 834 uint64_t flags) 835 { 836 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 837 struct ttm_tt *ttm = tbo->ttm; 838 struct amdgpu_ttm_tt *gtt = (void *)ttm; 839 int r; 840 841 if (amdgpu_bo_encrypted(abo)) 842 flags |= AMDGPU_PTE_TMZ; 843 844 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 845 uint64_t page_idx = 1; 846 847 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 848 gtt->ttm.dma_address, flags); 849 if (r) 850 goto gart_bind_fail; 851 852 /* The memory type of the first page defaults to UC. Now 853 * modify the memory type to NC from the second page of 854 * the BO onward. 855 */ 856 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 857 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 858 859 r = amdgpu_gart_bind(adev, 860 gtt->offset + (page_idx << PAGE_SHIFT), 861 ttm->num_pages - page_idx, 862 &(gtt->ttm.dma_address[page_idx]), flags); 863 } else { 864 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 865 gtt->ttm.dma_address, flags); 866 } 867 868 gart_bind_fail: 869 if (r) 870 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 871 ttm->num_pages, gtt->offset); 872 873 return r; 874 } 875 876 /* 877 * amdgpu_ttm_backend_bind - Bind GTT memory 878 * 879 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 880 * This handles binding GTT memory to the device address space. 881 */ 882 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 883 struct ttm_tt *ttm, 884 struct ttm_resource *bo_mem) 885 { 886 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 887 struct amdgpu_ttm_tt *gtt = (void*)ttm; 888 uint64_t flags; 889 int r = 0; 890 891 if (!bo_mem) 892 return -EINVAL; 893 894 if (gtt->bound) 895 return 0; 896 897 if (gtt->userptr) { 898 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 899 if (r) { 900 DRM_ERROR("failed to pin userptr\n"); 901 return r; 902 } 903 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 904 if (!ttm->sg) { 905 struct dma_buf_attachment *attach; 906 struct sg_table *sgt; 907 908 attach = gtt->gobj->import_attach; 909 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 910 if (IS_ERR(sgt)) 911 return PTR_ERR(sgt); 912 913 ttm->sg = sgt; 914 } 915 916 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 917 ttm->num_pages); 918 } 919 920 if (!ttm->num_pages) { 921 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 922 ttm->num_pages, bo_mem, ttm); 923 } 924 925 if (bo_mem->mem_type != TTM_PL_TT || 926 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 927 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 928 return 0; 929 } 930 931 /* compute PTE flags relevant to this BO memory */ 932 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 933 934 /* bind pages into GART page tables */ 935 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 936 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 937 gtt->ttm.dma_address, flags); 938 939 if (r) 940 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 941 ttm->num_pages, gtt->offset); 942 gtt->bound = true; 943 return r; 944 } 945 946 /* 947 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 948 * through AGP or GART aperture. 949 * 950 * If bo is accessible through AGP aperture, then use AGP aperture 951 * to access bo; otherwise allocate logical space in GART aperture 952 * and map bo to GART aperture. 953 */ 954 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 955 { 956 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 957 struct ttm_operation_ctx ctx = { false, false }; 958 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 959 struct ttm_placement placement; 960 struct ttm_place placements; 961 struct ttm_resource *tmp; 962 uint64_t addr, flags; 963 int r; 964 965 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 966 return 0; 967 968 addr = amdgpu_gmc_agp_addr(bo); 969 if (addr != AMDGPU_BO_INVALID_OFFSET) { 970 bo->resource->start = addr >> PAGE_SHIFT; 971 return 0; 972 } 973 974 /* allocate GART space */ 975 placement.num_placement = 1; 976 placement.placement = &placements; 977 placement.num_busy_placement = 1; 978 placement.busy_placement = &placements; 979 placements.fpfn = 0; 980 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 981 placements.mem_type = TTM_PL_TT; 982 placements.flags = bo->resource->placement; 983 984 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 985 if (unlikely(r)) 986 return r; 987 988 /* compute PTE flags for this buffer object */ 989 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 990 991 /* Bind pages */ 992 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 993 r = amdgpu_ttm_gart_bind(adev, bo, flags); 994 if (unlikely(r)) { 995 ttm_resource_free(bo, &tmp); 996 return r; 997 } 998 999 amdgpu_gart_invalidate_tlb(adev); 1000 ttm_resource_free(bo, &bo->resource); 1001 ttm_bo_assign_mem(bo, tmp); 1002 1003 return 0; 1004 } 1005 1006 /* 1007 * amdgpu_ttm_recover_gart - Rebind GTT pages 1008 * 1009 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1010 * rebind GTT pages during a GPU reset. 1011 */ 1012 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1013 { 1014 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1015 uint64_t flags; 1016 int r; 1017 1018 if (!tbo->ttm) 1019 return 0; 1020 1021 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1022 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1023 1024 return r; 1025 } 1026 1027 /* 1028 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1029 * 1030 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1031 * ttm_tt_destroy(). 1032 */ 1033 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1034 struct ttm_tt *ttm) 1035 { 1036 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1037 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1038 int r; 1039 1040 /* if the pages have userptr pinning then clear that first */ 1041 if (gtt->userptr) { 1042 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1043 } else if (ttm->sg && gtt->gobj->import_attach) { 1044 struct dma_buf_attachment *attach; 1045 1046 attach = gtt->gobj->import_attach; 1047 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1048 ttm->sg = NULL; 1049 } 1050 1051 if (!gtt->bound) 1052 return; 1053 1054 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1055 return; 1056 1057 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1058 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1059 if (r) 1060 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1061 gtt->ttm.num_pages, gtt->offset); 1062 gtt->bound = false; 1063 } 1064 1065 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1066 struct ttm_tt *ttm) 1067 { 1068 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1069 1070 if (gtt->usertask) 1071 put_task_struct(gtt->usertask); 1072 1073 ttm_tt_fini(>t->ttm); 1074 kfree(gtt); 1075 } 1076 1077 /** 1078 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1079 * 1080 * @bo: The buffer object to create a GTT ttm_tt object around 1081 * @page_flags: Page flags to be added to the ttm_tt object 1082 * 1083 * Called by ttm_tt_create(). 1084 */ 1085 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1086 uint32_t page_flags) 1087 { 1088 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1089 struct amdgpu_ttm_tt *gtt; 1090 enum ttm_caching caching; 1091 1092 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1093 if (gtt == NULL) { 1094 return NULL; 1095 } 1096 gtt->gobj = &bo->base; 1097 1098 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1099 caching = ttm_write_combined; 1100 else 1101 caching = ttm_cached; 1102 1103 /* allocate space for the uninitialized page entries */ 1104 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1105 kfree(gtt); 1106 return NULL; 1107 } 1108 return >t->ttm; 1109 } 1110 1111 /* 1112 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1113 * 1114 * Map the pages of a ttm_tt object to an address space visible 1115 * to the underlying device. 1116 */ 1117 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1118 struct ttm_tt *ttm, 1119 struct ttm_operation_ctx *ctx) 1120 { 1121 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1122 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1123 pgoff_t i; 1124 int ret; 1125 1126 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1127 if (gtt->userptr) { 1128 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1129 if (!ttm->sg) 1130 return -ENOMEM; 1131 return 0; 1132 } 1133 1134 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1135 return 0; 1136 1137 ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1138 if (ret) 1139 return ret; 1140 1141 for (i = 0; i < ttm->num_pages; ++i) 1142 ttm->pages[i]->mapping = bdev->dev_mapping; 1143 1144 return 0; 1145 } 1146 1147 /* 1148 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1149 * 1150 * Unmaps pages of a ttm_tt object from the device address space and 1151 * unpopulates the page array backing it. 1152 */ 1153 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1154 struct ttm_tt *ttm) 1155 { 1156 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1157 struct amdgpu_device *adev; 1158 pgoff_t i; 1159 1160 amdgpu_ttm_backend_unbind(bdev, ttm); 1161 1162 if (gtt->userptr) { 1163 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1164 kfree(ttm->sg); 1165 ttm->sg = NULL; 1166 return; 1167 } 1168 1169 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1170 return; 1171 1172 for (i = 0; i < ttm->num_pages; ++i) 1173 ttm->pages[i]->mapping = NULL; 1174 1175 adev = amdgpu_ttm_adev(bdev); 1176 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1177 } 1178 1179 /** 1180 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1181 * task 1182 * 1183 * @bo: The ttm_buffer_object to bind this userptr to 1184 * @addr: The address in the current tasks VM space to use 1185 * @flags: Requirements of userptr object. 1186 * 1187 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1188 * to current task 1189 */ 1190 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1191 uint64_t addr, uint32_t flags) 1192 { 1193 struct amdgpu_ttm_tt *gtt; 1194 1195 if (!bo->ttm) { 1196 /* TODO: We want a separate TTM object type for userptrs */ 1197 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1198 if (bo->ttm == NULL) 1199 return -ENOMEM; 1200 } 1201 1202 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1203 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1204 1205 gtt = (void *)bo->ttm; 1206 gtt->userptr = addr; 1207 gtt->userflags = flags; 1208 1209 if (gtt->usertask) 1210 put_task_struct(gtt->usertask); 1211 gtt->usertask = current->group_leader; 1212 get_task_struct(gtt->usertask); 1213 1214 return 0; 1215 } 1216 1217 /* 1218 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1219 */ 1220 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1221 { 1222 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1223 1224 if (gtt == NULL) 1225 return NULL; 1226 1227 if (gtt->usertask == NULL) 1228 return NULL; 1229 1230 return gtt->usertask->mm; 1231 } 1232 1233 /* 1234 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1235 * address range for the current task. 1236 * 1237 */ 1238 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1239 unsigned long end, unsigned long *userptr) 1240 { 1241 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1242 unsigned long size; 1243 1244 if (gtt == NULL || !gtt->userptr) 1245 return false; 1246 1247 /* Return false if no part of the ttm_tt object lies within 1248 * the range 1249 */ 1250 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1251 if (gtt->userptr > end || gtt->userptr + size <= start) 1252 return false; 1253 1254 if (userptr) 1255 *userptr = gtt->userptr; 1256 return true; 1257 } 1258 1259 /* 1260 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1261 */ 1262 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1263 { 1264 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1265 1266 if (gtt == NULL || !gtt->userptr) 1267 return false; 1268 1269 return true; 1270 } 1271 1272 /* 1273 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1274 */ 1275 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1276 { 1277 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1278 1279 if (gtt == NULL) 1280 return false; 1281 1282 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1283 } 1284 1285 /** 1286 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1287 * 1288 * @ttm: The ttm_tt object to compute the flags for 1289 * @mem: The memory registry backing this ttm_tt object 1290 * 1291 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1292 */ 1293 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1294 { 1295 uint64_t flags = 0; 1296 1297 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1298 flags |= AMDGPU_PTE_VALID; 1299 1300 if (mem && (mem->mem_type == TTM_PL_TT || 1301 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1302 flags |= AMDGPU_PTE_SYSTEM; 1303 1304 if (ttm->caching == ttm_cached) 1305 flags |= AMDGPU_PTE_SNOOPED; 1306 } 1307 1308 if (mem && mem->mem_type == TTM_PL_VRAM && 1309 mem->bus.caching == ttm_cached) 1310 flags |= AMDGPU_PTE_SNOOPED; 1311 1312 return flags; 1313 } 1314 1315 /** 1316 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1317 * 1318 * @adev: amdgpu_device pointer 1319 * @ttm: The ttm_tt object to compute the flags for 1320 * @mem: The memory registry backing this ttm_tt object 1321 * 1322 * Figure out the flags to use for a VM PTE (Page Table Entry). 1323 */ 1324 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1325 struct ttm_resource *mem) 1326 { 1327 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1328 1329 flags |= adev->gart.gart_pte_flags; 1330 flags |= AMDGPU_PTE_READABLE; 1331 1332 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1333 flags |= AMDGPU_PTE_WRITEABLE; 1334 1335 return flags; 1336 } 1337 1338 /* 1339 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1340 * object. 1341 * 1342 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1343 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1344 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1345 * used to clean out a memory space. 1346 */ 1347 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1348 const struct ttm_place *place) 1349 { 1350 unsigned long num_pages = bo->resource->num_pages; 1351 struct amdgpu_res_cursor cursor; 1352 struct dma_resv_list *flist; 1353 struct dma_fence *f; 1354 int i; 1355 1356 /* Swapout? */ 1357 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1358 return true; 1359 1360 if (bo->type == ttm_bo_type_kernel && 1361 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1362 return false; 1363 1364 /* If bo is a KFD BO, check if the bo belongs to the current process. 1365 * If true, then return false as any KFD process needs all its BOs to 1366 * be resident to run successfully 1367 */ 1368 flist = dma_resv_shared_list(bo->base.resv); 1369 if (flist) { 1370 for (i = 0; i < flist->shared_count; ++i) { 1371 f = rcu_dereference_protected(flist->shared[i], 1372 dma_resv_held(bo->base.resv)); 1373 if (amdkfd_fence_check_mm(f, current->mm)) 1374 return false; 1375 } 1376 } 1377 1378 switch (bo->resource->mem_type) { 1379 case AMDGPU_PL_PREEMPT: 1380 /* Preemptible BOs don't own system resources managed by the 1381 * driver (pages, VRAM, GART space). They point to resources 1382 * owned by someone else (e.g. pageable memory in user mode 1383 * or a DMABuf). They are used in a preemptible context so we 1384 * can guarantee no deadlocks and good QoS in case of MMU 1385 * notifiers or DMABuf move notifiers from the resource owner. 1386 */ 1387 return false; 1388 case TTM_PL_TT: 1389 if (amdgpu_bo_is_amdgpu_bo(bo) && 1390 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1391 return false; 1392 return true; 1393 1394 case TTM_PL_VRAM: 1395 /* Check each drm MM node individually */ 1396 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1397 &cursor); 1398 while (cursor.remaining) { 1399 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1400 && !(place->lpfn && 1401 place->lpfn <= PFN_DOWN(cursor.start))) 1402 return true; 1403 1404 amdgpu_res_next(&cursor, cursor.size); 1405 } 1406 return false; 1407 1408 default: 1409 break; 1410 } 1411 1412 return ttm_bo_eviction_valuable(bo, place); 1413 } 1414 1415 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1416 void *buf, size_t size, bool write) 1417 { 1418 while (size) { 1419 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1420 uint64_t bytes = 4 - (pos & 0x3); 1421 uint32_t shift = (pos & 0x3) * 8; 1422 uint32_t mask = 0xffffffff << shift; 1423 uint32_t value = 0; 1424 1425 if (size < bytes) { 1426 mask &= 0xffffffff >> (bytes - size) * 8; 1427 bytes = size; 1428 } 1429 1430 if (mask != 0xffffffff) { 1431 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1432 if (write) { 1433 value &= ~mask; 1434 value |= (*(uint32_t *)buf << shift) & mask; 1435 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1436 } else { 1437 value = (value & mask) >> shift; 1438 memcpy(buf, &value, bytes); 1439 } 1440 } else { 1441 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1442 } 1443 1444 pos += bytes; 1445 buf += bytes; 1446 size -= bytes; 1447 } 1448 } 1449 1450 /** 1451 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1452 * 1453 * @bo: The buffer object to read/write 1454 * @offset: Offset into buffer object 1455 * @buf: Secondary buffer to write/read from 1456 * @len: Length in bytes of access 1457 * @write: true if writing 1458 * 1459 * This is used to access VRAM that backs a buffer object via MMIO 1460 * access for debugging purposes. 1461 */ 1462 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1463 unsigned long offset, void *buf, int len, 1464 int write) 1465 { 1466 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1467 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1468 struct amdgpu_res_cursor cursor; 1469 int ret = 0; 1470 1471 if (bo->resource->mem_type != TTM_PL_VRAM) 1472 return -EIO; 1473 1474 amdgpu_res_first(bo->resource, offset, len, &cursor); 1475 while (cursor.remaining) { 1476 size_t count, size = cursor.size; 1477 loff_t pos = cursor.start; 1478 1479 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1480 size -= count; 1481 if (size) { 1482 /* using MM to access rest vram and handle un-aligned address */ 1483 pos += count; 1484 buf += count; 1485 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1486 } 1487 1488 ret += cursor.size; 1489 buf += cursor.size; 1490 amdgpu_res_next(&cursor, cursor.size); 1491 } 1492 1493 return ret; 1494 } 1495 1496 static void 1497 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1498 { 1499 amdgpu_bo_move_notify(bo, false, NULL); 1500 } 1501 1502 static struct ttm_device_funcs amdgpu_bo_driver = { 1503 .ttm_tt_create = &amdgpu_ttm_tt_create, 1504 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1505 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1506 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1507 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1508 .evict_flags = &amdgpu_evict_flags, 1509 .move = &amdgpu_bo_move, 1510 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1511 .release_notify = &amdgpu_bo_release_notify, 1512 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1513 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1514 .access_memory = &amdgpu_ttm_access_memory, 1515 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1516 }; 1517 1518 /* 1519 * Firmware Reservation functions 1520 */ 1521 /** 1522 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1523 * 1524 * @adev: amdgpu_device pointer 1525 * 1526 * free fw reserved vram if it has been reserved. 1527 */ 1528 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1529 { 1530 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1531 NULL, &adev->mman.fw_vram_usage_va); 1532 } 1533 1534 /** 1535 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1536 * 1537 * @adev: amdgpu_device pointer 1538 * 1539 * create bo vram reservation from fw. 1540 */ 1541 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1542 { 1543 uint64_t vram_size = adev->gmc.visible_vram_size; 1544 1545 adev->mman.fw_vram_usage_va = NULL; 1546 adev->mman.fw_vram_usage_reserved_bo = NULL; 1547 1548 if (adev->mman.fw_vram_usage_size == 0 || 1549 adev->mman.fw_vram_usage_size > vram_size) 1550 return 0; 1551 1552 return amdgpu_bo_create_kernel_at(adev, 1553 adev->mman.fw_vram_usage_start_offset, 1554 adev->mman.fw_vram_usage_size, 1555 AMDGPU_GEM_DOMAIN_VRAM, 1556 &adev->mman.fw_vram_usage_reserved_bo, 1557 &adev->mman.fw_vram_usage_va); 1558 } 1559 1560 /* 1561 * Memoy training reservation functions 1562 */ 1563 1564 /** 1565 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1566 * 1567 * @adev: amdgpu_device pointer 1568 * 1569 * free memory training reserved vram if it has been reserved. 1570 */ 1571 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1572 { 1573 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1574 1575 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1576 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1577 ctx->c2p_bo = NULL; 1578 1579 return 0; 1580 } 1581 1582 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1583 { 1584 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1585 1586 memset(ctx, 0, sizeof(*ctx)); 1587 1588 ctx->c2p_train_data_offset = 1589 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1590 ctx->p2c_train_data_offset = 1591 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1592 ctx->train_data_size = 1593 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1594 1595 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1596 ctx->train_data_size, 1597 ctx->p2c_train_data_offset, 1598 ctx->c2p_train_data_offset); 1599 } 1600 1601 /* 1602 * reserve TMR memory at the top of VRAM which holds 1603 * IP Discovery data and is protected by PSP. 1604 */ 1605 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1606 { 1607 int ret; 1608 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1609 bool mem_train_support = false; 1610 1611 if (!amdgpu_sriov_vf(adev)) { 1612 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1613 mem_train_support = true; 1614 else 1615 DRM_DEBUG("memory training does not support!\n"); 1616 } 1617 1618 /* 1619 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1620 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1621 * 1622 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1623 * discovery data and G6 memory training data respectively 1624 */ 1625 adev->mman.discovery_tmr_size = 1626 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1627 if (!adev->mman.discovery_tmr_size) 1628 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1629 1630 if (mem_train_support) { 1631 /* reserve vram for mem train according to TMR location */ 1632 amdgpu_ttm_training_data_block_init(adev); 1633 ret = amdgpu_bo_create_kernel_at(adev, 1634 ctx->c2p_train_data_offset, 1635 ctx->train_data_size, 1636 AMDGPU_GEM_DOMAIN_VRAM, 1637 &ctx->c2p_bo, 1638 NULL); 1639 if (ret) { 1640 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1641 amdgpu_ttm_training_reserve_vram_fini(adev); 1642 return ret; 1643 } 1644 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1645 } 1646 1647 ret = amdgpu_bo_create_kernel_at(adev, 1648 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1649 adev->mman.discovery_tmr_size, 1650 AMDGPU_GEM_DOMAIN_VRAM, 1651 &adev->mman.discovery_memory, 1652 NULL); 1653 if (ret) { 1654 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1655 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1656 return ret; 1657 } 1658 1659 return 0; 1660 } 1661 1662 /* 1663 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1664 * gtt/vram related fields. 1665 * 1666 * This initializes all of the memory space pools that the TTM layer 1667 * will need such as the GTT space (system memory mapped to the device), 1668 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1669 * can be mapped per VMID. 1670 */ 1671 int amdgpu_ttm_init(struct amdgpu_device *adev) 1672 { 1673 uint64_t gtt_size; 1674 int r; 1675 u64 vis_vram_limit; 1676 1677 mutex_init(&adev->mman.gtt_window_lock); 1678 1679 /* No others user of address space so set it to 0 */ 1680 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1681 adev_to_drm(adev)->anon_inode->i_mapping, 1682 adev_to_drm(adev)->vma_offset_manager, 1683 adev->need_swiotlb, 1684 dma_addressing_limited(adev->dev)); 1685 if (r) { 1686 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1687 return r; 1688 } 1689 adev->mman.initialized = true; 1690 1691 /* Initialize VRAM pool with all of VRAM divided into pages */ 1692 r = amdgpu_vram_mgr_init(adev); 1693 if (r) { 1694 DRM_ERROR("Failed initializing VRAM heap.\n"); 1695 return r; 1696 } 1697 1698 /* Reduce size of CPU-visible VRAM if requested */ 1699 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1700 if (amdgpu_vis_vram_limit > 0 && 1701 vis_vram_limit <= adev->gmc.visible_vram_size) 1702 adev->gmc.visible_vram_size = vis_vram_limit; 1703 1704 /* Change the size here instead of the init above so only lpfn is affected */ 1705 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1706 #ifdef CONFIG_64BIT 1707 #ifdef CONFIG_X86 1708 if (adev->gmc.xgmi.connected_to_cpu) 1709 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1710 adev->gmc.visible_vram_size); 1711 1712 else 1713 #endif 1714 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1715 adev->gmc.visible_vram_size); 1716 #endif 1717 1718 /* 1719 *The reserved vram for firmware must be pinned to the specified 1720 *place on the VRAM, so reserve it early. 1721 */ 1722 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1723 if (r) { 1724 return r; 1725 } 1726 1727 /* 1728 * only NAVI10 and onwards ASIC support for IP discovery. 1729 * If IP discovery enabled, a block of memory should be 1730 * reserved for IP discovey. 1731 */ 1732 if (adev->mman.discovery_bin) { 1733 r = amdgpu_ttm_reserve_tmr(adev); 1734 if (r) 1735 return r; 1736 } 1737 1738 /* allocate memory as required for VGA 1739 * This is used for VGA emulation and pre-OS scanout buffers to 1740 * avoid display artifacts while transitioning between pre-OS 1741 * and driver. */ 1742 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1743 AMDGPU_GEM_DOMAIN_VRAM, 1744 &adev->mman.stolen_vga_memory, 1745 NULL); 1746 if (r) 1747 return r; 1748 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1749 adev->mman.stolen_extended_size, 1750 AMDGPU_GEM_DOMAIN_VRAM, 1751 &adev->mman.stolen_extended_memory, 1752 NULL); 1753 if (r) 1754 return r; 1755 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1756 adev->mman.stolen_reserved_size, 1757 AMDGPU_GEM_DOMAIN_VRAM, 1758 &adev->mman.stolen_reserved_memory, 1759 NULL); 1760 if (r) 1761 return r; 1762 1763 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1764 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1765 1766 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1767 * or whatever the user passed on module init */ 1768 if (amdgpu_gtt_size == -1) { 1769 struct sysinfo si; 1770 1771 si_meminfo(&si); 1772 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1773 adev->gmc.mc_vram_size), 1774 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1775 } 1776 else 1777 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1778 1779 /* Initialize GTT memory pool */ 1780 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1781 if (r) { 1782 DRM_ERROR("Failed initializing GTT heap.\n"); 1783 return r; 1784 } 1785 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1786 (unsigned)(gtt_size / (1024 * 1024))); 1787 1788 /* Initialize preemptible memory pool */ 1789 r = amdgpu_preempt_mgr_init(adev); 1790 if (r) { 1791 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1792 return r; 1793 } 1794 1795 /* Initialize various on-chip memory pools */ 1796 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1797 if (r) { 1798 DRM_ERROR("Failed initializing GDS heap.\n"); 1799 return r; 1800 } 1801 1802 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1803 if (r) { 1804 DRM_ERROR("Failed initializing gws heap.\n"); 1805 return r; 1806 } 1807 1808 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1809 if (r) { 1810 DRM_ERROR("Failed initializing oa heap.\n"); 1811 return r; 1812 } 1813 1814 return 0; 1815 } 1816 1817 /* 1818 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1819 */ 1820 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1821 { 1822 if (!adev->mman.initialized) 1823 return; 1824 1825 amdgpu_ttm_training_reserve_vram_fini(adev); 1826 /* return the stolen vga memory back to VRAM */ 1827 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1828 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1829 /* return the IP Discovery TMR memory back to VRAM */ 1830 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1831 if (adev->mman.stolen_reserved_size) 1832 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1833 NULL, NULL); 1834 amdgpu_ttm_fw_reserve_vram_fini(adev); 1835 1836 amdgpu_vram_mgr_fini(adev); 1837 amdgpu_gtt_mgr_fini(adev); 1838 amdgpu_preempt_mgr_fini(adev); 1839 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1840 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1841 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1842 ttm_device_fini(&adev->mman.bdev); 1843 adev->mman.initialized = false; 1844 DRM_INFO("amdgpu: ttm finalized\n"); 1845 } 1846 1847 /** 1848 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1849 * 1850 * @adev: amdgpu_device pointer 1851 * @enable: true when we can use buffer functions. 1852 * 1853 * Enable/disable use of buffer functions during suspend/resume. This should 1854 * only be called at bootup or when userspace isn't running. 1855 */ 1856 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1857 { 1858 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1859 uint64_t size; 1860 int r; 1861 1862 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1863 adev->mman.buffer_funcs_enabled == enable) 1864 return; 1865 1866 if (enable) { 1867 struct amdgpu_ring *ring; 1868 struct drm_gpu_scheduler *sched; 1869 1870 ring = adev->mman.buffer_funcs_ring; 1871 sched = &ring->sched; 1872 r = drm_sched_entity_init(&adev->mman.entity, 1873 DRM_SCHED_PRIORITY_KERNEL, &sched, 1874 1, NULL); 1875 if (r) { 1876 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1877 r); 1878 return; 1879 } 1880 } else { 1881 drm_sched_entity_destroy(&adev->mman.entity); 1882 dma_fence_put(man->move); 1883 man->move = NULL; 1884 } 1885 1886 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1887 if (enable) 1888 size = adev->gmc.real_vram_size; 1889 else 1890 size = adev->gmc.visible_vram_size; 1891 man->size = size >> PAGE_SHIFT; 1892 adev->mman.buffer_funcs_enabled = enable; 1893 } 1894 1895 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1896 uint64_t dst_offset, uint32_t byte_count, 1897 struct dma_resv *resv, 1898 struct dma_fence **fence, bool direct_submit, 1899 bool vm_needs_flush, bool tmz) 1900 { 1901 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1902 AMDGPU_IB_POOL_DELAYED; 1903 struct amdgpu_device *adev = ring->adev; 1904 struct amdgpu_job *job; 1905 1906 uint32_t max_bytes; 1907 unsigned num_loops, num_dw; 1908 unsigned i; 1909 int r; 1910 1911 if (direct_submit && !ring->sched.ready) { 1912 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1913 return -EINVAL; 1914 } 1915 1916 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1917 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1918 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1919 1920 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1921 if (r) 1922 return r; 1923 1924 if (vm_needs_flush) { 1925 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1926 adev->gmc.pdb0_bo : adev->gart.bo); 1927 job->vm_needs_flush = true; 1928 } 1929 if (resv) { 1930 r = amdgpu_sync_resv(adev, &job->sync, resv, 1931 AMDGPU_SYNC_ALWAYS, 1932 AMDGPU_FENCE_OWNER_UNDEFINED); 1933 if (r) { 1934 DRM_ERROR("sync failed (%d).\n", r); 1935 goto error_free; 1936 } 1937 } 1938 1939 for (i = 0; i < num_loops; i++) { 1940 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1941 1942 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1943 dst_offset, cur_size_in_bytes, tmz); 1944 1945 src_offset += cur_size_in_bytes; 1946 dst_offset += cur_size_in_bytes; 1947 byte_count -= cur_size_in_bytes; 1948 } 1949 1950 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1951 WARN_ON(job->ibs[0].length_dw > num_dw); 1952 if (direct_submit) 1953 r = amdgpu_job_submit_direct(job, ring, fence); 1954 else 1955 r = amdgpu_job_submit(job, &adev->mman.entity, 1956 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1957 if (r) 1958 goto error_free; 1959 1960 return r; 1961 1962 error_free: 1963 amdgpu_job_free(job); 1964 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1965 return r; 1966 } 1967 1968 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1969 uint32_t src_data, 1970 struct dma_resv *resv, 1971 struct dma_fence **fence) 1972 { 1973 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1974 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1975 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1976 1977 struct amdgpu_res_cursor cursor; 1978 unsigned int num_loops, num_dw; 1979 uint64_t num_bytes; 1980 1981 struct amdgpu_job *job; 1982 int r; 1983 1984 if (!adev->mman.buffer_funcs_enabled) { 1985 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1986 return -EINVAL; 1987 } 1988 1989 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) { 1990 DRM_ERROR("Trying to clear preemptible memory.\n"); 1991 return -EINVAL; 1992 } 1993 1994 if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1995 r = amdgpu_ttm_alloc_gart(&bo->tbo); 1996 if (r) 1997 return r; 1998 } 1999 2000 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; 2001 num_loops = 0; 2002 2003 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2004 while (cursor.remaining) { 2005 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 2006 amdgpu_res_next(&cursor, cursor.size); 2007 } 2008 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2009 2010 /* for IB padding */ 2011 num_dw += 64; 2012 2013 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2014 &job); 2015 if (r) 2016 return r; 2017 2018 if (resv) { 2019 r = amdgpu_sync_resv(adev, &job->sync, resv, 2020 AMDGPU_SYNC_ALWAYS, 2021 AMDGPU_FENCE_OWNER_UNDEFINED); 2022 if (r) { 2023 DRM_ERROR("sync failed (%d).\n", r); 2024 goto error_free; 2025 } 2026 } 2027 2028 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2029 while (cursor.remaining) { 2030 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2031 uint64_t dst_addr = cursor.start; 2032 2033 dst_addr += amdgpu_ttm_domain_start(adev, 2034 bo->tbo.resource->mem_type); 2035 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2036 cur_size); 2037 2038 amdgpu_res_next(&cursor, cur_size); 2039 } 2040 2041 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2042 WARN_ON(job->ibs[0].length_dw > num_dw); 2043 r = amdgpu_job_submit(job, &adev->mman.entity, 2044 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2045 if (r) 2046 goto error_free; 2047 2048 return 0; 2049 2050 error_free: 2051 amdgpu_job_free(job); 2052 return r; 2053 } 2054 2055 /** 2056 * amdgpu_ttm_evict_resources - evict memory buffers 2057 * @adev: amdgpu device object 2058 * @mem_type: evicted BO's memory type 2059 * 2060 * Evicts all @mem_type buffers on the lru list of the memory type. 2061 * 2062 * Returns: 2063 * 0 for success or a negative error code on failure. 2064 */ 2065 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2066 { 2067 struct ttm_resource_manager *man; 2068 2069 switch (mem_type) { 2070 case TTM_PL_VRAM: 2071 case TTM_PL_TT: 2072 case AMDGPU_PL_GWS: 2073 case AMDGPU_PL_GDS: 2074 case AMDGPU_PL_OA: 2075 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2076 break; 2077 default: 2078 DRM_ERROR("Trying to evict invalid memory type\n"); 2079 return -EINVAL; 2080 } 2081 2082 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2083 } 2084 2085 #if defined(CONFIG_DEBUG_FS) 2086 2087 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2088 { 2089 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2090 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2091 TTM_PL_VRAM); 2092 struct drm_printer p = drm_seq_file_printer(m); 2093 2094 man->func->debug(man, &p); 2095 return 0; 2096 } 2097 2098 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2099 { 2100 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2101 2102 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2103 } 2104 2105 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2106 { 2107 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2108 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2109 TTM_PL_TT); 2110 struct drm_printer p = drm_seq_file_printer(m); 2111 2112 man->func->debug(man, &p); 2113 return 0; 2114 } 2115 2116 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2117 { 2118 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2119 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2120 AMDGPU_PL_GDS); 2121 struct drm_printer p = drm_seq_file_printer(m); 2122 2123 man->func->debug(man, &p); 2124 return 0; 2125 } 2126 2127 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2128 { 2129 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2130 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2131 AMDGPU_PL_GWS); 2132 struct drm_printer p = drm_seq_file_printer(m); 2133 2134 man->func->debug(man, &p); 2135 return 0; 2136 } 2137 2138 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2139 { 2140 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2141 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2142 AMDGPU_PL_OA); 2143 struct drm_printer p = drm_seq_file_printer(m); 2144 2145 man->func->debug(man, &p); 2146 return 0; 2147 } 2148 2149 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2150 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2151 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2152 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2153 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2154 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2155 2156 /* 2157 * amdgpu_ttm_vram_read - Linear read access to VRAM 2158 * 2159 * Accesses VRAM via MMIO for debugging purposes. 2160 */ 2161 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2162 size_t size, loff_t *pos) 2163 { 2164 struct amdgpu_device *adev = file_inode(f)->i_private; 2165 ssize_t result = 0; 2166 2167 if (size & 0x3 || *pos & 0x3) 2168 return -EINVAL; 2169 2170 if (*pos >= adev->gmc.mc_vram_size) 2171 return -ENXIO; 2172 2173 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2174 while (size) { 2175 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2176 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2177 2178 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2179 if (copy_to_user(buf, value, bytes)) 2180 return -EFAULT; 2181 2182 result += bytes; 2183 buf += bytes; 2184 *pos += bytes; 2185 size -= bytes; 2186 } 2187 2188 return result; 2189 } 2190 2191 /* 2192 * amdgpu_ttm_vram_write - Linear write access to VRAM 2193 * 2194 * Accesses VRAM via MMIO for debugging purposes. 2195 */ 2196 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2197 size_t size, loff_t *pos) 2198 { 2199 struct amdgpu_device *adev = file_inode(f)->i_private; 2200 ssize_t result = 0; 2201 int r; 2202 2203 if (size & 0x3 || *pos & 0x3) 2204 return -EINVAL; 2205 2206 if (*pos >= adev->gmc.mc_vram_size) 2207 return -ENXIO; 2208 2209 while (size) { 2210 uint32_t value; 2211 2212 if (*pos >= adev->gmc.mc_vram_size) 2213 return result; 2214 2215 r = get_user(value, (uint32_t *)buf); 2216 if (r) 2217 return r; 2218 2219 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2220 2221 result += 4; 2222 buf += 4; 2223 *pos += 4; 2224 size -= 4; 2225 } 2226 2227 return result; 2228 } 2229 2230 static const struct file_operations amdgpu_ttm_vram_fops = { 2231 .owner = THIS_MODULE, 2232 .read = amdgpu_ttm_vram_read, 2233 .write = amdgpu_ttm_vram_write, 2234 .llseek = default_llseek, 2235 }; 2236 2237 /* 2238 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2239 * 2240 * This function is used to read memory that has been mapped to the 2241 * GPU and the known addresses are not physical addresses but instead 2242 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2243 */ 2244 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2245 size_t size, loff_t *pos) 2246 { 2247 struct amdgpu_device *adev = file_inode(f)->i_private; 2248 struct iommu_domain *dom; 2249 ssize_t result = 0; 2250 int r; 2251 2252 /* retrieve the IOMMU domain if any for this device */ 2253 dom = iommu_get_domain_for_dev(adev->dev); 2254 2255 while (size) { 2256 phys_addr_t addr = *pos & PAGE_MASK; 2257 loff_t off = *pos & ~PAGE_MASK; 2258 size_t bytes = PAGE_SIZE - off; 2259 unsigned long pfn; 2260 struct page *p; 2261 void *ptr; 2262 2263 bytes = bytes < size ? bytes : size; 2264 2265 /* Translate the bus address to a physical address. If 2266 * the domain is NULL it means there is no IOMMU active 2267 * and the address translation is the identity 2268 */ 2269 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2270 2271 pfn = addr >> PAGE_SHIFT; 2272 if (!pfn_valid(pfn)) 2273 return -EPERM; 2274 2275 p = pfn_to_page(pfn); 2276 if (p->mapping != adev->mman.bdev.dev_mapping) 2277 return -EPERM; 2278 2279 ptr = kmap(p); 2280 r = copy_to_user(buf, ptr + off, bytes); 2281 kunmap(p); 2282 if (r) 2283 return -EFAULT; 2284 2285 size -= bytes; 2286 *pos += bytes; 2287 result += bytes; 2288 } 2289 2290 return result; 2291 } 2292 2293 /* 2294 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2295 * 2296 * This function is used to write memory that has been mapped to the 2297 * GPU and the known addresses are not physical addresses but instead 2298 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2299 */ 2300 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2301 size_t size, loff_t *pos) 2302 { 2303 struct amdgpu_device *adev = file_inode(f)->i_private; 2304 struct iommu_domain *dom; 2305 ssize_t result = 0; 2306 int r; 2307 2308 dom = iommu_get_domain_for_dev(adev->dev); 2309 2310 while (size) { 2311 phys_addr_t addr = *pos & PAGE_MASK; 2312 loff_t off = *pos & ~PAGE_MASK; 2313 size_t bytes = PAGE_SIZE - off; 2314 unsigned long pfn; 2315 struct page *p; 2316 void *ptr; 2317 2318 bytes = bytes < size ? bytes : size; 2319 2320 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2321 2322 pfn = addr >> PAGE_SHIFT; 2323 if (!pfn_valid(pfn)) 2324 return -EPERM; 2325 2326 p = pfn_to_page(pfn); 2327 if (p->mapping != adev->mman.bdev.dev_mapping) 2328 return -EPERM; 2329 2330 ptr = kmap(p); 2331 r = copy_from_user(ptr + off, buf, bytes); 2332 kunmap(p); 2333 if (r) 2334 return -EFAULT; 2335 2336 size -= bytes; 2337 *pos += bytes; 2338 result += bytes; 2339 } 2340 2341 return result; 2342 } 2343 2344 static const struct file_operations amdgpu_ttm_iomem_fops = { 2345 .owner = THIS_MODULE, 2346 .read = amdgpu_iomem_read, 2347 .write = amdgpu_iomem_write, 2348 .llseek = default_llseek 2349 }; 2350 2351 #endif 2352 2353 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2354 { 2355 #if defined(CONFIG_DEBUG_FS) 2356 struct drm_minor *minor = adev_to_drm(adev)->primary; 2357 struct dentry *root = minor->debugfs_root; 2358 2359 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2360 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2361 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2362 &amdgpu_ttm_iomem_fops); 2363 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2364 &amdgpu_mm_vram_table_fops); 2365 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2366 &amdgpu_mm_tt_table_fops); 2367 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2368 &amdgpu_mm_gds_table_fops); 2369 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2370 &amdgpu_mm_gws_table_fops); 2371 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2372 &amdgpu_mm_oa_table_fops); 2373 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2374 &amdgpu_ttm_page_pool_fops); 2375 #endif 2376 } 2377