1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <ttm/ttm_bo_api.h> 33 #include <ttm/ttm_bo_driver.h> 34 #include <ttm/ttm_placement.h> 35 #include <ttm/ttm_module.h> 36 #include <ttm/ttm_page_alloc.h> 37 #include <drm/drmP.h> 38 #include <drm/amdgpu_drm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swiotlb.h> 42 #include <linux/swap.h> 43 #include <linux/pagemap.h> 44 #include <linux/debugfs.h> 45 #include "amdgpu.h" 46 #include "bif/bif_4_1_d.h" 47 48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 49 50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); 52 53 54 /* 55 * Global memory. 56 */ 57 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) 58 { 59 return ttm_mem_global_init(ref->object); 60 } 61 62 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) 63 { 64 ttm_mem_global_release(ref->object); 65 } 66 67 static int amdgpu_ttm_global_init(struct amdgpu_device *adev) 68 { 69 struct drm_global_reference *global_ref; 70 struct amdgpu_ring *ring; 71 struct amd_sched_rq *rq; 72 int r; 73 74 adev->mman.mem_global_referenced = false; 75 global_ref = &adev->mman.mem_global_ref; 76 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 77 global_ref->size = sizeof(struct ttm_mem_global); 78 global_ref->init = &amdgpu_ttm_mem_global_init; 79 global_ref->release = &amdgpu_ttm_mem_global_release; 80 r = drm_global_item_ref(global_ref); 81 if (r) { 82 DRM_ERROR("Failed setting up TTM memory accounting " 83 "subsystem.\n"); 84 goto error_mem; 85 } 86 87 adev->mman.bo_global_ref.mem_glob = 88 adev->mman.mem_global_ref.object; 89 global_ref = &adev->mman.bo_global_ref.ref; 90 global_ref->global_type = DRM_GLOBAL_TTM_BO; 91 global_ref->size = sizeof(struct ttm_bo_global); 92 global_ref->init = &ttm_bo_global_init; 93 global_ref->release = &ttm_bo_global_release; 94 r = drm_global_item_ref(global_ref); 95 if (r) { 96 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 97 goto error_bo; 98 } 99 100 ring = adev->mman.buffer_funcs_ring; 101 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; 102 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, 103 rq, amdgpu_sched_jobs); 104 if (r) { 105 DRM_ERROR("Failed setting up TTM BO move run queue.\n"); 106 goto error_entity; 107 } 108 109 adev->mman.mem_global_referenced = true; 110 111 return 0; 112 113 error_entity: 114 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 115 error_bo: 116 drm_global_item_unref(&adev->mman.mem_global_ref); 117 error_mem: 118 return r; 119 } 120 121 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) 122 { 123 if (adev->mman.mem_global_referenced) { 124 amd_sched_entity_fini(adev->mman.entity.sched, 125 &adev->mman.entity); 126 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 127 drm_global_item_unref(&adev->mman.mem_global_ref); 128 adev->mman.mem_global_referenced = false; 129 } 130 } 131 132 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 133 { 134 return 0; 135 } 136 137 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 138 struct ttm_mem_type_manager *man) 139 { 140 struct amdgpu_device *adev; 141 142 adev = amdgpu_ttm_adev(bdev); 143 144 switch (type) { 145 case TTM_PL_SYSTEM: 146 /* System memory */ 147 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 148 man->available_caching = TTM_PL_MASK_CACHING; 149 man->default_caching = TTM_PL_FLAG_CACHED; 150 break; 151 case TTM_PL_TT: 152 man->func = &amdgpu_gtt_mgr_func; 153 man->gpu_offset = adev->mc.gtt_start; 154 man->available_caching = TTM_PL_MASK_CACHING; 155 man->default_caching = TTM_PL_FLAG_CACHED; 156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 157 break; 158 case TTM_PL_VRAM: 159 /* "On-card" video ram */ 160 man->func = &amdgpu_vram_mgr_func; 161 man->gpu_offset = adev->mc.vram_start; 162 man->flags = TTM_MEMTYPE_FLAG_FIXED | 163 TTM_MEMTYPE_FLAG_MAPPABLE; 164 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 165 man->default_caching = TTM_PL_FLAG_WC; 166 break; 167 case AMDGPU_PL_GDS: 168 case AMDGPU_PL_GWS: 169 case AMDGPU_PL_OA: 170 /* On-chip GDS memory*/ 171 man->func = &ttm_bo_manager_func; 172 man->gpu_offset = 0; 173 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; 174 man->available_caching = TTM_PL_FLAG_UNCACHED; 175 man->default_caching = TTM_PL_FLAG_UNCACHED; 176 break; 177 default: 178 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 179 return -EINVAL; 180 } 181 return 0; 182 } 183 184 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 185 struct ttm_placement *placement) 186 { 187 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 188 struct amdgpu_bo *abo; 189 static struct ttm_place placements = { 190 .fpfn = 0, 191 .lpfn = 0, 192 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 193 }; 194 unsigned i; 195 196 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { 197 placement->placement = &placements; 198 placement->busy_placement = &placements; 199 placement->num_placement = 1; 200 placement->num_busy_placement = 1; 201 return; 202 } 203 abo = container_of(bo, struct amdgpu_bo, tbo); 204 switch (bo->mem.mem_type) { 205 case TTM_PL_VRAM: 206 if (adev->mman.buffer_funcs_ring->ready == false) { 207 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 208 } else { 209 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 210 for (i = 0; i < abo->placement.num_placement; ++i) { 211 if (!(abo->placements[i].flags & 212 TTM_PL_FLAG_TT)) 213 continue; 214 215 if (abo->placements[i].lpfn) 216 continue; 217 218 /* set an upper limit to force directly 219 * allocating address space for the BO. 220 */ 221 abo->placements[i].lpfn = 222 adev->mc.gtt_size >> PAGE_SHIFT; 223 } 224 } 225 break; 226 case TTM_PL_TT: 227 default: 228 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 229 } 230 *placement = abo->placement; 231 } 232 233 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 234 { 235 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo); 236 237 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 238 return -EPERM; 239 return drm_vma_node_verify_access(&abo->gem_base.vma_node, 240 filp->private_data); 241 } 242 243 static void amdgpu_move_null(struct ttm_buffer_object *bo, 244 struct ttm_mem_reg *new_mem) 245 { 246 struct ttm_mem_reg *old_mem = &bo->mem; 247 248 BUG_ON(old_mem->mm_node != NULL); 249 *old_mem = *new_mem; 250 new_mem->mm_node = NULL; 251 } 252 253 static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 254 struct drm_mm_node *mm_node, 255 struct ttm_mem_reg *mem, 256 uint64_t *addr) 257 { 258 int r; 259 260 switch (mem->mem_type) { 261 case TTM_PL_TT: 262 r = amdgpu_ttm_bind(bo, mem); 263 if (r) 264 return r; 265 266 case TTM_PL_VRAM: 267 *addr = mm_node->start << PAGE_SHIFT; 268 *addr += bo->bdev->man[mem->mem_type].gpu_offset; 269 break; 270 default: 271 DRM_ERROR("Unknown placement %d\n", mem->mem_type); 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 279 bool evict, bool no_wait_gpu, 280 struct ttm_mem_reg *new_mem, 281 struct ttm_mem_reg *old_mem) 282 { 283 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 284 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 285 286 struct drm_mm_node *old_mm, *new_mm; 287 uint64_t old_start, old_size, new_start, new_size; 288 unsigned long num_pages; 289 struct dma_fence *fence = NULL; 290 int r; 291 292 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); 293 294 if (!ring->ready) { 295 DRM_ERROR("Trying to move memory with ring turned off.\n"); 296 return -EINVAL; 297 } 298 299 old_mm = old_mem->mm_node; 300 r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start); 301 if (r) 302 return r; 303 old_size = old_mm->size; 304 305 306 new_mm = new_mem->mm_node; 307 r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start); 308 if (r) 309 return r; 310 new_size = new_mm->size; 311 312 num_pages = new_mem->num_pages; 313 while (num_pages) { 314 unsigned long cur_pages = min(old_size, new_size); 315 struct dma_fence *next; 316 317 r = amdgpu_copy_buffer(ring, old_start, new_start, 318 cur_pages * PAGE_SIZE, 319 bo->resv, &next, false); 320 if (r) 321 goto error; 322 323 dma_fence_put(fence); 324 fence = next; 325 326 num_pages -= cur_pages; 327 if (!num_pages) 328 break; 329 330 old_size -= cur_pages; 331 if (!old_size) { 332 r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem, 333 &old_start); 334 if (r) 335 goto error; 336 old_size = old_mm->size; 337 } else { 338 old_start += cur_pages * PAGE_SIZE; 339 } 340 341 new_size -= cur_pages; 342 if (!new_size) { 343 r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem, 344 &new_start); 345 if (r) 346 goto error; 347 348 new_size = new_mm->size; 349 } else { 350 new_start += cur_pages * PAGE_SIZE; 351 } 352 } 353 354 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 355 dma_fence_put(fence); 356 return r; 357 358 error: 359 if (fence) 360 dma_fence_wait(fence, false); 361 dma_fence_put(fence); 362 return r; 363 } 364 365 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, 366 bool evict, bool interruptible, 367 bool no_wait_gpu, 368 struct ttm_mem_reg *new_mem) 369 { 370 struct amdgpu_device *adev; 371 struct ttm_mem_reg *old_mem = &bo->mem; 372 struct ttm_mem_reg tmp_mem; 373 struct ttm_place placements; 374 struct ttm_placement placement; 375 int r; 376 377 adev = amdgpu_ttm_adev(bo->bdev); 378 tmp_mem = *new_mem; 379 tmp_mem.mm_node = NULL; 380 placement.num_placement = 1; 381 placement.placement = &placements; 382 placement.num_busy_placement = 1; 383 placement.busy_placement = &placements; 384 placements.fpfn = 0; 385 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT; 386 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 387 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 388 interruptible, no_wait_gpu); 389 if (unlikely(r)) { 390 return r; 391 } 392 393 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 394 if (unlikely(r)) { 395 goto out_cleanup; 396 } 397 398 r = ttm_tt_bind(bo->ttm, &tmp_mem); 399 if (unlikely(r)) { 400 goto out_cleanup; 401 } 402 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 403 if (unlikely(r)) { 404 goto out_cleanup; 405 } 406 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); 407 out_cleanup: 408 ttm_bo_mem_put(bo, &tmp_mem); 409 return r; 410 } 411 412 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, 413 bool evict, bool interruptible, 414 bool no_wait_gpu, 415 struct ttm_mem_reg *new_mem) 416 { 417 struct amdgpu_device *adev; 418 struct ttm_mem_reg *old_mem = &bo->mem; 419 struct ttm_mem_reg tmp_mem; 420 struct ttm_placement placement; 421 struct ttm_place placements; 422 int r; 423 424 adev = amdgpu_ttm_adev(bo->bdev); 425 tmp_mem = *new_mem; 426 tmp_mem.mm_node = NULL; 427 placement.num_placement = 1; 428 placement.placement = &placements; 429 placement.num_busy_placement = 1; 430 placement.busy_placement = &placements; 431 placements.fpfn = 0; 432 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT; 433 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 434 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 435 interruptible, no_wait_gpu); 436 if (unlikely(r)) { 437 return r; 438 } 439 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); 440 if (unlikely(r)) { 441 goto out_cleanup; 442 } 443 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 444 if (unlikely(r)) { 445 goto out_cleanup; 446 } 447 out_cleanup: 448 ttm_bo_mem_put(bo, &tmp_mem); 449 return r; 450 } 451 452 static int amdgpu_bo_move(struct ttm_buffer_object *bo, 453 bool evict, bool interruptible, 454 bool no_wait_gpu, 455 struct ttm_mem_reg *new_mem) 456 { 457 struct amdgpu_device *adev; 458 struct amdgpu_bo *abo; 459 struct ttm_mem_reg *old_mem = &bo->mem; 460 int r; 461 462 /* Can't move a pinned BO */ 463 abo = container_of(bo, struct amdgpu_bo, tbo); 464 if (WARN_ON_ONCE(abo->pin_count > 0)) 465 return -EINVAL; 466 467 adev = amdgpu_ttm_adev(bo->bdev); 468 469 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 470 amdgpu_move_null(bo, new_mem); 471 return 0; 472 } 473 if ((old_mem->mem_type == TTM_PL_TT && 474 new_mem->mem_type == TTM_PL_SYSTEM) || 475 (old_mem->mem_type == TTM_PL_SYSTEM && 476 new_mem->mem_type == TTM_PL_TT)) { 477 /* bind is enough */ 478 amdgpu_move_null(bo, new_mem); 479 return 0; 480 } 481 if (adev->mman.buffer_funcs == NULL || 482 adev->mman.buffer_funcs_ring == NULL || 483 !adev->mman.buffer_funcs_ring->ready) { 484 /* use memcpy */ 485 goto memcpy; 486 } 487 488 if (old_mem->mem_type == TTM_PL_VRAM && 489 new_mem->mem_type == TTM_PL_SYSTEM) { 490 r = amdgpu_move_vram_ram(bo, evict, interruptible, 491 no_wait_gpu, new_mem); 492 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 493 new_mem->mem_type == TTM_PL_VRAM) { 494 r = amdgpu_move_ram_vram(bo, evict, interruptible, 495 no_wait_gpu, new_mem); 496 } else { 497 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 498 } 499 500 if (r) { 501 memcpy: 502 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); 503 if (r) { 504 return r; 505 } 506 } 507 508 /* update statistics */ 509 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 510 return 0; 511 } 512 513 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 514 { 515 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 516 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 517 518 mem->bus.addr = NULL; 519 mem->bus.offset = 0; 520 mem->bus.size = mem->num_pages << PAGE_SHIFT; 521 mem->bus.base = 0; 522 mem->bus.is_iomem = false; 523 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 524 return -EINVAL; 525 switch (mem->mem_type) { 526 case TTM_PL_SYSTEM: 527 /* system memory */ 528 return 0; 529 case TTM_PL_TT: 530 break; 531 case TTM_PL_VRAM: 532 if (mem->start == AMDGPU_BO_INVALID_OFFSET) 533 return -EINVAL; 534 535 mem->bus.offset = mem->start << PAGE_SHIFT; 536 /* check if it's visible */ 537 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) 538 return -EINVAL; 539 mem->bus.base = adev->mc.aper_base; 540 mem->bus.is_iomem = true; 541 #ifdef __alpha__ 542 /* 543 * Alpha: use bus.addr to hold the ioremap() return, 544 * so we can modify bus.base below. 545 */ 546 if (mem->placement & TTM_PL_FLAG_WC) 547 mem->bus.addr = 548 ioremap_wc(mem->bus.base + mem->bus.offset, 549 mem->bus.size); 550 else 551 mem->bus.addr = 552 ioremap_nocache(mem->bus.base + mem->bus.offset, 553 mem->bus.size); 554 if (!mem->bus.addr) 555 return -ENOMEM; 556 557 /* 558 * Alpha: Use just the bus offset plus 559 * the hose/domain memory base for bus.base. 560 * It then can be used to build PTEs for VRAM 561 * access, as done in ttm_bo_vm_fault(). 562 */ 563 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 564 adev->ddev->hose->dense_mem_base; 565 #endif 566 break; 567 default: 568 return -EINVAL; 569 } 570 return 0; 571 } 572 573 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 574 { 575 } 576 577 /* 578 * TTM backend functions. 579 */ 580 struct amdgpu_ttm_gup_task_list { 581 struct list_head list; 582 struct task_struct *task; 583 }; 584 585 struct amdgpu_ttm_tt { 586 struct ttm_dma_tt ttm; 587 struct amdgpu_device *adev; 588 u64 offset; 589 uint64_t userptr; 590 struct mm_struct *usermm; 591 uint32_t userflags; 592 spinlock_t guptasklock; 593 struct list_head guptasks; 594 atomic_t mmu_invalidations; 595 struct list_head list; 596 }; 597 598 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) 599 { 600 struct amdgpu_ttm_tt *gtt = (void *)ttm; 601 unsigned int flags = 0; 602 unsigned pinned = 0; 603 int r; 604 605 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 606 flags |= FOLL_WRITE; 607 608 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { 609 /* check that we only use anonymous memory 610 to prevent problems with writeback */ 611 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 612 struct vm_area_struct *vma; 613 614 vma = find_vma(gtt->usermm, gtt->userptr); 615 if (!vma || vma->vm_file || vma->vm_end < end) 616 return -EPERM; 617 } 618 619 do { 620 unsigned num_pages = ttm->num_pages - pinned; 621 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 622 struct page **p = pages + pinned; 623 struct amdgpu_ttm_gup_task_list guptask; 624 625 guptask.task = current; 626 spin_lock(>t->guptasklock); 627 list_add(&guptask.list, >t->guptasks); 628 spin_unlock(>t->guptasklock); 629 630 r = get_user_pages(userptr, num_pages, flags, p, NULL); 631 632 spin_lock(>t->guptasklock); 633 list_del(&guptask.list); 634 spin_unlock(>t->guptasklock); 635 636 if (r < 0) 637 goto release_pages; 638 639 pinned += r; 640 641 } while (pinned < ttm->num_pages); 642 643 return 0; 644 645 release_pages: 646 release_pages(pages, pinned, 0); 647 return r; 648 } 649 650 /* prepare the sg table with the user pages */ 651 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 652 { 653 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 654 struct amdgpu_ttm_tt *gtt = (void *)ttm; 655 unsigned nents; 656 int r; 657 658 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 659 enum dma_data_direction direction = write ? 660 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 661 662 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 663 ttm->num_pages << PAGE_SHIFT, 664 GFP_KERNEL); 665 if (r) 666 goto release_sg; 667 668 r = -ENOMEM; 669 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 670 if (nents != ttm->sg->nents) 671 goto release_sg; 672 673 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 674 gtt->ttm.dma_address, ttm->num_pages); 675 676 return 0; 677 678 release_sg: 679 kfree(ttm->sg); 680 return r; 681 } 682 683 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 684 { 685 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 686 struct amdgpu_ttm_tt *gtt = (void *)ttm; 687 struct sg_page_iter sg_iter; 688 689 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 690 enum dma_data_direction direction = write ? 691 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 692 693 /* double check that we don't free the table twice */ 694 if (!ttm->sg->sgl) 695 return; 696 697 /* free the sg table and pages again */ 698 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 699 700 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { 701 struct page *page = sg_page_iter_page(&sg_iter); 702 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 703 set_page_dirty(page); 704 705 mark_page_accessed(page); 706 put_page(page); 707 } 708 709 sg_free_table(ttm->sg); 710 } 711 712 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 713 struct ttm_mem_reg *bo_mem) 714 { 715 struct amdgpu_ttm_tt *gtt = (void*)ttm; 716 int r; 717 718 if (gtt->userptr) { 719 r = amdgpu_ttm_tt_pin_userptr(ttm); 720 if (r) { 721 DRM_ERROR("failed to pin userptr\n"); 722 return r; 723 } 724 } 725 if (!ttm->num_pages) { 726 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 727 ttm->num_pages, bo_mem, ttm); 728 } 729 730 if (bo_mem->mem_type == AMDGPU_PL_GDS || 731 bo_mem->mem_type == AMDGPU_PL_GWS || 732 bo_mem->mem_type == AMDGPU_PL_OA) 733 return -EINVAL; 734 735 return 0; 736 } 737 738 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) 739 { 740 struct amdgpu_ttm_tt *gtt = (void *)ttm; 741 742 return gtt && !list_empty(>t->list); 743 } 744 745 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) 746 { 747 struct ttm_tt *ttm = bo->ttm; 748 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 749 uint32_t flags; 750 int r; 751 752 if (!ttm || amdgpu_ttm_is_bound(ttm)) 753 return 0; 754 755 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo, 756 NULL, bo_mem); 757 if (r) { 758 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r); 759 return r; 760 } 761 762 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 763 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 764 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, 765 ttm->pages, gtt->ttm.dma_address, flags); 766 767 if (r) { 768 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 769 ttm->num_pages, gtt->offset); 770 return r; 771 } 772 spin_lock(>t->adev->gtt_list_lock); 773 list_add_tail(>t->list, >t->adev->gtt_list); 774 spin_unlock(>t->adev->gtt_list_lock); 775 return 0; 776 } 777 778 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) 779 { 780 struct amdgpu_ttm_tt *gtt, *tmp; 781 struct ttm_mem_reg bo_mem; 782 uint32_t flags; 783 int r; 784 785 bo_mem.mem_type = TTM_PL_TT; 786 spin_lock(&adev->gtt_list_lock); 787 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) { 788 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem); 789 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, 790 gtt->ttm.ttm.pages, gtt->ttm.dma_address, 791 flags); 792 if (r) { 793 spin_unlock(&adev->gtt_list_lock); 794 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 795 gtt->ttm.ttm.num_pages, gtt->offset); 796 return r; 797 } 798 } 799 spin_unlock(&adev->gtt_list_lock); 800 return 0; 801 } 802 803 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 804 { 805 struct amdgpu_ttm_tt *gtt = (void *)ttm; 806 807 if (gtt->userptr) 808 amdgpu_ttm_tt_unpin_userptr(ttm); 809 810 if (!amdgpu_ttm_is_bound(ttm)) 811 return 0; 812 813 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 814 if (gtt->adev->gart.ready) 815 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); 816 817 spin_lock(>t->adev->gtt_list_lock); 818 list_del_init(>t->list); 819 spin_unlock(>t->adev->gtt_list_lock); 820 821 return 0; 822 } 823 824 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 825 { 826 struct amdgpu_ttm_tt *gtt = (void *)ttm; 827 828 ttm_dma_tt_fini(>t->ttm); 829 kfree(gtt); 830 } 831 832 static struct ttm_backend_func amdgpu_backend_func = { 833 .bind = &amdgpu_ttm_backend_bind, 834 .unbind = &amdgpu_ttm_backend_unbind, 835 .destroy = &amdgpu_ttm_backend_destroy, 836 }; 837 838 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, 839 unsigned long size, uint32_t page_flags, 840 struct page *dummy_read_page) 841 { 842 struct amdgpu_device *adev; 843 struct amdgpu_ttm_tt *gtt; 844 845 adev = amdgpu_ttm_adev(bdev); 846 847 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 848 if (gtt == NULL) { 849 return NULL; 850 } 851 gtt->ttm.ttm.func = &amdgpu_backend_func; 852 gtt->adev = adev; 853 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 854 kfree(gtt); 855 return NULL; 856 } 857 INIT_LIST_HEAD(>t->list); 858 return >t->ttm.ttm; 859 } 860 861 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) 862 { 863 struct amdgpu_device *adev; 864 struct amdgpu_ttm_tt *gtt = (void *)ttm; 865 unsigned i; 866 int r; 867 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 868 869 if (ttm->state != tt_unpopulated) 870 return 0; 871 872 if (gtt && gtt->userptr) { 873 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 874 if (!ttm->sg) 875 return -ENOMEM; 876 877 ttm->page_flags |= TTM_PAGE_FLAG_SG; 878 ttm->state = tt_unbound; 879 return 0; 880 } 881 882 if (slave && ttm->sg) { 883 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 884 gtt->ttm.dma_address, ttm->num_pages); 885 ttm->state = tt_unbound; 886 return 0; 887 } 888 889 adev = amdgpu_ttm_adev(ttm->bdev); 890 891 #ifdef CONFIG_SWIOTLB 892 if (swiotlb_nr_tbl()) { 893 return ttm_dma_populate(>t->ttm, adev->dev); 894 } 895 #endif 896 897 r = ttm_pool_populate(ttm); 898 if (r) { 899 return r; 900 } 901 902 for (i = 0; i < ttm->num_pages; i++) { 903 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], 904 0, PAGE_SIZE, 905 PCI_DMA_BIDIRECTIONAL); 906 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { 907 while (i--) { 908 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 909 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 910 gtt->ttm.dma_address[i] = 0; 911 } 912 ttm_pool_unpopulate(ttm); 913 return -EFAULT; 914 } 915 } 916 return 0; 917 } 918 919 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 920 { 921 struct amdgpu_device *adev; 922 struct amdgpu_ttm_tt *gtt = (void *)ttm; 923 unsigned i; 924 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 925 926 if (gtt && gtt->userptr) { 927 kfree(ttm->sg); 928 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 929 return; 930 } 931 932 if (slave) 933 return; 934 935 adev = amdgpu_ttm_adev(ttm->bdev); 936 937 #ifdef CONFIG_SWIOTLB 938 if (swiotlb_nr_tbl()) { 939 ttm_dma_unpopulate(>t->ttm, adev->dev); 940 return; 941 } 942 #endif 943 944 for (i = 0; i < ttm->num_pages; i++) { 945 if (gtt->ttm.dma_address[i]) { 946 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 947 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 948 } 949 } 950 951 ttm_pool_unpopulate(ttm); 952 } 953 954 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 955 uint32_t flags) 956 { 957 struct amdgpu_ttm_tt *gtt = (void *)ttm; 958 959 if (gtt == NULL) 960 return -EINVAL; 961 962 gtt->userptr = addr; 963 gtt->usermm = current->mm; 964 gtt->userflags = flags; 965 spin_lock_init(>t->guptasklock); 966 INIT_LIST_HEAD(>t->guptasks); 967 atomic_set(>t->mmu_invalidations, 0); 968 969 return 0; 970 } 971 972 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 973 { 974 struct amdgpu_ttm_tt *gtt = (void *)ttm; 975 976 if (gtt == NULL) 977 return NULL; 978 979 return gtt->usermm; 980 } 981 982 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 983 unsigned long end) 984 { 985 struct amdgpu_ttm_tt *gtt = (void *)ttm; 986 struct amdgpu_ttm_gup_task_list *entry; 987 unsigned long size; 988 989 if (gtt == NULL || !gtt->userptr) 990 return false; 991 992 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 993 if (gtt->userptr > end || gtt->userptr + size <= start) 994 return false; 995 996 spin_lock(>t->guptasklock); 997 list_for_each_entry(entry, >t->guptasks, list) { 998 if (entry->task == current) { 999 spin_unlock(>t->guptasklock); 1000 return false; 1001 } 1002 } 1003 spin_unlock(>t->guptasklock); 1004 1005 atomic_inc(>t->mmu_invalidations); 1006 1007 return true; 1008 } 1009 1010 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1011 int *last_invalidated) 1012 { 1013 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1014 int prev_invalidated = *last_invalidated; 1015 1016 *last_invalidated = atomic_read(>t->mmu_invalidations); 1017 return prev_invalidated != *last_invalidated; 1018 } 1019 1020 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1021 { 1022 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1023 1024 if (gtt == NULL) 1025 return false; 1026 1027 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1028 } 1029 1030 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1031 struct ttm_mem_reg *mem) 1032 { 1033 uint32_t flags = 0; 1034 1035 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1036 flags |= AMDGPU_PTE_VALID; 1037 1038 if (mem && mem->mem_type == TTM_PL_TT) { 1039 flags |= AMDGPU_PTE_SYSTEM; 1040 1041 if (ttm->caching_state == tt_cached) 1042 flags |= AMDGPU_PTE_SNOOPED; 1043 } 1044 1045 if (adev->asic_type >= CHIP_TONGA) 1046 flags |= AMDGPU_PTE_EXECUTABLE; 1047 1048 flags |= AMDGPU_PTE_READABLE; 1049 1050 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1051 flags |= AMDGPU_PTE_WRITEABLE; 1052 1053 return flags; 1054 } 1055 1056 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1057 const struct ttm_place *place) 1058 { 1059 if (bo->mem.mem_type == TTM_PL_VRAM && 1060 bo->mem.start == AMDGPU_BO_INVALID_OFFSET) { 1061 unsigned long num_pages = bo->mem.num_pages; 1062 struct drm_mm_node *node = bo->mem.mm_node; 1063 1064 /* Check each drm MM node individually */ 1065 while (num_pages) { 1066 if (place->fpfn < (node->start + node->size) && 1067 !(place->lpfn && place->lpfn <= node->start)) 1068 return true; 1069 1070 num_pages -= node->size; 1071 ++node; 1072 } 1073 1074 return false; 1075 } 1076 1077 return ttm_bo_eviction_valuable(bo, place); 1078 } 1079 1080 static struct ttm_bo_driver amdgpu_bo_driver = { 1081 .ttm_tt_create = &amdgpu_ttm_tt_create, 1082 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1083 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1084 .invalidate_caches = &amdgpu_invalidate_caches, 1085 .init_mem_type = &amdgpu_init_mem_type, 1086 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1087 .evict_flags = &amdgpu_evict_flags, 1088 .move = &amdgpu_bo_move, 1089 .verify_access = &amdgpu_verify_access, 1090 .move_notify = &amdgpu_bo_move_notify, 1091 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1092 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1093 .io_mem_free = &amdgpu_ttm_io_mem_free, 1094 }; 1095 1096 int amdgpu_ttm_init(struct amdgpu_device *adev) 1097 { 1098 int r; 1099 1100 r = amdgpu_ttm_global_init(adev); 1101 if (r) { 1102 return r; 1103 } 1104 /* No others user of address space so set it to 0 */ 1105 r = ttm_bo_device_init(&adev->mman.bdev, 1106 adev->mman.bo_global_ref.ref.object, 1107 &amdgpu_bo_driver, 1108 adev->ddev->anon_inode->i_mapping, 1109 DRM_FILE_PAGE_OFFSET, 1110 adev->need_dma32); 1111 if (r) { 1112 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1113 return r; 1114 } 1115 adev->mman.initialized = true; 1116 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1117 adev->mc.real_vram_size >> PAGE_SHIFT); 1118 if (r) { 1119 DRM_ERROR("Failed initializing VRAM heap.\n"); 1120 return r; 1121 } 1122 /* Change the size here instead of the init above so only lpfn is affected */ 1123 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 1124 1125 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, 1126 AMDGPU_GEM_DOMAIN_VRAM, 1127 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1128 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1129 NULL, NULL, &adev->stollen_vga_memory); 1130 if (r) { 1131 return r; 1132 } 1133 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1134 if (r) 1135 return r; 1136 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); 1137 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1138 if (r) { 1139 amdgpu_bo_unref(&adev->stollen_vga_memory); 1140 return r; 1141 } 1142 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1143 (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); 1144 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, 1145 adev->mc.gtt_size >> PAGE_SHIFT); 1146 if (r) { 1147 DRM_ERROR("Failed initializing GTT heap.\n"); 1148 return r; 1149 } 1150 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1151 (unsigned)(adev->mc.gtt_size / (1024 * 1024))); 1152 1153 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; 1154 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; 1155 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; 1156 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; 1157 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; 1158 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; 1159 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; 1160 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; 1161 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; 1162 /* GDS Memory */ 1163 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 1164 adev->gds.mem.total_size >> PAGE_SHIFT); 1165 if (r) { 1166 DRM_ERROR("Failed initializing GDS heap.\n"); 1167 return r; 1168 } 1169 1170 /* GWS */ 1171 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 1172 adev->gds.gws.total_size >> PAGE_SHIFT); 1173 if (r) { 1174 DRM_ERROR("Failed initializing gws heap.\n"); 1175 return r; 1176 } 1177 1178 /* OA */ 1179 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 1180 adev->gds.oa.total_size >> PAGE_SHIFT); 1181 if (r) { 1182 DRM_ERROR("Failed initializing oa heap.\n"); 1183 return r; 1184 } 1185 1186 r = amdgpu_ttm_debugfs_init(adev); 1187 if (r) { 1188 DRM_ERROR("Failed to init debugfs\n"); 1189 return r; 1190 } 1191 return 0; 1192 } 1193 1194 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1195 { 1196 int r; 1197 1198 if (!adev->mman.initialized) 1199 return; 1200 amdgpu_ttm_debugfs_fini(adev); 1201 if (adev->stollen_vga_memory) { 1202 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1203 if (r == 0) { 1204 amdgpu_bo_unpin(adev->stollen_vga_memory); 1205 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1206 } 1207 amdgpu_bo_unref(&adev->stollen_vga_memory); 1208 } 1209 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 1210 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 1211 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 1212 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 1213 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 1214 ttm_bo_device_release(&adev->mman.bdev); 1215 amdgpu_gart_fini(adev); 1216 amdgpu_ttm_global_fini(adev); 1217 adev->mman.initialized = false; 1218 DRM_INFO("amdgpu: ttm finalized\n"); 1219 } 1220 1221 /* this should only be called at bootup or when userspace 1222 * isn't running */ 1223 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) 1224 { 1225 struct ttm_mem_type_manager *man; 1226 1227 if (!adev->mman.initialized) 1228 return; 1229 1230 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 1231 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1232 man->size = size >> PAGE_SHIFT; 1233 } 1234 1235 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1236 { 1237 struct drm_file *file_priv; 1238 struct amdgpu_device *adev; 1239 1240 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 1241 return -EINVAL; 1242 1243 file_priv = filp->private_data; 1244 adev = file_priv->minor->dev->dev_private; 1245 if (adev == NULL) 1246 return -EINVAL; 1247 1248 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1249 } 1250 1251 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 1252 uint64_t src_offset, 1253 uint64_t dst_offset, 1254 uint32_t byte_count, 1255 struct reservation_object *resv, 1256 struct dma_fence **fence, bool direct_submit) 1257 { 1258 struct amdgpu_device *adev = ring->adev; 1259 struct amdgpu_job *job; 1260 1261 uint32_t max_bytes; 1262 unsigned num_loops, num_dw; 1263 unsigned i; 1264 int r; 1265 1266 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1267 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1268 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; 1269 1270 /* for IB padding */ 1271 while (num_dw & 0x7) 1272 num_dw++; 1273 1274 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1275 if (r) 1276 return r; 1277 1278 if (resv) { 1279 r = amdgpu_sync_resv(adev, &job->sync, resv, 1280 AMDGPU_FENCE_OWNER_UNDEFINED); 1281 if (r) { 1282 DRM_ERROR("sync failed (%d).\n", r); 1283 goto error_free; 1284 } 1285 } 1286 1287 for (i = 0; i < num_loops; i++) { 1288 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1289 1290 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1291 dst_offset, cur_size_in_bytes); 1292 1293 src_offset += cur_size_in_bytes; 1294 dst_offset += cur_size_in_bytes; 1295 byte_count -= cur_size_in_bytes; 1296 } 1297 1298 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1299 WARN_ON(job->ibs[0].length_dw > num_dw); 1300 if (direct_submit) { 1301 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, 1302 NULL, fence); 1303 job->fence = dma_fence_get(*fence); 1304 if (r) 1305 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1306 amdgpu_job_free(job); 1307 } else { 1308 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1309 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1310 if (r) 1311 goto error_free; 1312 } 1313 1314 return r; 1315 1316 error_free: 1317 amdgpu_job_free(job); 1318 return r; 1319 } 1320 1321 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1322 uint32_t src_data, 1323 struct reservation_object *resv, 1324 struct dma_fence **fence) 1325 { 1326 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1327 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1328 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1329 1330 struct drm_mm_node *mm_node; 1331 unsigned long num_pages; 1332 unsigned int num_loops, num_dw; 1333 1334 struct amdgpu_job *job; 1335 int r; 1336 1337 if (!ring->ready) { 1338 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1339 return -EINVAL; 1340 } 1341 1342 num_pages = bo->tbo.num_pages; 1343 mm_node = bo->tbo.mem.mm_node; 1344 num_loops = 0; 1345 while (num_pages) { 1346 uint32_t byte_count = mm_node->size << PAGE_SHIFT; 1347 1348 num_loops += DIV_ROUND_UP(byte_count, max_bytes); 1349 num_pages -= mm_node->size; 1350 ++mm_node; 1351 } 1352 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1353 1354 /* for IB padding */ 1355 num_dw += 64; 1356 1357 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1358 if (r) 1359 return r; 1360 1361 if (resv) { 1362 r = amdgpu_sync_resv(adev, &job->sync, resv, 1363 AMDGPU_FENCE_OWNER_UNDEFINED); 1364 if (r) { 1365 DRM_ERROR("sync failed (%d).\n", r); 1366 goto error_free; 1367 } 1368 } 1369 1370 num_pages = bo->tbo.num_pages; 1371 mm_node = bo->tbo.mem.mm_node; 1372 1373 while (num_pages) { 1374 uint32_t byte_count = mm_node->size << PAGE_SHIFT; 1375 uint64_t dst_addr; 1376 1377 r = amdgpu_mm_node_addr(&bo->tbo, mm_node, 1378 &bo->tbo.mem, &dst_addr); 1379 if (r) 1380 return r; 1381 1382 while (byte_count) { 1383 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1384 1385 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 1386 dst_addr, cur_size_in_bytes); 1387 1388 dst_addr += cur_size_in_bytes; 1389 byte_count -= cur_size_in_bytes; 1390 } 1391 1392 num_pages -= mm_node->size; 1393 ++mm_node; 1394 } 1395 1396 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1397 WARN_ON(job->ibs[0].length_dw > num_dw); 1398 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1399 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1400 if (r) 1401 goto error_free; 1402 1403 return 0; 1404 1405 error_free: 1406 amdgpu_job_free(job); 1407 return r; 1408 } 1409 1410 #if defined(CONFIG_DEBUG_FS) 1411 1412 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 1413 { 1414 struct drm_info_node *node = (struct drm_info_node *)m->private; 1415 unsigned ttm_pl = *(int *)node->info_ent->data; 1416 struct drm_device *dev = node->minor->dev; 1417 struct amdgpu_device *adev = dev->dev_private; 1418 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; 1419 struct ttm_bo_global *glob = adev->mman.bdev.glob; 1420 struct drm_printer p = drm_seq_file_printer(m); 1421 1422 spin_lock(&glob->lru_lock); 1423 drm_mm_print(mm, &p); 1424 spin_unlock(&glob->lru_lock); 1425 if (ttm_pl == TTM_PL_VRAM) 1426 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", 1427 adev->mman.bdev.man[ttm_pl].size, 1428 (u64)atomic64_read(&adev->vram_usage) >> 20, 1429 (u64)atomic64_read(&adev->vram_vis_usage) >> 20); 1430 return 0; 1431 } 1432 1433 static int ttm_pl_vram = TTM_PL_VRAM; 1434 static int ttm_pl_tt = TTM_PL_TT; 1435 1436 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 1437 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, 1438 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, 1439 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 1440 #ifdef CONFIG_SWIOTLB 1441 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 1442 #endif 1443 }; 1444 1445 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 1446 size_t size, loff_t *pos) 1447 { 1448 struct amdgpu_device *adev = file_inode(f)->i_private; 1449 ssize_t result = 0; 1450 int r; 1451 1452 if (size & 0x3 || *pos & 0x3) 1453 return -EINVAL; 1454 1455 while (size) { 1456 unsigned long flags; 1457 uint32_t value; 1458 1459 if (*pos >= adev->mc.mc_vram_size) 1460 return result; 1461 1462 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1463 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 1464 WREG32(mmMM_INDEX_HI, *pos >> 31); 1465 value = RREG32(mmMM_DATA); 1466 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1467 1468 r = put_user(value, (uint32_t *)buf); 1469 if (r) 1470 return r; 1471 1472 result += 4; 1473 buf += 4; 1474 *pos += 4; 1475 size -= 4; 1476 } 1477 1478 return result; 1479 } 1480 1481 static const struct file_operations amdgpu_ttm_vram_fops = { 1482 .owner = THIS_MODULE, 1483 .read = amdgpu_ttm_vram_read, 1484 .llseek = default_llseek 1485 }; 1486 1487 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1488 1489 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 1490 size_t size, loff_t *pos) 1491 { 1492 struct amdgpu_device *adev = file_inode(f)->i_private; 1493 ssize_t result = 0; 1494 int r; 1495 1496 while (size) { 1497 loff_t p = *pos / PAGE_SIZE; 1498 unsigned off = *pos & ~PAGE_MASK; 1499 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1500 struct page *page; 1501 void *ptr; 1502 1503 if (p >= adev->gart.num_cpu_pages) 1504 return result; 1505 1506 page = adev->gart.pages[p]; 1507 if (page) { 1508 ptr = kmap(page); 1509 ptr += off; 1510 1511 r = copy_to_user(buf, ptr, cur_size); 1512 kunmap(adev->gart.pages[p]); 1513 } else 1514 r = clear_user(buf, cur_size); 1515 1516 if (r) 1517 return -EFAULT; 1518 1519 result += cur_size; 1520 buf += cur_size; 1521 *pos += cur_size; 1522 size -= cur_size; 1523 } 1524 1525 return result; 1526 } 1527 1528 static const struct file_operations amdgpu_ttm_gtt_fops = { 1529 .owner = THIS_MODULE, 1530 .read = amdgpu_ttm_gtt_read, 1531 .llseek = default_llseek 1532 }; 1533 1534 #endif 1535 1536 #endif 1537 1538 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 1539 { 1540 #if defined(CONFIG_DEBUG_FS) 1541 unsigned count; 1542 1543 struct drm_minor *minor = adev->ddev->primary; 1544 struct dentry *ent, *root = minor->debugfs_root; 1545 1546 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, 1547 adev, &amdgpu_ttm_vram_fops); 1548 if (IS_ERR(ent)) 1549 return PTR_ERR(ent); 1550 i_size_write(ent->d_inode, adev->mc.mc_vram_size); 1551 adev->mman.vram = ent; 1552 1553 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1554 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, 1555 adev, &amdgpu_ttm_gtt_fops); 1556 if (IS_ERR(ent)) 1557 return PTR_ERR(ent); 1558 i_size_write(ent->d_inode, adev->mc.gtt_size); 1559 adev->mman.gtt = ent; 1560 1561 #endif 1562 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 1563 1564 #ifdef CONFIG_SWIOTLB 1565 if (!swiotlb_nr_tbl()) 1566 --count; 1567 #endif 1568 1569 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 1570 #else 1571 1572 return 0; 1573 #endif 1574 } 1575 1576 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) 1577 { 1578 #if defined(CONFIG_DEBUG_FS) 1579 1580 debugfs_remove(adev->mman.vram); 1581 adev->mman.vram = NULL; 1582 1583 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1584 debugfs_remove(adev->mman.gtt); 1585 adev->mman.gtt = NULL; 1586 #endif 1587 1588 #endif 1589 } 1590