1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 45 #include <drm/ttm/ttm_bo_api.h> 46 #include <drm/ttm/ttm_bo_driver.h> 47 #include <drm/ttm/ttm_placement.h> 48 49 #include <drm/amdgpu_drm.h> 50 51 #include "amdgpu.h" 52 #include "amdgpu_object.h" 53 #include "amdgpu_trace.h" 54 #include "amdgpu_amdkfd.h" 55 #include "amdgpu_sdma.h" 56 #include "amdgpu_ras.h" 57 #include "amdgpu_atomfirmware.h" 58 #include "amdgpu_res_cursor.h" 59 #include "bif/bif_4_1_d.h" 60 61 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 62 63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 64 struct ttm_tt *ttm, 65 struct ttm_resource *bo_mem); 66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 67 struct ttm_tt *ttm); 68 69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 70 unsigned int type, 71 uint64_t size_in_page) 72 { 73 return ttm_range_man_init(&adev->mman.bdev, type, 74 false, size_in_page); 75 } 76 77 /** 78 * amdgpu_evict_flags - Compute placement flags 79 * 80 * @bo: The buffer object to evict 81 * @placement: Possible destination(s) for evicted BO 82 * 83 * Fill in placement data when ttm_bo_evict() is called 84 */ 85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 86 struct ttm_placement *placement) 87 { 88 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 89 struct amdgpu_bo *abo; 90 static const struct ttm_place placements = { 91 .fpfn = 0, 92 .lpfn = 0, 93 .mem_type = TTM_PL_SYSTEM, 94 .flags = 0 95 }; 96 97 /* Don't handle scatter gather BOs */ 98 if (bo->type == ttm_bo_type_sg) { 99 placement->num_placement = 0; 100 placement->num_busy_placement = 0; 101 return; 102 } 103 104 /* Object isn't an AMDGPU object so ignore */ 105 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 106 placement->placement = &placements; 107 placement->busy_placement = &placements; 108 placement->num_placement = 1; 109 placement->num_busy_placement = 1; 110 return; 111 } 112 113 abo = ttm_to_amdgpu_bo(bo); 114 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 115 struct dma_fence *fence; 116 struct dma_resv *resv = &bo->base._resv; 117 118 rcu_read_lock(); 119 fence = rcu_dereference(resv->fence_excl); 120 if (fence && !fence->ops->signaled) 121 dma_fence_enable_sw_signaling(fence); 122 123 placement->num_placement = 0; 124 placement->num_busy_placement = 0; 125 rcu_read_unlock(); 126 return; 127 } 128 switch (bo->mem.mem_type) { 129 case AMDGPU_PL_GDS: 130 case AMDGPU_PL_GWS: 131 case AMDGPU_PL_OA: 132 placement->num_placement = 0; 133 placement->num_busy_placement = 0; 134 return; 135 136 case TTM_PL_VRAM: 137 if (!adev->mman.buffer_funcs_enabled) { 138 /* Move to system memory */ 139 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 140 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 141 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 142 amdgpu_bo_in_cpu_visible_vram(abo)) { 143 144 /* Try evicting to the CPU inaccessible part of VRAM 145 * first, but only set GTT as busy placement, so this 146 * BO will be evicted to GTT rather than causing other 147 * BOs to be evicted from VRAM 148 */ 149 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 150 AMDGPU_GEM_DOMAIN_GTT); 151 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 152 abo->placements[0].lpfn = 0; 153 abo->placement.busy_placement = &abo->placements[1]; 154 abo->placement.num_busy_placement = 1; 155 } else { 156 /* Move to GTT memory */ 157 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 158 } 159 break; 160 case TTM_PL_TT: 161 default: 162 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 163 break; 164 } 165 *placement = abo->placement; 166 } 167 168 /** 169 * amdgpu_verify_access - Verify access for a mmap call 170 * 171 * @bo: The buffer object to map 172 * @filp: The file pointer from the process performing the mmap 173 * 174 * This is called by ttm_bo_mmap() to verify whether a process 175 * has the right to mmap a BO to their process space. 176 */ 177 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 178 { 179 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 180 181 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 182 return -EPERM; 183 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 184 filp->private_data); 185 } 186 187 /** 188 * amdgpu_ttm_map_buffer - Map memory into the GART windows 189 * @bo: buffer object to map 190 * @mem: memory object to map 191 * @mm_cur: range to map 192 * @num_pages: number of pages to map 193 * @window: which GART window to use 194 * @ring: DMA ring to use for the copy 195 * @tmz: if we should setup a TMZ enabled mapping 196 * @addr: resulting address inside the MC address space 197 * 198 * Setup one of the GART windows to access a specific piece of memory or return 199 * the physical address for local memory. 200 */ 201 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 202 struct ttm_resource *mem, 203 struct amdgpu_res_cursor *mm_cur, 204 unsigned num_pages, unsigned window, 205 struct amdgpu_ring *ring, bool tmz, 206 uint64_t *addr) 207 { 208 struct amdgpu_device *adev = ring->adev; 209 struct amdgpu_job *job; 210 unsigned num_dw, num_bytes; 211 struct dma_fence *fence; 212 uint64_t src_addr, dst_addr; 213 void *cpu_addr; 214 uint64_t flags; 215 unsigned int i; 216 int r; 217 218 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 219 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 220 221 /* Map only what can't be accessed directly */ 222 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 223 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 224 mm_cur->start; 225 return 0; 226 } 227 228 *addr = adev->gmc.gart_start; 229 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 230 AMDGPU_GPU_PAGE_SIZE; 231 *addr += mm_cur->start & ~PAGE_MASK; 232 233 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 234 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 235 236 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 237 AMDGPU_IB_POOL_DELAYED, &job); 238 if (r) 239 return r; 240 241 src_addr = num_dw * 4; 242 src_addr += job->ibs[0].gpu_addr; 243 244 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 245 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 246 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 247 dst_addr, num_bytes, false); 248 249 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 250 WARN_ON(job->ibs[0].length_dw > num_dw); 251 252 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 253 if (tmz) 254 flags |= AMDGPU_PTE_TMZ; 255 256 cpu_addr = &job->ibs[0].ptr[num_dw]; 257 258 if (mem->mem_type == TTM_PL_TT) { 259 dma_addr_t *dma_addr; 260 261 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 262 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 263 cpu_addr); 264 if (r) 265 goto error_free; 266 } else { 267 dma_addr_t dma_address; 268 269 dma_address = mm_cur->start; 270 dma_address += adev->vm_manager.vram_base_offset; 271 272 for (i = 0; i < num_pages; ++i) { 273 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 274 &dma_address, flags, cpu_addr); 275 if (r) 276 goto error_free; 277 278 dma_address += PAGE_SIZE; 279 } 280 } 281 282 r = amdgpu_job_submit(job, &adev->mman.entity, 283 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 284 if (r) 285 goto error_free; 286 287 dma_fence_put(fence); 288 289 return r; 290 291 error_free: 292 amdgpu_job_free(job); 293 return r; 294 } 295 296 /** 297 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 298 * @adev: amdgpu device 299 * @src: buffer/address where to read from 300 * @dst: buffer/address where to write to 301 * @size: number of bytes to copy 302 * @tmz: if a secure copy should be used 303 * @resv: resv object to sync to 304 * @f: Returns the last fence if multiple jobs are submitted. 305 * 306 * The function copies @size bytes from {src->mem + src->offset} to 307 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 308 * move and different for a BO to BO copy. 309 * 310 */ 311 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 312 const struct amdgpu_copy_mem *src, 313 const struct amdgpu_copy_mem *dst, 314 uint64_t size, bool tmz, 315 struct dma_resv *resv, 316 struct dma_fence **f) 317 { 318 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 319 AMDGPU_GPU_PAGE_SIZE); 320 321 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 322 struct amdgpu_res_cursor src_mm, dst_mm; 323 struct dma_fence *fence = NULL; 324 int r = 0; 325 326 if (!adev->mman.buffer_funcs_enabled) { 327 DRM_ERROR("Trying to move memory with ring turned off.\n"); 328 return -EINVAL; 329 } 330 331 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 332 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 333 334 mutex_lock(&adev->mman.gtt_window_lock); 335 while (src_mm.remaining) { 336 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 337 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 338 struct dma_fence *next; 339 uint32_t cur_size; 340 uint64_t from, to; 341 342 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 343 * begins at an offset, then adjust the size accordingly 344 */ 345 cur_size = max(src_page_offset, dst_page_offset); 346 cur_size = min(min3(src_mm.size, dst_mm.size, size), 347 (uint64_t)(GTT_MAX_BYTES - cur_size)); 348 349 /* Map src to window 0 and dst to window 1. */ 350 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 351 PFN_UP(cur_size + src_page_offset), 352 0, ring, tmz, &from); 353 if (r) 354 goto error; 355 356 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 357 PFN_UP(cur_size + dst_page_offset), 358 1, ring, tmz, &to); 359 if (r) 360 goto error; 361 362 r = amdgpu_copy_buffer(ring, from, to, cur_size, 363 resv, &next, false, true, tmz); 364 if (r) 365 goto error; 366 367 dma_fence_put(fence); 368 fence = next; 369 370 amdgpu_res_next(&src_mm, cur_size); 371 amdgpu_res_next(&dst_mm, cur_size); 372 } 373 error: 374 mutex_unlock(&adev->mman.gtt_window_lock); 375 if (f) 376 *f = dma_fence_get(fence); 377 dma_fence_put(fence); 378 return r; 379 } 380 381 /* 382 * amdgpu_move_blit - Copy an entire buffer to another buffer 383 * 384 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 385 * help move buffers to and from VRAM. 386 */ 387 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 388 bool evict, 389 struct ttm_resource *new_mem, 390 struct ttm_resource *old_mem) 391 { 392 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 393 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 394 struct amdgpu_copy_mem src, dst; 395 struct dma_fence *fence = NULL; 396 int r; 397 398 src.bo = bo; 399 dst.bo = bo; 400 src.mem = old_mem; 401 dst.mem = new_mem; 402 src.offset = 0; 403 dst.offset = 0; 404 405 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 406 new_mem->num_pages << PAGE_SHIFT, 407 amdgpu_bo_encrypted(abo), 408 bo->base.resv, &fence); 409 if (r) 410 goto error; 411 412 /* clear the space being freed */ 413 if (old_mem->mem_type == TTM_PL_VRAM && 414 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 415 struct dma_fence *wipe_fence = NULL; 416 417 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 418 NULL, &wipe_fence); 419 if (r) { 420 goto error; 421 } else if (wipe_fence) { 422 dma_fence_put(fence); 423 fence = wipe_fence; 424 } 425 } 426 427 /* Always block for VM page tables before committing the new location */ 428 if (bo->type == ttm_bo_type_kernel) 429 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 430 else 431 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 432 dma_fence_put(fence); 433 return r; 434 435 error: 436 if (fence) 437 dma_fence_wait(fence, false); 438 dma_fence_put(fence); 439 return r; 440 } 441 442 /* 443 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 444 * 445 * Called by amdgpu_bo_move() 446 */ 447 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 448 struct ttm_resource *mem) 449 { 450 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 451 struct amdgpu_res_cursor cursor; 452 453 if (mem->mem_type == TTM_PL_SYSTEM || 454 mem->mem_type == TTM_PL_TT) 455 return true; 456 if (mem->mem_type != TTM_PL_VRAM) 457 return false; 458 459 amdgpu_res_first(mem, 0, mem_size, &cursor); 460 461 /* ttm_resource_ioremap only supports contiguous memory */ 462 if (cursor.size != mem_size) 463 return false; 464 465 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 466 } 467 468 /* 469 * amdgpu_bo_move - Move a buffer object to a new memory location 470 * 471 * Called by ttm_bo_handle_move_mem() 472 */ 473 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 474 struct ttm_operation_ctx *ctx, 475 struct ttm_resource *new_mem, 476 struct ttm_place *hop) 477 { 478 struct amdgpu_device *adev; 479 struct amdgpu_bo *abo; 480 struct ttm_resource *old_mem = &bo->mem; 481 int r; 482 483 if (new_mem->mem_type == TTM_PL_TT) { 484 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 485 if (r) 486 return r; 487 } 488 489 /* Can't move a pinned BO */ 490 abo = ttm_to_amdgpu_bo(bo); 491 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 492 return -EINVAL; 493 494 adev = amdgpu_ttm_adev(bo->bdev); 495 496 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 497 ttm_bo_move_null(bo, new_mem); 498 goto out; 499 } 500 if (old_mem->mem_type == TTM_PL_SYSTEM && 501 new_mem->mem_type == TTM_PL_TT) { 502 ttm_bo_move_null(bo, new_mem); 503 goto out; 504 } 505 if (old_mem->mem_type == TTM_PL_TT && 506 new_mem->mem_type == TTM_PL_SYSTEM) { 507 r = ttm_bo_wait_ctx(bo, ctx); 508 if (r) 509 return r; 510 511 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 512 ttm_resource_free(bo, &bo->mem); 513 ttm_bo_assign_mem(bo, new_mem); 514 goto out; 515 } 516 517 if (old_mem->mem_type == AMDGPU_PL_GDS || 518 old_mem->mem_type == AMDGPU_PL_GWS || 519 old_mem->mem_type == AMDGPU_PL_OA || 520 new_mem->mem_type == AMDGPU_PL_GDS || 521 new_mem->mem_type == AMDGPU_PL_GWS || 522 new_mem->mem_type == AMDGPU_PL_OA) { 523 /* Nothing to save here */ 524 ttm_bo_move_null(bo, new_mem); 525 goto out; 526 } 527 528 if (adev->mman.buffer_funcs_enabled) { 529 if (((old_mem->mem_type == TTM_PL_SYSTEM && 530 new_mem->mem_type == TTM_PL_VRAM) || 531 (old_mem->mem_type == TTM_PL_VRAM && 532 new_mem->mem_type == TTM_PL_SYSTEM))) { 533 hop->fpfn = 0; 534 hop->lpfn = 0; 535 hop->mem_type = TTM_PL_TT; 536 hop->flags = 0; 537 return -EMULTIHOP; 538 } 539 540 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 541 } else { 542 r = -ENODEV; 543 } 544 545 if (r) { 546 /* Check that all memory is CPU accessible */ 547 if (!amdgpu_mem_visible(adev, old_mem) || 548 !amdgpu_mem_visible(adev, new_mem)) { 549 pr_err("Move buffer fallback to memcpy unavailable\n"); 550 return r; 551 } 552 553 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 554 if (r) 555 return r; 556 } 557 558 if (bo->type == ttm_bo_type_device && 559 new_mem->mem_type == TTM_PL_VRAM && 560 old_mem->mem_type != TTM_PL_VRAM) { 561 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 562 * accesses the BO after it's moved. 563 */ 564 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 565 } 566 567 out: 568 /* update statistics */ 569 atomic64_add(bo->base.size, &adev->num_bytes_moved); 570 amdgpu_bo_move_notify(bo, evict, new_mem); 571 return 0; 572 } 573 574 /* 575 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 576 * 577 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 578 */ 579 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 580 struct ttm_resource *mem) 581 { 582 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 583 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 584 585 switch (mem->mem_type) { 586 case TTM_PL_SYSTEM: 587 /* system memory */ 588 return 0; 589 case TTM_PL_TT: 590 break; 591 case TTM_PL_VRAM: 592 mem->bus.offset = mem->start << PAGE_SHIFT; 593 /* check if it's visible */ 594 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 595 return -EINVAL; 596 597 if (adev->mman.aper_base_kaddr && 598 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 599 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 600 mem->bus.offset; 601 602 mem->bus.offset += adev->gmc.aper_base; 603 mem->bus.is_iomem = true; 604 if (adev->gmc.xgmi.connected_to_cpu) 605 mem->bus.caching = ttm_cached; 606 else 607 mem->bus.caching = ttm_write_combined; 608 break; 609 default: 610 return -EINVAL; 611 } 612 return 0; 613 } 614 615 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 616 unsigned long page_offset) 617 { 618 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 619 struct amdgpu_res_cursor cursor; 620 621 amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor); 622 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 623 } 624 625 /** 626 * amdgpu_ttm_domain_start - Returns GPU start address 627 * @adev: amdgpu device object 628 * @type: type of the memory 629 * 630 * Returns: 631 * GPU start address of a memory domain 632 */ 633 634 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 635 { 636 switch (type) { 637 case TTM_PL_TT: 638 return adev->gmc.gart_start; 639 case TTM_PL_VRAM: 640 return adev->gmc.vram_start; 641 } 642 643 return 0; 644 } 645 646 /* 647 * TTM backend functions. 648 */ 649 struct amdgpu_ttm_tt { 650 struct ttm_tt ttm; 651 struct drm_gem_object *gobj; 652 u64 offset; 653 uint64_t userptr; 654 struct task_struct *usertask; 655 uint32_t userflags; 656 bool bound; 657 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 658 struct hmm_range *range; 659 #endif 660 }; 661 662 #ifdef CONFIG_DRM_AMDGPU_USERPTR 663 /* 664 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 665 * memory and start HMM tracking CPU page table update 666 * 667 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 668 * once afterwards to stop HMM tracking 669 */ 670 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 671 { 672 struct ttm_tt *ttm = bo->tbo.ttm; 673 struct amdgpu_ttm_tt *gtt = (void *)ttm; 674 unsigned long start = gtt->userptr; 675 struct vm_area_struct *vma; 676 struct mm_struct *mm; 677 bool readonly; 678 int r = 0; 679 680 mm = bo->notifier.mm; 681 if (unlikely(!mm)) { 682 DRM_DEBUG_DRIVER("BO is not registered?\n"); 683 return -EFAULT; 684 } 685 686 /* Another get_user_pages is running at the same time?? */ 687 if (WARN_ON(gtt->range)) 688 return -EFAULT; 689 690 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 691 return -ESRCH; 692 693 mmap_read_lock(mm); 694 vma = find_vma(mm, start); 695 mmap_read_unlock(mm); 696 if (unlikely(!vma || start < vma->vm_start)) { 697 r = -EFAULT; 698 goto out_putmm; 699 } 700 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 701 vma->vm_file)) { 702 r = -EPERM; 703 goto out_putmm; 704 } 705 706 readonly = amdgpu_ttm_tt_is_readonly(ttm); 707 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 708 ttm->num_pages, >t->range, readonly, 709 false); 710 out_putmm: 711 mmput(mm); 712 713 return r; 714 } 715 716 /* 717 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 718 * Check if the pages backing this ttm range have been invalidated 719 * 720 * Returns: true if pages are still valid 721 */ 722 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 723 { 724 struct amdgpu_ttm_tt *gtt = (void *)ttm; 725 bool r = false; 726 727 if (!gtt || !gtt->userptr) 728 return false; 729 730 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 731 gtt->userptr, ttm->num_pages); 732 733 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 734 "No user pages to check\n"); 735 736 if (gtt->range) { 737 /* 738 * FIXME: Must always hold notifier_lock for this, and must 739 * not ignore the return code. 740 */ 741 r = amdgpu_hmm_range_get_pages_done(gtt->range); 742 gtt->range = NULL; 743 } 744 745 return !r; 746 } 747 #endif 748 749 /* 750 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 751 * 752 * Called by amdgpu_cs_list_validate(). This creates the page list 753 * that backs user memory and will ultimately be mapped into the device 754 * address space. 755 */ 756 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 757 { 758 unsigned long i; 759 760 for (i = 0; i < ttm->num_pages; ++i) 761 ttm->pages[i] = pages ? pages[i] : NULL; 762 } 763 764 /* 765 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 766 * 767 * Called by amdgpu_ttm_backend_bind() 768 **/ 769 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 770 struct ttm_tt *ttm) 771 { 772 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 773 struct amdgpu_ttm_tt *gtt = (void *)ttm; 774 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 775 enum dma_data_direction direction = write ? 776 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 777 int r; 778 779 /* Allocate an SG array and squash pages into it */ 780 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 781 (u64)ttm->num_pages << PAGE_SHIFT, 782 GFP_KERNEL); 783 if (r) 784 goto release_sg; 785 786 /* Map SG to device */ 787 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 788 if (r) 789 goto release_sg; 790 791 /* convert SG to linear array of pages and dma addresses */ 792 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 793 ttm->num_pages); 794 795 return 0; 796 797 release_sg: 798 kfree(ttm->sg); 799 ttm->sg = NULL; 800 return r; 801 } 802 803 /* 804 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 805 */ 806 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 807 struct ttm_tt *ttm) 808 { 809 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 810 struct amdgpu_ttm_tt *gtt = (void *)ttm; 811 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 812 enum dma_data_direction direction = write ? 813 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 814 815 /* double check that we don't free the table twice */ 816 if (!ttm->sg || !ttm->sg->sgl) 817 return; 818 819 /* unmap the pages mapped to the device */ 820 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 821 sg_free_table(ttm->sg); 822 823 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 824 if (gtt->range) { 825 unsigned long i; 826 827 for (i = 0; i < ttm->num_pages; i++) { 828 if (ttm->pages[i] != 829 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 830 break; 831 } 832 833 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 834 } 835 #endif 836 } 837 838 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 839 struct ttm_buffer_object *tbo, 840 uint64_t flags) 841 { 842 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 843 struct ttm_tt *ttm = tbo->ttm; 844 struct amdgpu_ttm_tt *gtt = (void *)ttm; 845 int r; 846 847 if (amdgpu_bo_encrypted(abo)) 848 flags |= AMDGPU_PTE_TMZ; 849 850 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 851 uint64_t page_idx = 1; 852 853 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 854 ttm->pages, gtt->ttm.dma_address, flags); 855 if (r) 856 goto gart_bind_fail; 857 858 /* The memory type of the first page defaults to UC. Now 859 * modify the memory type to NC from the second page of 860 * the BO onward. 861 */ 862 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 863 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 864 865 r = amdgpu_gart_bind(adev, 866 gtt->offset + (page_idx << PAGE_SHIFT), 867 ttm->num_pages - page_idx, 868 &ttm->pages[page_idx], 869 &(gtt->ttm.dma_address[page_idx]), flags); 870 } else { 871 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 872 ttm->pages, gtt->ttm.dma_address, flags); 873 } 874 875 gart_bind_fail: 876 if (r) 877 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 878 ttm->num_pages, gtt->offset); 879 880 return r; 881 } 882 883 /* 884 * amdgpu_ttm_backend_bind - Bind GTT memory 885 * 886 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 887 * This handles binding GTT memory to the device address space. 888 */ 889 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 890 struct ttm_tt *ttm, 891 struct ttm_resource *bo_mem) 892 { 893 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 894 struct amdgpu_ttm_tt *gtt = (void*)ttm; 895 uint64_t flags; 896 int r = 0; 897 898 if (!bo_mem) 899 return -EINVAL; 900 901 if (gtt->bound) 902 return 0; 903 904 if (gtt->userptr) { 905 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 906 if (r) { 907 DRM_ERROR("failed to pin userptr\n"); 908 return r; 909 } 910 } 911 if (!ttm->num_pages) { 912 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 913 ttm->num_pages, bo_mem, ttm); 914 } 915 916 if (bo_mem->mem_type == AMDGPU_PL_GDS || 917 bo_mem->mem_type == AMDGPU_PL_GWS || 918 bo_mem->mem_type == AMDGPU_PL_OA) 919 return -EINVAL; 920 921 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 922 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 923 return 0; 924 } 925 926 /* compute PTE flags relevant to this BO memory */ 927 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 928 929 /* bind pages into GART page tables */ 930 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 931 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 932 ttm->pages, gtt->ttm.dma_address, flags); 933 934 if (r) 935 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 936 ttm->num_pages, gtt->offset); 937 gtt->bound = true; 938 return r; 939 } 940 941 /* 942 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 943 * through AGP or GART aperture. 944 * 945 * If bo is accessible through AGP aperture, then use AGP aperture 946 * to access bo; otherwise allocate logical space in GART aperture 947 * and map bo to GART aperture. 948 */ 949 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 950 { 951 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 952 struct ttm_operation_ctx ctx = { false, false }; 953 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 954 struct ttm_resource tmp; 955 struct ttm_placement placement; 956 struct ttm_place placements; 957 uint64_t addr, flags; 958 int r; 959 960 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 961 return 0; 962 963 addr = amdgpu_gmc_agp_addr(bo); 964 if (addr != AMDGPU_BO_INVALID_OFFSET) { 965 bo->mem.start = addr >> PAGE_SHIFT; 966 } else { 967 968 /* allocate GART space */ 969 tmp = bo->mem; 970 tmp.mm_node = NULL; 971 placement.num_placement = 1; 972 placement.placement = &placements; 973 placement.num_busy_placement = 1; 974 placement.busy_placement = &placements; 975 placements.fpfn = 0; 976 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 977 placements.mem_type = TTM_PL_TT; 978 placements.flags = bo->mem.placement; 979 980 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 981 if (unlikely(r)) 982 return r; 983 984 /* compute PTE flags for this buffer object */ 985 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 986 987 /* Bind pages */ 988 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 989 r = amdgpu_ttm_gart_bind(adev, bo, flags); 990 if (unlikely(r)) { 991 ttm_resource_free(bo, &tmp); 992 return r; 993 } 994 995 ttm_resource_free(bo, &bo->mem); 996 bo->mem = tmp; 997 } 998 999 return 0; 1000 } 1001 1002 /* 1003 * amdgpu_ttm_recover_gart - Rebind GTT pages 1004 * 1005 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1006 * rebind GTT pages during a GPU reset. 1007 */ 1008 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1009 { 1010 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1011 uint64_t flags; 1012 int r; 1013 1014 if (!tbo->ttm) 1015 return 0; 1016 1017 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1018 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1019 1020 return r; 1021 } 1022 1023 /* 1024 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1025 * 1026 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1027 * ttm_tt_destroy(). 1028 */ 1029 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1030 struct ttm_tt *ttm) 1031 { 1032 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1033 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1034 int r; 1035 1036 /* if the pages have userptr pinning then clear that first */ 1037 if (gtt->userptr) 1038 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1039 1040 if (!gtt->bound) 1041 return; 1042 1043 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1044 return; 1045 1046 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1047 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1048 if (r) 1049 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1050 gtt->ttm.num_pages, gtt->offset); 1051 gtt->bound = false; 1052 } 1053 1054 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1055 struct ttm_tt *ttm) 1056 { 1057 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1058 1059 amdgpu_ttm_backend_unbind(bdev, ttm); 1060 ttm_tt_destroy_common(bdev, ttm); 1061 if (gtt->usertask) 1062 put_task_struct(gtt->usertask); 1063 1064 ttm_tt_fini(>t->ttm); 1065 kfree(gtt); 1066 } 1067 1068 /** 1069 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1070 * 1071 * @bo: The buffer object to create a GTT ttm_tt object around 1072 * @page_flags: Page flags to be added to the ttm_tt object 1073 * 1074 * Called by ttm_tt_create(). 1075 */ 1076 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1077 uint32_t page_flags) 1078 { 1079 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1080 struct amdgpu_ttm_tt *gtt; 1081 enum ttm_caching caching; 1082 1083 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1084 if (gtt == NULL) { 1085 return NULL; 1086 } 1087 gtt->gobj = &bo->base; 1088 1089 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1090 caching = ttm_write_combined; 1091 else 1092 caching = ttm_cached; 1093 1094 /* allocate space for the uninitialized page entries */ 1095 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1096 kfree(gtt); 1097 return NULL; 1098 } 1099 return >t->ttm; 1100 } 1101 1102 /* 1103 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1104 * 1105 * Map the pages of a ttm_tt object to an address space visible 1106 * to the underlying device. 1107 */ 1108 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1109 struct ttm_tt *ttm, 1110 struct ttm_operation_ctx *ctx) 1111 { 1112 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1113 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1114 1115 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1116 if (gtt && gtt->userptr) { 1117 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1118 if (!ttm->sg) 1119 return -ENOMEM; 1120 1121 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1122 return 0; 1123 } 1124 1125 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1126 if (!ttm->sg) { 1127 struct dma_buf_attachment *attach; 1128 struct sg_table *sgt; 1129 1130 attach = gtt->gobj->import_attach; 1131 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1132 if (IS_ERR(sgt)) 1133 return PTR_ERR(sgt); 1134 1135 ttm->sg = sgt; 1136 } 1137 1138 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 1139 ttm->num_pages); 1140 return 0; 1141 } 1142 1143 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1144 } 1145 1146 /* 1147 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1148 * 1149 * Unmaps pages of a ttm_tt object from the device address space and 1150 * unpopulates the page array backing it. 1151 */ 1152 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1153 struct ttm_tt *ttm) 1154 { 1155 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1156 struct amdgpu_device *adev; 1157 1158 if (gtt && gtt->userptr) { 1159 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1160 kfree(ttm->sg); 1161 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1162 return; 1163 } 1164 1165 if (ttm->sg && gtt->gobj->import_attach) { 1166 struct dma_buf_attachment *attach; 1167 1168 attach = gtt->gobj->import_attach; 1169 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1170 ttm->sg = NULL; 1171 return; 1172 } 1173 1174 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1175 return; 1176 1177 adev = amdgpu_ttm_adev(bdev); 1178 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1179 } 1180 1181 /** 1182 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1183 * task 1184 * 1185 * @bo: The ttm_buffer_object to bind this userptr to 1186 * @addr: The address in the current tasks VM space to use 1187 * @flags: Requirements of userptr object. 1188 * 1189 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1190 * to current task 1191 */ 1192 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1193 uint64_t addr, uint32_t flags) 1194 { 1195 struct amdgpu_ttm_tt *gtt; 1196 1197 if (!bo->ttm) { 1198 /* TODO: We want a separate TTM object type for userptrs */ 1199 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1200 if (bo->ttm == NULL) 1201 return -ENOMEM; 1202 } 1203 1204 gtt = (void *)bo->ttm; 1205 gtt->userptr = addr; 1206 gtt->userflags = flags; 1207 1208 if (gtt->usertask) 1209 put_task_struct(gtt->usertask); 1210 gtt->usertask = current->group_leader; 1211 get_task_struct(gtt->usertask); 1212 1213 return 0; 1214 } 1215 1216 /* 1217 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1218 */ 1219 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1220 { 1221 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1222 1223 if (gtt == NULL) 1224 return NULL; 1225 1226 if (gtt->usertask == NULL) 1227 return NULL; 1228 1229 return gtt->usertask->mm; 1230 } 1231 1232 /* 1233 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1234 * address range for the current task. 1235 * 1236 */ 1237 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1238 unsigned long end) 1239 { 1240 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1241 unsigned long size; 1242 1243 if (gtt == NULL || !gtt->userptr) 1244 return false; 1245 1246 /* Return false if no part of the ttm_tt object lies within 1247 * the range 1248 */ 1249 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1250 if (gtt->userptr > end || gtt->userptr + size <= start) 1251 return false; 1252 1253 return true; 1254 } 1255 1256 /* 1257 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1258 */ 1259 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1260 { 1261 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1262 1263 if (gtt == NULL || !gtt->userptr) 1264 return false; 1265 1266 return true; 1267 } 1268 1269 /* 1270 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1271 */ 1272 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1273 { 1274 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1275 1276 if (gtt == NULL) 1277 return false; 1278 1279 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1280 } 1281 1282 /** 1283 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1284 * 1285 * @ttm: The ttm_tt object to compute the flags for 1286 * @mem: The memory registry backing this ttm_tt object 1287 * 1288 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1289 */ 1290 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1291 { 1292 uint64_t flags = 0; 1293 1294 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1295 flags |= AMDGPU_PTE_VALID; 1296 1297 if (mem && mem->mem_type == TTM_PL_TT) { 1298 flags |= AMDGPU_PTE_SYSTEM; 1299 1300 if (ttm->caching == ttm_cached) 1301 flags |= AMDGPU_PTE_SNOOPED; 1302 } 1303 1304 if (mem && mem->mem_type == TTM_PL_VRAM && 1305 mem->bus.caching == ttm_cached) 1306 flags |= AMDGPU_PTE_SNOOPED; 1307 1308 return flags; 1309 } 1310 1311 /** 1312 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1313 * 1314 * @adev: amdgpu_device pointer 1315 * @ttm: The ttm_tt object to compute the flags for 1316 * @mem: The memory registry backing this ttm_tt object 1317 * 1318 * Figure out the flags to use for a VM PTE (Page Table Entry). 1319 */ 1320 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1321 struct ttm_resource *mem) 1322 { 1323 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1324 1325 flags |= adev->gart.gart_pte_flags; 1326 flags |= AMDGPU_PTE_READABLE; 1327 1328 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1329 flags |= AMDGPU_PTE_WRITEABLE; 1330 1331 return flags; 1332 } 1333 1334 /* 1335 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1336 * object. 1337 * 1338 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1339 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1340 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1341 * used to clean out a memory space. 1342 */ 1343 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1344 const struct ttm_place *place) 1345 { 1346 unsigned long num_pages = bo->mem.num_pages; 1347 struct amdgpu_res_cursor cursor; 1348 struct dma_resv_list *flist; 1349 struct dma_fence *f; 1350 int i; 1351 1352 if (bo->type == ttm_bo_type_kernel && 1353 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1354 return false; 1355 1356 /* If bo is a KFD BO, check if the bo belongs to the current process. 1357 * If true, then return false as any KFD process needs all its BOs to 1358 * be resident to run successfully 1359 */ 1360 flist = dma_resv_get_list(bo->base.resv); 1361 if (flist) { 1362 for (i = 0; i < flist->shared_count; ++i) { 1363 f = rcu_dereference_protected(flist->shared[i], 1364 dma_resv_held(bo->base.resv)); 1365 if (amdkfd_fence_check_mm(f, current->mm)) 1366 return false; 1367 } 1368 } 1369 1370 switch (bo->mem.mem_type) { 1371 case TTM_PL_TT: 1372 if (amdgpu_bo_is_amdgpu_bo(bo) && 1373 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1374 return false; 1375 return true; 1376 1377 case TTM_PL_VRAM: 1378 /* Check each drm MM node individually */ 1379 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT, 1380 &cursor); 1381 while (cursor.remaining) { 1382 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1383 && !(place->lpfn && 1384 place->lpfn <= PFN_DOWN(cursor.start))) 1385 return true; 1386 1387 amdgpu_res_next(&cursor, cursor.size); 1388 } 1389 return false; 1390 1391 default: 1392 break; 1393 } 1394 1395 return ttm_bo_eviction_valuable(bo, place); 1396 } 1397 1398 /** 1399 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1400 * 1401 * @bo: The buffer object to read/write 1402 * @offset: Offset into buffer object 1403 * @buf: Secondary buffer to write/read from 1404 * @len: Length in bytes of access 1405 * @write: true if writing 1406 * 1407 * This is used to access VRAM that backs a buffer object via MMIO 1408 * access for debugging purposes. 1409 */ 1410 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1411 unsigned long offset, void *buf, int len, 1412 int write) 1413 { 1414 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1415 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1416 struct amdgpu_res_cursor cursor; 1417 unsigned long flags; 1418 uint32_t value = 0; 1419 int ret = 0; 1420 1421 if (bo->mem.mem_type != TTM_PL_VRAM) 1422 return -EIO; 1423 1424 amdgpu_res_first(&bo->mem, offset, len, &cursor); 1425 while (cursor.remaining) { 1426 uint64_t aligned_pos = cursor.start & ~(uint64_t)3; 1427 uint64_t bytes = 4 - (cursor.start & 3); 1428 uint32_t shift = (cursor.start & 3) * 8; 1429 uint32_t mask = 0xffffffff << shift; 1430 1431 if (cursor.size < bytes) { 1432 mask &= 0xffffffff >> (bytes - cursor.size) * 8; 1433 bytes = cursor.size; 1434 } 1435 1436 if (mask != 0xffffffff) { 1437 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1438 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1439 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1440 value = RREG32_NO_KIQ(mmMM_DATA); 1441 if (write) { 1442 value &= ~mask; 1443 value |= (*(uint32_t *)buf << shift) & mask; 1444 WREG32_NO_KIQ(mmMM_DATA, value); 1445 } 1446 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1447 if (!write) { 1448 value = (value & mask) >> shift; 1449 memcpy(buf, &value, bytes); 1450 } 1451 } else { 1452 bytes = cursor.size & ~0x3ULL; 1453 amdgpu_device_vram_access(adev, cursor.start, 1454 (uint32_t *)buf, bytes, 1455 write); 1456 } 1457 1458 ret += bytes; 1459 buf = (uint8_t *)buf + bytes; 1460 amdgpu_res_next(&cursor, bytes); 1461 } 1462 1463 return ret; 1464 } 1465 1466 static void 1467 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1468 { 1469 amdgpu_bo_move_notify(bo, false, NULL); 1470 } 1471 1472 static struct ttm_device_funcs amdgpu_bo_driver = { 1473 .ttm_tt_create = &amdgpu_ttm_tt_create, 1474 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1475 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1476 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1477 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1478 .evict_flags = &amdgpu_evict_flags, 1479 .move = &amdgpu_bo_move, 1480 .verify_access = &amdgpu_verify_access, 1481 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1482 .release_notify = &amdgpu_bo_release_notify, 1483 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1484 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1485 .access_memory = &amdgpu_ttm_access_memory, 1486 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1487 }; 1488 1489 /* 1490 * Firmware Reservation functions 1491 */ 1492 /** 1493 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1494 * 1495 * @adev: amdgpu_device pointer 1496 * 1497 * free fw reserved vram if it has been reserved. 1498 */ 1499 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1500 { 1501 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1502 NULL, &adev->mman.fw_vram_usage_va); 1503 } 1504 1505 /** 1506 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1507 * 1508 * @adev: amdgpu_device pointer 1509 * 1510 * create bo vram reservation from fw. 1511 */ 1512 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1513 { 1514 uint64_t vram_size = adev->gmc.visible_vram_size; 1515 1516 adev->mman.fw_vram_usage_va = NULL; 1517 adev->mman.fw_vram_usage_reserved_bo = NULL; 1518 1519 if (adev->mman.fw_vram_usage_size == 0 || 1520 adev->mman.fw_vram_usage_size > vram_size) 1521 return 0; 1522 1523 return amdgpu_bo_create_kernel_at(adev, 1524 adev->mman.fw_vram_usage_start_offset, 1525 adev->mman.fw_vram_usage_size, 1526 AMDGPU_GEM_DOMAIN_VRAM, 1527 &adev->mman.fw_vram_usage_reserved_bo, 1528 &adev->mman.fw_vram_usage_va); 1529 } 1530 1531 /* 1532 * Memoy training reservation functions 1533 */ 1534 1535 /** 1536 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1537 * 1538 * @adev: amdgpu_device pointer 1539 * 1540 * free memory training reserved vram if it has been reserved. 1541 */ 1542 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1543 { 1544 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1545 1546 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1547 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1548 ctx->c2p_bo = NULL; 1549 1550 return 0; 1551 } 1552 1553 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1554 { 1555 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1556 1557 memset(ctx, 0, sizeof(*ctx)); 1558 1559 ctx->c2p_train_data_offset = 1560 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1561 ctx->p2c_train_data_offset = 1562 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1563 ctx->train_data_size = 1564 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1565 1566 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1567 ctx->train_data_size, 1568 ctx->p2c_train_data_offset, 1569 ctx->c2p_train_data_offset); 1570 } 1571 1572 /* 1573 * reserve TMR memory at the top of VRAM which holds 1574 * IP Discovery data and is protected by PSP. 1575 */ 1576 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1577 { 1578 int ret; 1579 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1580 bool mem_train_support = false; 1581 1582 if (!amdgpu_sriov_vf(adev)) { 1583 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1584 mem_train_support = true; 1585 else 1586 DRM_DEBUG("memory training does not support!\n"); 1587 } 1588 1589 /* 1590 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1591 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1592 * 1593 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1594 * discovery data and G6 memory training data respectively 1595 */ 1596 adev->mman.discovery_tmr_size = 1597 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1598 if (!adev->mman.discovery_tmr_size) 1599 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1600 1601 if (mem_train_support) { 1602 /* reserve vram for mem train according to TMR location */ 1603 amdgpu_ttm_training_data_block_init(adev); 1604 ret = amdgpu_bo_create_kernel_at(adev, 1605 ctx->c2p_train_data_offset, 1606 ctx->train_data_size, 1607 AMDGPU_GEM_DOMAIN_VRAM, 1608 &ctx->c2p_bo, 1609 NULL); 1610 if (ret) { 1611 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1612 amdgpu_ttm_training_reserve_vram_fini(adev); 1613 return ret; 1614 } 1615 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1616 } 1617 1618 ret = amdgpu_bo_create_kernel_at(adev, 1619 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1620 adev->mman.discovery_tmr_size, 1621 AMDGPU_GEM_DOMAIN_VRAM, 1622 &adev->mman.discovery_memory, 1623 NULL); 1624 if (ret) { 1625 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1626 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1627 return ret; 1628 } 1629 1630 return 0; 1631 } 1632 1633 /* 1634 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1635 * gtt/vram related fields. 1636 * 1637 * This initializes all of the memory space pools that the TTM layer 1638 * will need such as the GTT space (system memory mapped to the device), 1639 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1640 * can be mapped per VMID. 1641 */ 1642 int amdgpu_ttm_init(struct amdgpu_device *adev) 1643 { 1644 uint64_t gtt_size; 1645 int r; 1646 u64 vis_vram_limit; 1647 1648 mutex_init(&adev->mman.gtt_window_lock); 1649 1650 /* No others user of address space so set it to 0 */ 1651 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1652 adev_to_drm(adev)->anon_inode->i_mapping, 1653 adev_to_drm(adev)->vma_offset_manager, 1654 adev->need_swiotlb, 1655 dma_addressing_limited(adev->dev)); 1656 if (r) { 1657 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1658 return r; 1659 } 1660 adev->mman.initialized = true; 1661 1662 /* Initialize VRAM pool with all of VRAM divided into pages */ 1663 r = amdgpu_vram_mgr_init(adev); 1664 if (r) { 1665 DRM_ERROR("Failed initializing VRAM heap.\n"); 1666 return r; 1667 } 1668 1669 /* Reduce size of CPU-visible VRAM if requested */ 1670 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1671 if (amdgpu_vis_vram_limit > 0 && 1672 vis_vram_limit <= adev->gmc.visible_vram_size) 1673 adev->gmc.visible_vram_size = vis_vram_limit; 1674 1675 /* Change the size here instead of the init above so only lpfn is affected */ 1676 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1677 #ifdef CONFIG_64BIT 1678 #ifdef CONFIG_X86 1679 if (adev->gmc.xgmi.connected_to_cpu) 1680 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1681 adev->gmc.visible_vram_size); 1682 1683 else 1684 #endif 1685 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1686 adev->gmc.visible_vram_size); 1687 #endif 1688 1689 /* 1690 *The reserved vram for firmware must be pinned to the specified 1691 *place on the VRAM, so reserve it early. 1692 */ 1693 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1694 if (r) { 1695 return r; 1696 } 1697 1698 /* 1699 * only NAVI10 and onwards ASIC support for IP discovery. 1700 * If IP discovery enabled, a block of memory should be 1701 * reserved for IP discovey. 1702 */ 1703 if (adev->mman.discovery_bin) { 1704 r = amdgpu_ttm_reserve_tmr(adev); 1705 if (r) 1706 return r; 1707 } 1708 1709 /* allocate memory as required for VGA 1710 * This is used for VGA emulation and pre-OS scanout buffers to 1711 * avoid display artifacts while transitioning between pre-OS 1712 * and driver. */ 1713 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1714 AMDGPU_GEM_DOMAIN_VRAM, 1715 &adev->mman.stolen_vga_memory, 1716 NULL); 1717 if (r) 1718 return r; 1719 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1720 adev->mman.stolen_extended_size, 1721 AMDGPU_GEM_DOMAIN_VRAM, 1722 &adev->mman.stolen_extended_memory, 1723 NULL); 1724 if (r) 1725 return r; 1726 1727 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1728 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1729 1730 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1731 * or whatever the user passed on module init */ 1732 if (amdgpu_gtt_size == -1) { 1733 struct sysinfo si; 1734 1735 si_meminfo(&si); 1736 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1737 adev->gmc.mc_vram_size), 1738 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1739 } 1740 else 1741 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1742 1743 /* Initialize GTT memory pool */ 1744 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1745 if (r) { 1746 DRM_ERROR("Failed initializing GTT heap.\n"); 1747 return r; 1748 } 1749 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1750 (unsigned)(gtt_size / (1024 * 1024))); 1751 1752 /* Initialize various on-chip memory pools */ 1753 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1754 if (r) { 1755 DRM_ERROR("Failed initializing GDS heap.\n"); 1756 return r; 1757 } 1758 1759 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1760 if (r) { 1761 DRM_ERROR("Failed initializing gws heap.\n"); 1762 return r; 1763 } 1764 1765 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1766 if (r) { 1767 DRM_ERROR("Failed initializing oa heap.\n"); 1768 return r; 1769 } 1770 1771 return 0; 1772 } 1773 1774 /* 1775 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1776 */ 1777 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1778 { 1779 if (!adev->mman.initialized) 1780 return; 1781 1782 amdgpu_ttm_training_reserve_vram_fini(adev); 1783 /* return the stolen vga memory back to VRAM */ 1784 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1785 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1786 /* return the IP Discovery TMR memory back to VRAM */ 1787 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1788 amdgpu_ttm_fw_reserve_vram_fini(adev); 1789 1790 if (adev->mman.aper_base_kaddr) 1791 iounmap(adev->mman.aper_base_kaddr); 1792 adev->mman.aper_base_kaddr = NULL; 1793 1794 amdgpu_vram_mgr_fini(adev); 1795 amdgpu_gtt_mgr_fini(adev); 1796 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1797 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1798 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1799 ttm_device_fini(&adev->mman.bdev); 1800 adev->mman.initialized = false; 1801 DRM_INFO("amdgpu: ttm finalized\n"); 1802 } 1803 1804 /** 1805 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1806 * 1807 * @adev: amdgpu_device pointer 1808 * @enable: true when we can use buffer functions. 1809 * 1810 * Enable/disable use of buffer functions during suspend/resume. This should 1811 * only be called at bootup or when userspace isn't running. 1812 */ 1813 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1814 { 1815 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1816 uint64_t size; 1817 int r; 1818 1819 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1820 adev->mman.buffer_funcs_enabled == enable) 1821 return; 1822 1823 if (enable) { 1824 struct amdgpu_ring *ring; 1825 struct drm_gpu_scheduler *sched; 1826 1827 ring = adev->mman.buffer_funcs_ring; 1828 sched = &ring->sched; 1829 r = drm_sched_entity_init(&adev->mman.entity, 1830 DRM_SCHED_PRIORITY_KERNEL, &sched, 1831 1, NULL); 1832 if (r) { 1833 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1834 r); 1835 return; 1836 } 1837 } else { 1838 drm_sched_entity_destroy(&adev->mman.entity); 1839 dma_fence_put(man->move); 1840 man->move = NULL; 1841 } 1842 1843 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1844 if (enable) 1845 size = adev->gmc.real_vram_size; 1846 else 1847 size = adev->gmc.visible_vram_size; 1848 man->size = size >> PAGE_SHIFT; 1849 adev->mman.buffer_funcs_enabled = enable; 1850 } 1851 1852 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) 1853 { 1854 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 1855 vm_fault_t ret; 1856 1857 ret = ttm_bo_vm_reserve(bo, vmf); 1858 if (ret) 1859 return ret; 1860 1861 ret = amdgpu_bo_fault_reserve_notify(bo); 1862 if (ret) 1863 goto unlock; 1864 1865 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 1866 TTM_BO_VM_NUM_PREFAULT, 1); 1867 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 1868 return ret; 1869 1870 unlock: 1871 dma_resv_unlock(bo->base.resv); 1872 return ret; 1873 } 1874 1875 static const struct vm_operations_struct amdgpu_ttm_vm_ops = { 1876 .fault = amdgpu_ttm_fault, 1877 .open = ttm_bo_vm_open, 1878 .close = ttm_bo_vm_close, 1879 .access = ttm_bo_vm_access 1880 }; 1881 1882 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1883 { 1884 struct drm_file *file_priv = filp->private_data; 1885 struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); 1886 int r; 1887 1888 r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1889 if (unlikely(r != 0)) 1890 return r; 1891 1892 vma->vm_ops = &amdgpu_ttm_vm_ops; 1893 return 0; 1894 } 1895 1896 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1897 uint64_t dst_offset, uint32_t byte_count, 1898 struct dma_resv *resv, 1899 struct dma_fence **fence, bool direct_submit, 1900 bool vm_needs_flush, bool tmz) 1901 { 1902 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1903 AMDGPU_IB_POOL_DELAYED; 1904 struct amdgpu_device *adev = ring->adev; 1905 struct amdgpu_job *job; 1906 1907 uint32_t max_bytes; 1908 unsigned num_loops, num_dw; 1909 unsigned i; 1910 int r; 1911 1912 if (direct_submit && !ring->sched.ready) { 1913 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1914 return -EINVAL; 1915 } 1916 1917 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1918 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1919 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1920 1921 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1922 if (r) 1923 return r; 1924 1925 if (vm_needs_flush) { 1926 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1927 adev->gmc.pdb0_bo : adev->gart.bo); 1928 job->vm_needs_flush = true; 1929 } 1930 if (resv) { 1931 r = amdgpu_sync_resv(adev, &job->sync, resv, 1932 AMDGPU_SYNC_ALWAYS, 1933 AMDGPU_FENCE_OWNER_UNDEFINED); 1934 if (r) { 1935 DRM_ERROR("sync failed (%d).\n", r); 1936 goto error_free; 1937 } 1938 } 1939 1940 for (i = 0; i < num_loops; i++) { 1941 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1942 1943 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1944 dst_offset, cur_size_in_bytes, tmz); 1945 1946 src_offset += cur_size_in_bytes; 1947 dst_offset += cur_size_in_bytes; 1948 byte_count -= cur_size_in_bytes; 1949 } 1950 1951 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1952 WARN_ON(job->ibs[0].length_dw > num_dw); 1953 if (direct_submit) 1954 r = amdgpu_job_submit_direct(job, ring, fence); 1955 else 1956 r = amdgpu_job_submit(job, &adev->mman.entity, 1957 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1958 if (r) 1959 goto error_free; 1960 1961 return r; 1962 1963 error_free: 1964 amdgpu_job_free(job); 1965 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1966 return r; 1967 } 1968 1969 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1970 uint32_t src_data, 1971 struct dma_resv *resv, 1972 struct dma_fence **fence) 1973 { 1974 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1975 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1976 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1977 1978 struct amdgpu_res_cursor cursor; 1979 unsigned int num_loops, num_dw; 1980 uint64_t num_bytes; 1981 1982 struct amdgpu_job *job; 1983 int r; 1984 1985 if (!adev->mman.buffer_funcs_enabled) { 1986 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1987 return -EINVAL; 1988 } 1989 1990 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 1991 r = amdgpu_ttm_alloc_gart(&bo->tbo); 1992 if (r) 1993 return r; 1994 } 1995 1996 num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT; 1997 num_loops = 0; 1998 1999 amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); 2000 while (cursor.remaining) { 2001 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 2002 amdgpu_res_next(&cursor, cursor.size); 2003 } 2004 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2005 2006 /* for IB padding */ 2007 num_dw += 64; 2008 2009 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2010 &job); 2011 if (r) 2012 return r; 2013 2014 if (resv) { 2015 r = amdgpu_sync_resv(adev, &job->sync, resv, 2016 AMDGPU_SYNC_ALWAYS, 2017 AMDGPU_FENCE_OWNER_UNDEFINED); 2018 if (r) { 2019 DRM_ERROR("sync failed (%d).\n", r); 2020 goto error_free; 2021 } 2022 } 2023 2024 amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); 2025 while (cursor.remaining) { 2026 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2027 uint64_t dst_addr = cursor.start; 2028 2029 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 2030 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2031 cur_size); 2032 2033 amdgpu_res_next(&cursor, cur_size); 2034 } 2035 2036 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2037 WARN_ON(job->ibs[0].length_dw > num_dw); 2038 r = amdgpu_job_submit(job, &adev->mman.entity, 2039 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2040 if (r) 2041 goto error_free; 2042 2043 return 0; 2044 2045 error_free: 2046 amdgpu_job_free(job); 2047 return r; 2048 } 2049 2050 #if defined(CONFIG_DEBUG_FS) 2051 2052 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2053 { 2054 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2055 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2056 TTM_PL_VRAM); 2057 struct drm_printer p = drm_seq_file_printer(m); 2058 2059 man->func->debug(man, &p); 2060 return 0; 2061 } 2062 2063 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2064 { 2065 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2066 2067 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2068 } 2069 2070 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2071 { 2072 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2073 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2074 TTM_PL_TT); 2075 struct drm_printer p = drm_seq_file_printer(m); 2076 2077 man->func->debug(man, &p); 2078 return 0; 2079 } 2080 2081 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2082 { 2083 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2084 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2085 AMDGPU_PL_GDS); 2086 struct drm_printer p = drm_seq_file_printer(m); 2087 2088 man->func->debug(man, &p); 2089 return 0; 2090 } 2091 2092 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2093 { 2094 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2095 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2096 AMDGPU_PL_GWS); 2097 struct drm_printer p = drm_seq_file_printer(m); 2098 2099 man->func->debug(man, &p); 2100 return 0; 2101 } 2102 2103 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2104 { 2105 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2106 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2107 AMDGPU_PL_OA); 2108 struct drm_printer p = drm_seq_file_printer(m); 2109 2110 man->func->debug(man, &p); 2111 return 0; 2112 } 2113 2114 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2115 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2116 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2117 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2118 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2119 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2120 2121 /* 2122 * amdgpu_ttm_vram_read - Linear read access to VRAM 2123 * 2124 * Accesses VRAM via MMIO for debugging purposes. 2125 */ 2126 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2127 size_t size, loff_t *pos) 2128 { 2129 struct amdgpu_device *adev = file_inode(f)->i_private; 2130 ssize_t result = 0; 2131 2132 if (size & 0x3 || *pos & 0x3) 2133 return -EINVAL; 2134 2135 if (*pos >= adev->gmc.mc_vram_size) 2136 return -ENXIO; 2137 2138 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2139 while (size) { 2140 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2141 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2142 2143 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2144 if (copy_to_user(buf, value, bytes)) 2145 return -EFAULT; 2146 2147 result += bytes; 2148 buf += bytes; 2149 *pos += bytes; 2150 size -= bytes; 2151 } 2152 2153 return result; 2154 } 2155 2156 /* 2157 * amdgpu_ttm_vram_write - Linear write access to VRAM 2158 * 2159 * Accesses VRAM via MMIO for debugging purposes. 2160 */ 2161 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2162 size_t size, loff_t *pos) 2163 { 2164 struct amdgpu_device *adev = file_inode(f)->i_private; 2165 ssize_t result = 0; 2166 int r; 2167 2168 if (size & 0x3 || *pos & 0x3) 2169 return -EINVAL; 2170 2171 if (*pos >= adev->gmc.mc_vram_size) 2172 return -ENXIO; 2173 2174 while (size) { 2175 unsigned long flags; 2176 uint32_t value; 2177 2178 if (*pos >= adev->gmc.mc_vram_size) 2179 return result; 2180 2181 r = get_user(value, (uint32_t *)buf); 2182 if (r) 2183 return r; 2184 2185 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2186 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2187 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2188 WREG32_NO_KIQ(mmMM_DATA, value); 2189 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2190 2191 result += 4; 2192 buf += 4; 2193 *pos += 4; 2194 size -= 4; 2195 } 2196 2197 return result; 2198 } 2199 2200 static const struct file_operations amdgpu_ttm_vram_fops = { 2201 .owner = THIS_MODULE, 2202 .read = amdgpu_ttm_vram_read, 2203 .write = amdgpu_ttm_vram_write, 2204 .llseek = default_llseek, 2205 }; 2206 2207 /* 2208 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2209 * 2210 * This function is used to read memory that has been mapped to the 2211 * GPU and the known addresses are not physical addresses but instead 2212 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2213 */ 2214 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2215 size_t size, loff_t *pos) 2216 { 2217 struct amdgpu_device *adev = file_inode(f)->i_private; 2218 struct iommu_domain *dom; 2219 ssize_t result = 0; 2220 int r; 2221 2222 /* retrieve the IOMMU domain if any for this device */ 2223 dom = iommu_get_domain_for_dev(adev->dev); 2224 2225 while (size) { 2226 phys_addr_t addr = *pos & PAGE_MASK; 2227 loff_t off = *pos & ~PAGE_MASK; 2228 size_t bytes = PAGE_SIZE - off; 2229 unsigned long pfn; 2230 struct page *p; 2231 void *ptr; 2232 2233 bytes = bytes < size ? bytes : size; 2234 2235 /* Translate the bus address to a physical address. If 2236 * the domain is NULL it means there is no IOMMU active 2237 * and the address translation is the identity 2238 */ 2239 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2240 2241 pfn = addr >> PAGE_SHIFT; 2242 if (!pfn_valid(pfn)) 2243 return -EPERM; 2244 2245 p = pfn_to_page(pfn); 2246 if (p->mapping != adev->mman.bdev.dev_mapping) 2247 return -EPERM; 2248 2249 ptr = kmap(p); 2250 r = copy_to_user(buf, ptr + off, bytes); 2251 kunmap(p); 2252 if (r) 2253 return -EFAULT; 2254 2255 size -= bytes; 2256 *pos += bytes; 2257 result += bytes; 2258 } 2259 2260 return result; 2261 } 2262 2263 /* 2264 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2265 * 2266 * This function is used to write memory that has been mapped to the 2267 * GPU and the known addresses are not physical addresses but instead 2268 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2269 */ 2270 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2271 size_t size, loff_t *pos) 2272 { 2273 struct amdgpu_device *adev = file_inode(f)->i_private; 2274 struct iommu_domain *dom; 2275 ssize_t result = 0; 2276 int r; 2277 2278 dom = iommu_get_domain_for_dev(adev->dev); 2279 2280 while (size) { 2281 phys_addr_t addr = *pos & PAGE_MASK; 2282 loff_t off = *pos & ~PAGE_MASK; 2283 size_t bytes = PAGE_SIZE - off; 2284 unsigned long pfn; 2285 struct page *p; 2286 void *ptr; 2287 2288 bytes = bytes < size ? bytes : size; 2289 2290 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2291 2292 pfn = addr >> PAGE_SHIFT; 2293 if (!pfn_valid(pfn)) 2294 return -EPERM; 2295 2296 p = pfn_to_page(pfn); 2297 if (p->mapping != adev->mman.bdev.dev_mapping) 2298 return -EPERM; 2299 2300 ptr = kmap(p); 2301 r = copy_from_user(ptr + off, buf, bytes); 2302 kunmap(p); 2303 if (r) 2304 return -EFAULT; 2305 2306 size -= bytes; 2307 *pos += bytes; 2308 result += bytes; 2309 } 2310 2311 return result; 2312 } 2313 2314 static const struct file_operations amdgpu_ttm_iomem_fops = { 2315 .owner = THIS_MODULE, 2316 .read = amdgpu_iomem_read, 2317 .write = amdgpu_iomem_write, 2318 .llseek = default_llseek 2319 }; 2320 2321 #endif 2322 2323 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2324 { 2325 #if defined(CONFIG_DEBUG_FS) 2326 struct drm_minor *minor = adev_to_drm(adev)->primary; 2327 struct dentry *root = minor->debugfs_root; 2328 2329 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2330 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2331 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2332 &amdgpu_ttm_iomem_fops); 2333 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2334 &amdgpu_mm_vram_table_fops); 2335 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2336 &amdgpu_mm_tt_table_fops); 2337 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2338 &amdgpu_mm_gds_table_fops); 2339 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2340 &amdgpu_mm_gws_table_fops); 2341 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2342 &amdgpu_mm_oa_table_fops); 2343 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2344 &amdgpu_ttm_page_pool_fops); 2345 #endif 2346 } 2347