1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 52 #include <drm/drm_debugfs.h> 53 #include <drm/amdgpu_drm.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "bif/bif_4_1_d.h" 62 63 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 64 65 66 /** 67 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of 68 * memory request. 69 * 70 * @bdev: The TTM BO device object (contains a reference to amdgpu_device) 71 * @type: The type of memory requested 72 * @man: The memory type manager for each domain 73 * 74 * This is called by ttm_bo_init_mm() when a buffer object is being 75 * initialized. 76 */ 77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 78 struct ttm_mem_type_manager *man) 79 { 80 struct amdgpu_device *adev; 81 82 adev = amdgpu_ttm_adev(bdev); 83 84 switch (type) { 85 case TTM_PL_SYSTEM: 86 /* System memory */ 87 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 88 man->available_caching = TTM_PL_MASK_CACHING; 89 man->default_caching = TTM_PL_FLAG_CACHED; 90 break; 91 case TTM_PL_TT: 92 /* GTT memory */ 93 man->func = &amdgpu_gtt_mgr_func; 94 man->gpu_offset = adev->gmc.gart_start; 95 man->available_caching = TTM_PL_MASK_CACHING; 96 man->default_caching = TTM_PL_FLAG_CACHED; 97 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 98 break; 99 case TTM_PL_VRAM: 100 /* "On-card" video ram */ 101 man->func = &amdgpu_vram_mgr_func; 102 man->gpu_offset = adev->gmc.vram_start; 103 man->flags = TTM_MEMTYPE_FLAG_FIXED | 104 TTM_MEMTYPE_FLAG_MAPPABLE; 105 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 106 man->default_caching = TTM_PL_FLAG_WC; 107 break; 108 case AMDGPU_PL_GDS: 109 case AMDGPU_PL_GWS: 110 case AMDGPU_PL_OA: 111 /* On-chip GDS memory*/ 112 man->func = &ttm_bo_manager_func; 113 man->gpu_offset = 0; 114 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; 115 man->available_caching = TTM_PL_FLAG_UNCACHED; 116 man->default_caching = TTM_PL_FLAG_UNCACHED; 117 break; 118 default: 119 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 120 return -EINVAL; 121 } 122 return 0; 123 } 124 125 /** 126 * amdgpu_evict_flags - Compute placement flags 127 * 128 * @bo: The buffer object to evict 129 * @placement: Possible destination(s) for evicted BO 130 * 131 * Fill in placement data when ttm_bo_evict() is called 132 */ 133 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 134 struct ttm_placement *placement) 135 { 136 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 137 struct amdgpu_bo *abo; 138 static const struct ttm_place placements = { 139 .fpfn = 0, 140 .lpfn = 0, 141 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 142 }; 143 144 /* Don't handle scatter gather BOs */ 145 if (bo->type == ttm_bo_type_sg) { 146 placement->num_placement = 0; 147 placement->num_busy_placement = 0; 148 return; 149 } 150 151 /* Object isn't an AMDGPU object so ignore */ 152 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 153 placement->placement = &placements; 154 placement->busy_placement = &placements; 155 placement->num_placement = 1; 156 placement->num_busy_placement = 1; 157 return; 158 } 159 160 abo = ttm_to_amdgpu_bo(bo); 161 switch (bo->mem.mem_type) { 162 case AMDGPU_PL_GDS: 163 case AMDGPU_PL_GWS: 164 case AMDGPU_PL_OA: 165 placement->num_placement = 0; 166 placement->num_busy_placement = 0; 167 return; 168 169 case TTM_PL_VRAM: 170 if (!adev->mman.buffer_funcs_enabled) { 171 /* Move to system memory */ 172 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 173 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 174 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 175 amdgpu_bo_in_cpu_visible_vram(abo)) { 176 177 /* Try evicting to the CPU inaccessible part of VRAM 178 * first, but only set GTT as busy placement, so this 179 * BO will be evicted to GTT rather than causing other 180 * BOs to be evicted from VRAM 181 */ 182 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 183 AMDGPU_GEM_DOMAIN_GTT); 184 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 185 abo->placements[0].lpfn = 0; 186 abo->placement.busy_placement = &abo->placements[1]; 187 abo->placement.num_busy_placement = 1; 188 } else { 189 /* Move to GTT memory */ 190 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 191 } 192 break; 193 case TTM_PL_TT: 194 default: 195 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 196 break; 197 } 198 *placement = abo->placement; 199 } 200 201 /** 202 * amdgpu_verify_access - Verify access for a mmap call 203 * 204 * @bo: The buffer object to map 205 * @filp: The file pointer from the process performing the mmap 206 * 207 * This is called by ttm_bo_mmap() to verify whether a process 208 * has the right to mmap a BO to their process space. 209 */ 210 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 211 { 212 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 213 214 /* 215 * Don't verify access for KFD BOs. They don't have a GEM 216 * object associated with them. 217 */ 218 if (abo->kfd_bo) 219 return 0; 220 221 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 222 return -EPERM; 223 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 224 filp->private_data); 225 } 226 227 /** 228 * amdgpu_move_null - Register memory for a buffer object 229 * 230 * @bo: The bo to assign the memory to 231 * @new_mem: The memory to be assigned. 232 * 233 * Assign the memory from new_mem to the memory of the buffer object bo. 234 */ 235 static void amdgpu_move_null(struct ttm_buffer_object *bo, 236 struct ttm_mem_reg *new_mem) 237 { 238 struct ttm_mem_reg *old_mem = &bo->mem; 239 240 BUG_ON(old_mem->mm_node != NULL); 241 *old_mem = *new_mem; 242 new_mem->mm_node = NULL; 243 } 244 245 /** 246 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. 247 * 248 * @bo: The bo to assign the memory to. 249 * @mm_node: Memory manager node for drm allocator. 250 * @mem: The region where the bo resides. 251 * 252 */ 253 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 254 struct drm_mm_node *mm_node, 255 struct ttm_mem_reg *mem) 256 { 257 uint64_t addr = 0; 258 259 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { 260 addr = mm_node->start << PAGE_SHIFT; 261 addr += bo->bdev->man[mem->mem_type].gpu_offset; 262 } 263 return addr; 264 } 265 266 /** 267 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to 268 * @offset. It also modifies the offset to be within the drm_mm_node returned 269 * 270 * @mem: The region where the bo resides. 271 * @offset: The offset that drm_mm_node is used for finding. 272 * 273 */ 274 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem, 275 uint64_t *offset) 276 { 277 struct drm_mm_node *mm_node = mem->mm_node; 278 279 while (*offset >= (mm_node->size << PAGE_SHIFT)) { 280 *offset -= (mm_node->size << PAGE_SHIFT); 281 ++mm_node; 282 } 283 return mm_node; 284 } 285 286 /** 287 * amdgpu_ttm_map_buffer - Map memory into the GART windows 288 * @bo: buffer object to map 289 * @mem: memory object to map 290 * @mm_node: drm_mm node object to map 291 * @num_pages: number of pages to map 292 * @offset: offset into @mm_node where to start 293 * @window: which GART window to use 294 * @ring: DMA ring to use for the copy 295 * @tmz: if we should setup a TMZ enabled mapping 296 * @addr: resulting address inside the MC address space 297 * 298 * Setup one of the GART windows to access a specific piece of memory or return 299 * the physical address for local memory. 300 */ 301 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 302 struct ttm_mem_reg *mem, 303 struct drm_mm_node *mm_node, 304 unsigned num_pages, uint64_t offset, 305 unsigned window, struct amdgpu_ring *ring, 306 bool tmz, uint64_t *addr) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 struct amdgpu_job *job; 310 unsigned num_dw, num_bytes; 311 struct dma_fence *fence; 312 uint64_t src_addr, dst_addr; 313 void *cpu_addr; 314 uint64_t flags; 315 unsigned int i; 316 int r; 317 318 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 319 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 320 321 /* Map only what can't be accessed directly */ 322 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 323 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; 324 return 0; 325 } 326 327 *addr = adev->gmc.gart_start; 328 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 329 AMDGPU_GPU_PAGE_SIZE; 330 *addr += offset & ~PAGE_MASK; 331 332 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 333 num_bytes = num_pages * 8; 334 335 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 336 AMDGPU_IB_POOL_DELAYED, &job); 337 if (r) 338 return r; 339 340 src_addr = num_dw * 4; 341 src_addr += job->ibs[0].gpu_addr; 342 343 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 344 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 345 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 346 dst_addr, num_bytes, false); 347 348 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 349 WARN_ON(job->ibs[0].length_dw > num_dw); 350 351 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 352 if (tmz) 353 flags |= AMDGPU_PTE_TMZ; 354 355 cpu_addr = &job->ibs[0].ptr[num_dw]; 356 357 if (mem->mem_type == TTM_PL_TT) { 358 struct ttm_dma_tt *dma; 359 dma_addr_t *dma_address; 360 361 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm); 362 dma_address = &dma->dma_address[offset >> PAGE_SHIFT]; 363 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, 364 cpu_addr); 365 if (r) 366 goto error_free; 367 } else { 368 dma_addr_t dma_address; 369 370 dma_address = (mm_node->start << PAGE_SHIFT) + offset; 371 dma_address += adev->vm_manager.vram_base_offset; 372 373 for (i = 0; i < num_pages; ++i) { 374 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 375 &dma_address, flags, cpu_addr); 376 if (r) 377 goto error_free; 378 379 dma_address += PAGE_SIZE; 380 } 381 } 382 383 r = amdgpu_job_submit(job, &adev->mman.entity, 384 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 385 if (r) 386 goto error_free; 387 388 dma_fence_put(fence); 389 390 return r; 391 392 error_free: 393 amdgpu_job_free(job); 394 return r; 395 } 396 397 /** 398 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 399 * @adev: amdgpu device 400 * @src: buffer/address where to read from 401 * @dst: buffer/address where to write to 402 * @size: number of bytes to copy 403 * @tmz: if a secure copy should be used 404 * @resv: resv object to sync to 405 * @f: Returns the last fence if multiple jobs are submitted. 406 * 407 * The function copies @size bytes from {src->mem + src->offset} to 408 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 409 * move and different for a BO to BO copy. 410 * 411 */ 412 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 413 const struct amdgpu_copy_mem *src, 414 const struct amdgpu_copy_mem *dst, 415 uint64_t size, bool tmz, 416 struct dma_resv *resv, 417 struct dma_fence **f) 418 { 419 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 420 AMDGPU_GPU_PAGE_SIZE); 421 422 uint64_t src_node_size, dst_node_size, src_offset, dst_offset; 423 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 424 struct drm_mm_node *src_mm, *dst_mm; 425 struct dma_fence *fence = NULL; 426 int r = 0; 427 428 if (!adev->mman.buffer_funcs_enabled) { 429 DRM_ERROR("Trying to move memory with ring turned off.\n"); 430 return -EINVAL; 431 } 432 433 src_offset = src->offset; 434 src_mm = amdgpu_find_mm_node(src->mem, &src_offset); 435 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; 436 437 dst_offset = dst->offset; 438 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); 439 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; 440 441 mutex_lock(&adev->mman.gtt_window_lock); 442 443 while (size) { 444 uint32_t src_page_offset = src_offset & ~PAGE_MASK; 445 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; 446 struct dma_fence *next; 447 uint32_t cur_size; 448 uint64_t from, to; 449 450 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 451 * begins at an offset, then adjust the size accordingly 452 */ 453 cur_size = max(src_page_offset, dst_page_offset); 454 cur_size = min(min3(src_node_size, dst_node_size, size), 455 (uint64_t)(GTT_MAX_BYTES - cur_size)); 456 457 /* Map src to window 0 and dst to window 1. */ 458 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, 459 PFN_UP(cur_size + src_page_offset), 460 src_offset, 0, ring, tmz, &from); 461 if (r) 462 goto error; 463 464 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, 465 PFN_UP(cur_size + dst_page_offset), 466 dst_offset, 1, ring, tmz, &to); 467 if (r) 468 goto error; 469 470 r = amdgpu_copy_buffer(ring, from, to, cur_size, 471 resv, &next, false, true, tmz); 472 if (r) 473 goto error; 474 475 dma_fence_put(fence); 476 fence = next; 477 478 size -= cur_size; 479 if (!size) 480 break; 481 482 src_node_size -= cur_size; 483 if (!src_node_size) { 484 ++src_mm; 485 src_node_size = src_mm->size << PAGE_SHIFT; 486 src_offset = 0; 487 } else { 488 src_offset += cur_size; 489 } 490 491 dst_node_size -= cur_size; 492 if (!dst_node_size) { 493 ++dst_mm; 494 dst_node_size = dst_mm->size << PAGE_SHIFT; 495 dst_offset = 0; 496 } else { 497 dst_offset += cur_size; 498 } 499 } 500 error: 501 mutex_unlock(&adev->mman.gtt_window_lock); 502 if (f) 503 *f = dma_fence_get(fence); 504 dma_fence_put(fence); 505 return r; 506 } 507 508 /** 509 * amdgpu_move_blit - Copy an entire buffer to another buffer 510 * 511 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 512 * help move buffers to and from VRAM. 513 */ 514 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 515 bool evict, bool no_wait_gpu, 516 struct ttm_mem_reg *new_mem, 517 struct ttm_mem_reg *old_mem) 518 { 519 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 520 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 521 struct amdgpu_copy_mem src, dst; 522 struct dma_fence *fence = NULL; 523 int r; 524 525 src.bo = bo; 526 dst.bo = bo; 527 src.mem = old_mem; 528 dst.mem = new_mem; 529 src.offset = 0; 530 dst.offset = 0; 531 532 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 533 new_mem->num_pages << PAGE_SHIFT, 534 amdgpu_bo_encrypted(abo), 535 bo->base.resv, &fence); 536 if (r) 537 goto error; 538 539 /* clear the space being freed */ 540 if (old_mem->mem_type == TTM_PL_VRAM && 541 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 542 struct dma_fence *wipe_fence = NULL; 543 544 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 545 NULL, &wipe_fence); 546 if (r) { 547 goto error; 548 } else if (wipe_fence) { 549 dma_fence_put(fence); 550 fence = wipe_fence; 551 } 552 } 553 554 /* Always block for VM page tables before committing the new location */ 555 if (bo->type == ttm_bo_type_kernel) 556 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem); 557 else 558 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 559 dma_fence_put(fence); 560 return r; 561 562 error: 563 if (fence) 564 dma_fence_wait(fence, false); 565 dma_fence_put(fence); 566 return r; 567 } 568 569 /** 570 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer 571 * 572 * Called by amdgpu_bo_move(). 573 */ 574 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 575 struct ttm_operation_ctx *ctx, 576 struct ttm_mem_reg *new_mem) 577 { 578 struct ttm_mem_reg *old_mem = &bo->mem; 579 struct ttm_mem_reg tmp_mem; 580 struct ttm_place placements; 581 struct ttm_placement placement; 582 int r; 583 584 /* create space/pages for new_mem in GTT space */ 585 tmp_mem = *new_mem; 586 tmp_mem.mm_node = NULL; 587 placement.num_placement = 1; 588 placement.placement = &placements; 589 placement.num_busy_placement = 1; 590 placement.busy_placement = &placements; 591 placements.fpfn = 0; 592 placements.lpfn = 0; 593 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 594 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 595 if (unlikely(r)) { 596 pr_err("Failed to find GTT space for blit from VRAM\n"); 597 return r; 598 } 599 600 /* set caching flags */ 601 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 602 if (unlikely(r)) { 603 goto out_cleanup; 604 } 605 606 /* Bind the memory to the GTT space */ 607 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx); 608 if (unlikely(r)) { 609 goto out_cleanup; 610 } 611 612 /* blit VRAM to GTT */ 613 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem); 614 if (unlikely(r)) { 615 goto out_cleanup; 616 } 617 618 /* move BO (in tmp_mem) to new_mem */ 619 r = ttm_bo_move_ttm(bo, ctx, new_mem); 620 out_cleanup: 621 ttm_bo_mem_put(bo, &tmp_mem); 622 return r; 623 } 624 625 /** 626 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM 627 * 628 * Called by amdgpu_bo_move(). 629 */ 630 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 631 struct ttm_operation_ctx *ctx, 632 struct ttm_mem_reg *new_mem) 633 { 634 struct ttm_mem_reg *old_mem = &bo->mem; 635 struct ttm_mem_reg tmp_mem; 636 struct ttm_placement placement; 637 struct ttm_place placements; 638 int r; 639 640 /* make space in GTT for old_mem buffer */ 641 tmp_mem = *new_mem; 642 tmp_mem.mm_node = NULL; 643 placement.num_placement = 1; 644 placement.placement = &placements; 645 placement.num_busy_placement = 1; 646 placement.busy_placement = &placements; 647 placements.fpfn = 0; 648 placements.lpfn = 0; 649 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 650 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 651 if (unlikely(r)) { 652 pr_err("Failed to find GTT space for blit to VRAM\n"); 653 return r; 654 } 655 656 /* move/bind old memory to GTT space */ 657 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); 658 if (unlikely(r)) { 659 goto out_cleanup; 660 } 661 662 /* copy to VRAM */ 663 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem); 664 if (unlikely(r)) { 665 goto out_cleanup; 666 } 667 out_cleanup: 668 ttm_bo_mem_put(bo, &tmp_mem); 669 return r; 670 } 671 672 /** 673 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 674 * 675 * Called by amdgpu_bo_move() 676 */ 677 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 678 struct ttm_mem_reg *mem) 679 { 680 struct drm_mm_node *nodes = mem->mm_node; 681 682 if (mem->mem_type == TTM_PL_SYSTEM || 683 mem->mem_type == TTM_PL_TT) 684 return true; 685 if (mem->mem_type != TTM_PL_VRAM) 686 return false; 687 688 /* ttm_mem_reg_ioremap only supports contiguous memory */ 689 if (nodes->size != mem->num_pages) 690 return false; 691 692 return ((nodes->start + nodes->size) << PAGE_SHIFT) 693 <= adev->gmc.visible_vram_size; 694 } 695 696 /** 697 * amdgpu_bo_move - Move a buffer object to a new memory location 698 * 699 * Called by ttm_bo_handle_move_mem() 700 */ 701 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 702 struct ttm_operation_ctx *ctx, 703 struct ttm_mem_reg *new_mem) 704 { 705 struct amdgpu_device *adev; 706 struct amdgpu_bo *abo; 707 struct ttm_mem_reg *old_mem = &bo->mem; 708 int r; 709 710 /* Can't move a pinned BO */ 711 abo = ttm_to_amdgpu_bo(bo); 712 if (WARN_ON_ONCE(abo->pin_count > 0)) 713 return -EINVAL; 714 715 adev = amdgpu_ttm_adev(bo->bdev); 716 717 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 718 amdgpu_move_null(bo, new_mem); 719 return 0; 720 } 721 if ((old_mem->mem_type == TTM_PL_TT && 722 new_mem->mem_type == TTM_PL_SYSTEM) || 723 (old_mem->mem_type == TTM_PL_SYSTEM && 724 new_mem->mem_type == TTM_PL_TT)) { 725 /* bind is enough */ 726 amdgpu_move_null(bo, new_mem); 727 return 0; 728 } 729 if (old_mem->mem_type == AMDGPU_PL_GDS || 730 old_mem->mem_type == AMDGPU_PL_GWS || 731 old_mem->mem_type == AMDGPU_PL_OA || 732 new_mem->mem_type == AMDGPU_PL_GDS || 733 new_mem->mem_type == AMDGPU_PL_GWS || 734 new_mem->mem_type == AMDGPU_PL_OA) { 735 /* Nothing to save here */ 736 amdgpu_move_null(bo, new_mem); 737 return 0; 738 } 739 740 if (!adev->mman.buffer_funcs_enabled) { 741 r = -ENODEV; 742 goto memcpy; 743 } 744 745 if (old_mem->mem_type == TTM_PL_VRAM && 746 new_mem->mem_type == TTM_PL_SYSTEM) { 747 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); 748 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 749 new_mem->mem_type == TTM_PL_VRAM) { 750 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); 751 } else { 752 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, 753 new_mem, old_mem); 754 } 755 756 if (r) { 757 memcpy: 758 /* Check that all memory is CPU accessible */ 759 if (!amdgpu_mem_visible(adev, old_mem) || 760 !amdgpu_mem_visible(adev, new_mem)) { 761 pr_err("Move buffer fallback to memcpy unavailable\n"); 762 return r; 763 } 764 765 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 766 if (r) 767 return r; 768 } 769 770 if (bo->type == ttm_bo_type_device && 771 new_mem->mem_type == TTM_PL_VRAM && 772 old_mem->mem_type != TTM_PL_VRAM) { 773 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 774 * accesses the BO after it's moved. 775 */ 776 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 777 } 778 779 /* update statistics */ 780 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 781 return 0; 782 } 783 784 /** 785 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 786 * 787 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 788 */ 789 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 790 { 791 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 792 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 793 struct drm_mm_node *mm_node = mem->mm_node; 794 795 mem->bus.addr = NULL; 796 mem->bus.offset = 0; 797 mem->bus.size = mem->num_pages << PAGE_SHIFT; 798 mem->bus.base = 0; 799 mem->bus.is_iomem = false; 800 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 801 return -EINVAL; 802 switch (mem->mem_type) { 803 case TTM_PL_SYSTEM: 804 /* system memory */ 805 return 0; 806 case TTM_PL_TT: 807 break; 808 case TTM_PL_VRAM: 809 mem->bus.offset = mem->start << PAGE_SHIFT; 810 /* check if it's visible */ 811 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size) 812 return -EINVAL; 813 /* Only physically contiguous buffers apply. In a contiguous 814 * buffer, size of the first mm_node would match the number of 815 * pages in ttm_mem_reg. 816 */ 817 if (adev->mman.aper_base_kaddr && 818 (mm_node->size == mem->num_pages)) 819 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 820 mem->bus.offset; 821 822 mem->bus.base = adev->gmc.aper_base; 823 mem->bus.is_iomem = true; 824 break; 825 default: 826 return -EINVAL; 827 } 828 return 0; 829 } 830 831 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 832 { 833 } 834 835 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 836 unsigned long page_offset) 837 { 838 uint64_t offset = (page_offset << PAGE_SHIFT); 839 struct drm_mm_node *mm; 840 841 mm = amdgpu_find_mm_node(&bo->mem, &offset); 842 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + 843 (offset >> PAGE_SHIFT); 844 } 845 846 /* 847 * TTM backend functions. 848 */ 849 struct amdgpu_ttm_tt { 850 struct ttm_dma_tt ttm; 851 struct drm_gem_object *gobj; 852 u64 offset; 853 uint64_t userptr; 854 struct task_struct *usertask; 855 uint32_t userflags; 856 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 857 struct hmm_range *range; 858 #endif 859 }; 860 861 #ifdef CONFIG_DRM_AMDGPU_USERPTR 862 /* flags used by HMM internal, not related to CPU/GPU PTE flags */ 863 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { 864 (1 << 0), /* HMM_PFN_VALID */ 865 (1 << 1), /* HMM_PFN_WRITE */ 866 }; 867 868 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { 869 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ 870 0, /* HMM_PFN_NONE */ 871 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ 872 }; 873 874 /** 875 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 876 * memory and start HMM tracking CPU page table update 877 * 878 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 879 * once afterwards to stop HMM tracking 880 */ 881 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 882 { 883 struct ttm_tt *ttm = bo->tbo.ttm; 884 struct amdgpu_ttm_tt *gtt = (void *)ttm; 885 unsigned long start = gtt->userptr; 886 struct vm_area_struct *vma; 887 struct hmm_range *range; 888 unsigned long timeout; 889 struct mm_struct *mm; 890 unsigned long i; 891 int r = 0; 892 893 mm = bo->notifier.mm; 894 if (unlikely(!mm)) { 895 DRM_DEBUG_DRIVER("BO is not registered?\n"); 896 return -EFAULT; 897 } 898 899 /* Another get_user_pages is running at the same time?? */ 900 if (WARN_ON(gtt->range)) 901 return -EFAULT; 902 903 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 904 return -ESRCH; 905 906 range = kzalloc(sizeof(*range), GFP_KERNEL); 907 if (unlikely(!range)) { 908 r = -ENOMEM; 909 goto out; 910 } 911 range->notifier = &bo->notifier; 912 range->flags = hmm_range_flags; 913 range->values = hmm_range_values; 914 range->pfn_shift = PAGE_SHIFT; 915 range->start = bo->notifier.interval_tree.start; 916 range->end = bo->notifier.interval_tree.last + 1; 917 range->default_flags = hmm_range_flags[HMM_PFN_VALID]; 918 if (!amdgpu_ttm_tt_is_readonly(ttm)) 919 range->default_flags |= range->flags[HMM_PFN_WRITE]; 920 921 range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns), 922 GFP_KERNEL); 923 if (unlikely(!range->pfns)) { 924 r = -ENOMEM; 925 goto out_free_ranges; 926 } 927 928 down_read(&mm->mmap_sem); 929 vma = find_vma(mm, start); 930 if (unlikely(!vma || start < vma->vm_start)) { 931 r = -EFAULT; 932 goto out_unlock; 933 } 934 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 935 vma->vm_file)) { 936 r = -EPERM; 937 goto out_unlock; 938 } 939 up_read(&mm->mmap_sem); 940 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 941 942 retry: 943 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 944 945 down_read(&mm->mmap_sem); 946 r = hmm_range_fault(range); 947 up_read(&mm->mmap_sem); 948 if (unlikely(r <= 0)) { 949 /* 950 * FIXME: This timeout should encompass the retry from 951 * mmu_interval_read_retry() as well. 952 */ 953 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout)) 954 goto retry; 955 goto out_free_pfns; 956 } 957 958 for (i = 0; i < ttm->num_pages; i++) { 959 /* FIXME: The pages cannot be touched outside the notifier_lock */ 960 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]); 961 if (unlikely(!pages[i])) { 962 pr_err("Page fault failed for pfn[%lu] = 0x%llx\n", 963 i, range->pfns[i]); 964 r = -ENOMEM; 965 966 goto out_free_pfns; 967 } 968 } 969 970 gtt->range = range; 971 mmput(mm); 972 973 return 0; 974 975 out_unlock: 976 up_read(&mm->mmap_sem); 977 out_free_pfns: 978 kvfree(range->pfns); 979 out_free_ranges: 980 kfree(range); 981 out: 982 mmput(mm); 983 return r; 984 } 985 986 /** 987 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 988 * Check if the pages backing this ttm range have been invalidated 989 * 990 * Returns: true if pages are still valid 991 */ 992 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 993 { 994 struct amdgpu_ttm_tt *gtt = (void *)ttm; 995 bool r = false; 996 997 if (!gtt || !gtt->userptr) 998 return false; 999 1000 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n", 1001 gtt->userptr, ttm->num_pages); 1002 1003 WARN_ONCE(!gtt->range || !gtt->range->pfns, 1004 "No user pages to check\n"); 1005 1006 if (gtt->range) { 1007 /* 1008 * FIXME: Must always hold notifier_lock for this, and must 1009 * not ignore the return code. 1010 */ 1011 r = mmu_interval_read_retry(gtt->range->notifier, 1012 gtt->range->notifier_seq); 1013 kvfree(gtt->range->pfns); 1014 kfree(gtt->range); 1015 gtt->range = NULL; 1016 } 1017 1018 return !r; 1019 } 1020 #endif 1021 1022 /** 1023 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 1024 * 1025 * Called by amdgpu_cs_list_validate(). This creates the page list 1026 * that backs user memory and will ultimately be mapped into the device 1027 * address space. 1028 */ 1029 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 1030 { 1031 unsigned long i; 1032 1033 for (i = 0; i < ttm->num_pages; ++i) 1034 ttm->pages[i] = pages ? pages[i] : NULL; 1035 } 1036 1037 /** 1038 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 1039 * 1040 * Called by amdgpu_ttm_backend_bind() 1041 **/ 1042 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 1043 { 1044 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1045 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1046 unsigned nents; 1047 int r; 1048 1049 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1050 enum dma_data_direction direction = write ? 1051 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1052 1053 /* Allocate an SG array and squash pages into it */ 1054 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 1055 ttm->num_pages << PAGE_SHIFT, 1056 GFP_KERNEL); 1057 if (r) 1058 goto release_sg; 1059 1060 /* Map SG to device */ 1061 r = -ENOMEM; 1062 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 1063 if (nents == 0) 1064 goto release_sg; 1065 1066 /* convert SG to linear array of pages and dma addresses */ 1067 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1068 gtt->ttm.dma_address, ttm->num_pages); 1069 1070 return 0; 1071 1072 release_sg: 1073 kfree(ttm->sg); 1074 return r; 1075 } 1076 1077 /** 1078 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 1079 */ 1080 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 1081 { 1082 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1083 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1084 1085 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1086 enum dma_data_direction direction = write ? 1087 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1088 1089 /* double check that we don't free the table twice */ 1090 if (!ttm->sg->sgl) 1091 return; 1092 1093 /* unmap the pages mapped to the device */ 1094 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 1095 1096 sg_free_table(ttm->sg); 1097 1098 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 1099 if (gtt->range) { 1100 unsigned long i; 1101 1102 for (i = 0; i < ttm->num_pages; i++) { 1103 if (ttm->pages[i] != 1104 hmm_device_entry_to_page(gtt->range, 1105 gtt->range->pfns[i])) 1106 break; 1107 } 1108 1109 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 1110 } 1111 #endif 1112 } 1113 1114 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 1115 struct ttm_buffer_object *tbo, 1116 uint64_t flags) 1117 { 1118 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 1119 struct ttm_tt *ttm = tbo->ttm; 1120 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1121 int r; 1122 1123 if (amdgpu_bo_encrypted(abo)) 1124 flags |= AMDGPU_PTE_TMZ; 1125 1126 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 1127 uint64_t page_idx = 1; 1128 1129 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 1130 ttm->pages, gtt->ttm.dma_address, flags); 1131 if (r) 1132 goto gart_bind_fail; 1133 1134 /* The memory type of the first page defaults to UC. Now 1135 * modify the memory type to NC from the second page of 1136 * the BO onward. 1137 */ 1138 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1139 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 1140 1141 r = amdgpu_gart_bind(adev, 1142 gtt->offset + (page_idx << PAGE_SHIFT), 1143 ttm->num_pages - page_idx, 1144 &ttm->pages[page_idx], 1145 &(gtt->ttm.dma_address[page_idx]), flags); 1146 } else { 1147 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1148 ttm->pages, gtt->ttm.dma_address, flags); 1149 } 1150 1151 gart_bind_fail: 1152 if (r) 1153 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1154 ttm->num_pages, gtt->offset); 1155 1156 return r; 1157 } 1158 1159 /** 1160 * amdgpu_ttm_backend_bind - Bind GTT memory 1161 * 1162 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 1163 * This handles binding GTT memory to the device address space. 1164 */ 1165 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 1166 struct ttm_mem_reg *bo_mem) 1167 { 1168 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1169 struct amdgpu_ttm_tt *gtt = (void*)ttm; 1170 uint64_t flags; 1171 int r = 0; 1172 1173 if (gtt->userptr) { 1174 r = amdgpu_ttm_tt_pin_userptr(ttm); 1175 if (r) { 1176 DRM_ERROR("failed to pin userptr\n"); 1177 return r; 1178 } 1179 } 1180 if (!ttm->num_pages) { 1181 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 1182 ttm->num_pages, bo_mem, ttm); 1183 } 1184 1185 if (bo_mem->mem_type == AMDGPU_PL_GDS || 1186 bo_mem->mem_type == AMDGPU_PL_GWS || 1187 bo_mem->mem_type == AMDGPU_PL_OA) 1188 return -EINVAL; 1189 1190 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 1191 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 1192 return 0; 1193 } 1194 1195 /* compute PTE flags relevant to this BO memory */ 1196 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 1197 1198 /* bind pages into GART page tables */ 1199 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 1200 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1201 ttm->pages, gtt->ttm.dma_address, flags); 1202 1203 if (r) 1204 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1205 ttm->num_pages, gtt->offset); 1206 return r; 1207 } 1208 1209 /** 1210 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object 1211 */ 1212 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1213 { 1214 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1215 struct ttm_operation_ctx ctx = { false, false }; 1216 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; 1217 struct ttm_mem_reg tmp; 1218 struct ttm_placement placement; 1219 struct ttm_place placements; 1220 uint64_t addr, flags; 1221 int r; 1222 1223 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1224 return 0; 1225 1226 addr = amdgpu_gmc_agp_addr(bo); 1227 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1228 bo->mem.start = addr >> PAGE_SHIFT; 1229 } else { 1230 1231 /* allocate GART space */ 1232 tmp = bo->mem; 1233 tmp.mm_node = NULL; 1234 placement.num_placement = 1; 1235 placement.placement = &placements; 1236 placement.num_busy_placement = 1; 1237 placement.busy_placement = &placements; 1238 placements.fpfn = 0; 1239 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1240 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | 1241 TTM_PL_FLAG_TT; 1242 1243 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1244 if (unlikely(r)) 1245 return r; 1246 1247 /* compute PTE flags for this buffer object */ 1248 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1249 1250 /* Bind pages */ 1251 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1252 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1253 if (unlikely(r)) { 1254 ttm_bo_mem_put(bo, &tmp); 1255 return r; 1256 } 1257 1258 ttm_bo_mem_put(bo, &bo->mem); 1259 bo->mem = tmp; 1260 } 1261 1262 bo->offset = (bo->mem.start << PAGE_SHIFT) + 1263 bo->bdev->man[bo->mem.mem_type].gpu_offset; 1264 1265 return 0; 1266 } 1267 1268 /** 1269 * amdgpu_ttm_recover_gart - Rebind GTT pages 1270 * 1271 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1272 * rebind GTT pages during a GPU reset. 1273 */ 1274 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1275 { 1276 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1277 uint64_t flags; 1278 int r; 1279 1280 if (!tbo->ttm) 1281 return 0; 1282 1283 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1284 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1285 1286 return r; 1287 } 1288 1289 /** 1290 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1291 * 1292 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1293 * ttm_tt_destroy(). 1294 */ 1295 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 1296 { 1297 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1298 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1299 int r; 1300 1301 /* if the pages have userptr pinning then clear that first */ 1302 if (gtt->userptr) 1303 amdgpu_ttm_tt_unpin_userptr(ttm); 1304 1305 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1306 return 0; 1307 1308 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1309 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1310 if (r) 1311 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", 1312 gtt->ttm.ttm.num_pages, gtt->offset); 1313 return r; 1314 } 1315 1316 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 1317 { 1318 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1319 1320 if (gtt->usertask) 1321 put_task_struct(gtt->usertask); 1322 1323 ttm_dma_tt_fini(>t->ttm); 1324 kfree(gtt); 1325 } 1326 1327 static struct ttm_backend_func amdgpu_backend_func = { 1328 .bind = &amdgpu_ttm_backend_bind, 1329 .unbind = &amdgpu_ttm_backend_unbind, 1330 .destroy = &amdgpu_ttm_backend_destroy, 1331 }; 1332 1333 /** 1334 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1335 * 1336 * @bo: The buffer object to create a GTT ttm_tt object around 1337 * 1338 * Called by ttm_tt_create(). 1339 */ 1340 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1341 uint32_t page_flags) 1342 { 1343 struct amdgpu_ttm_tt *gtt; 1344 1345 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1346 if (gtt == NULL) { 1347 return NULL; 1348 } 1349 gtt->ttm.ttm.func = &amdgpu_backend_func; 1350 gtt->gobj = &bo->base; 1351 1352 /* allocate space for the uninitialized page entries */ 1353 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) { 1354 kfree(gtt); 1355 return NULL; 1356 } 1357 return >t->ttm.ttm; 1358 } 1359 1360 /** 1361 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1362 * 1363 * Map the pages of a ttm_tt object to an address space visible 1364 * to the underlying device. 1365 */ 1366 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, 1367 struct ttm_operation_ctx *ctx) 1368 { 1369 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 1370 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1371 1372 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1373 if (gtt && gtt->userptr) { 1374 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1375 if (!ttm->sg) 1376 return -ENOMEM; 1377 1378 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1379 ttm->state = tt_unbound; 1380 return 0; 1381 } 1382 1383 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1384 if (!ttm->sg) { 1385 struct dma_buf_attachment *attach; 1386 struct sg_table *sgt; 1387 1388 attach = gtt->gobj->import_attach; 1389 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1390 if (IS_ERR(sgt)) 1391 return PTR_ERR(sgt); 1392 1393 ttm->sg = sgt; 1394 } 1395 1396 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1397 gtt->ttm.dma_address, 1398 ttm->num_pages); 1399 ttm->state = tt_unbound; 1400 return 0; 1401 } 1402 1403 #ifdef CONFIG_SWIOTLB 1404 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1405 return ttm_dma_populate(>t->ttm, adev->dev, ctx); 1406 } 1407 #endif 1408 1409 /* fall back to generic helper to populate the page array 1410 * and map them to the device */ 1411 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx); 1412 } 1413 1414 /** 1415 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1416 * 1417 * Unmaps pages of a ttm_tt object from the device address space and 1418 * unpopulates the page array backing it. 1419 */ 1420 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 1421 { 1422 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1423 struct amdgpu_device *adev; 1424 1425 if (gtt && gtt->userptr) { 1426 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1427 kfree(ttm->sg); 1428 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1429 return; 1430 } 1431 1432 if (ttm->sg && gtt->gobj->import_attach) { 1433 struct dma_buf_attachment *attach; 1434 1435 attach = gtt->gobj->import_attach; 1436 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1437 ttm->sg = NULL; 1438 return; 1439 } 1440 1441 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1442 return; 1443 1444 adev = amdgpu_ttm_adev(ttm->bdev); 1445 1446 #ifdef CONFIG_SWIOTLB 1447 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1448 ttm_dma_unpopulate(>t->ttm, adev->dev); 1449 return; 1450 } 1451 #endif 1452 1453 /* fall back to generic helper to unmap and unpopulate array */ 1454 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); 1455 } 1456 1457 /** 1458 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1459 * task 1460 * 1461 * @ttm: The ttm_tt object to bind this userptr object to 1462 * @addr: The address in the current tasks VM space to use 1463 * @flags: Requirements of userptr object. 1464 * 1465 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1466 * to current task 1467 */ 1468 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1469 uint32_t flags) 1470 { 1471 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1472 1473 if (gtt == NULL) 1474 return -EINVAL; 1475 1476 gtt->userptr = addr; 1477 gtt->userflags = flags; 1478 1479 if (gtt->usertask) 1480 put_task_struct(gtt->usertask); 1481 gtt->usertask = current->group_leader; 1482 get_task_struct(gtt->usertask); 1483 1484 return 0; 1485 } 1486 1487 /** 1488 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1489 */ 1490 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1491 { 1492 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1493 1494 if (gtt == NULL) 1495 return NULL; 1496 1497 if (gtt->usertask == NULL) 1498 return NULL; 1499 1500 return gtt->usertask->mm; 1501 } 1502 1503 /** 1504 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1505 * address range for the current task. 1506 * 1507 */ 1508 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1509 unsigned long end) 1510 { 1511 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1512 unsigned long size; 1513 1514 if (gtt == NULL || !gtt->userptr) 1515 return false; 1516 1517 /* Return false if no part of the ttm_tt object lies within 1518 * the range 1519 */ 1520 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 1521 if (gtt->userptr > end || gtt->userptr + size <= start) 1522 return false; 1523 1524 return true; 1525 } 1526 1527 /** 1528 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1529 */ 1530 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1531 { 1532 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1533 1534 if (gtt == NULL || !gtt->userptr) 1535 return false; 1536 1537 return true; 1538 } 1539 1540 /** 1541 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1542 */ 1543 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1544 { 1545 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1546 1547 if (gtt == NULL) 1548 return false; 1549 1550 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1551 } 1552 1553 /** 1554 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1555 * 1556 * @ttm: The ttm_tt object to compute the flags for 1557 * @mem: The memory registry backing this ttm_tt object 1558 * 1559 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1560 */ 1561 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem) 1562 { 1563 uint64_t flags = 0; 1564 1565 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1566 flags |= AMDGPU_PTE_VALID; 1567 1568 if (mem && mem->mem_type == TTM_PL_TT) { 1569 flags |= AMDGPU_PTE_SYSTEM; 1570 1571 if (ttm->caching_state == tt_cached) 1572 flags |= AMDGPU_PTE_SNOOPED; 1573 } 1574 1575 return flags; 1576 } 1577 1578 /** 1579 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1580 * 1581 * @ttm: The ttm_tt object to compute the flags for 1582 * @mem: The memory registry backing this ttm_tt object 1583 1584 * Figure out the flags to use for a VM PTE (Page Table Entry). 1585 */ 1586 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1587 struct ttm_mem_reg *mem) 1588 { 1589 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1590 1591 flags |= adev->gart.gart_pte_flags; 1592 flags |= AMDGPU_PTE_READABLE; 1593 1594 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1595 flags |= AMDGPU_PTE_WRITEABLE; 1596 1597 return flags; 1598 } 1599 1600 /** 1601 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1602 * object. 1603 * 1604 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1605 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1606 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1607 * used to clean out a memory space. 1608 */ 1609 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1610 const struct ttm_place *place) 1611 { 1612 unsigned long num_pages = bo->mem.num_pages; 1613 struct drm_mm_node *node = bo->mem.mm_node; 1614 struct dma_resv_list *flist; 1615 struct dma_fence *f; 1616 int i; 1617 1618 if (bo->type == ttm_bo_type_kernel && 1619 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1620 return false; 1621 1622 /* If bo is a KFD BO, check if the bo belongs to the current process. 1623 * If true, then return false as any KFD process needs all its BOs to 1624 * be resident to run successfully 1625 */ 1626 flist = dma_resv_get_list(bo->base.resv); 1627 if (flist) { 1628 for (i = 0; i < flist->shared_count; ++i) { 1629 f = rcu_dereference_protected(flist->shared[i], 1630 dma_resv_held(bo->base.resv)); 1631 if (amdkfd_fence_check_mm(f, current->mm)) 1632 return false; 1633 } 1634 } 1635 1636 switch (bo->mem.mem_type) { 1637 case TTM_PL_TT: 1638 if (amdgpu_bo_is_amdgpu_bo(bo) && 1639 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1640 return false; 1641 return true; 1642 1643 case TTM_PL_VRAM: 1644 /* Check each drm MM node individually */ 1645 while (num_pages) { 1646 if (place->fpfn < (node->start + node->size) && 1647 !(place->lpfn && place->lpfn <= node->start)) 1648 return true; 1649 1650 num_pages -= node->size; 1651 ++node; 1652 } 1653 return false; 1654 1655 default: 1656 break; 1657 } 1658 1659 return ttm_bo_eviction_valuable(bo, place); 1660 } 1661 1662 /** 1663 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1664 * 1665 * @bo: The buffer object to read/write 1666 * @offset: Offset into buffer object 1667 * @buf: Secondary buffer to write/read from 1668 * @len: Length in bytes of access 1669 * @write: true if writing 1670 * 1671 * This is used to access VRAM that backs a buffer object via MMIO 1672 * access for debugging purposes. 1673 */ 1674 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1675 unsigned long offset, 1676 void *buf, int len, int write) 1677 { 1678 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1679 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1680 struct drm_mm_node *nodes; 1681 uint32_t value = 0; 1682 int ret = 0; 1683 uint64_t pos; 1684 unsigned long flags; 1685 1686 if (bo->mem.mem_type != TTM_PL_VRAM) 1687 return -EIO; 1688 1689 pos = offset; 1690 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); 1691 pos += (nodes->start << PAGE_SHIFT); 1692 1693 while (len && pos < adev->gmc.mc_vram_size) { 1694 uint64_t aligned_pos = pos & ~(uint64_t)3; 1695 uint64_t bytes = 4 - (pos & 3); 1696 uint32_t shift = (pos & 3) * 8; 1697 uint32_t mask = 0xffffffff << shift; 1698 1699 if (len < bytes) { 1700 mask &= 0xffffffff >> (bytes - len) * 8; 1701 bytes = len; 1702 } 1703 1704 if (mask != 0xffffffff) { 1705 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1706 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1707 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1708 if (!write || mask != 0xffffffff) 1709 value = RREG32_NO_KIQ(mmMM_DATA); 1710 if (write) { 1711 value &= ~mask; 1712 value |= (*(uint32_t *)buf << shift) & mask; 1713 WREG32_NO_KIQ(mmMM_DATA, value); 1714 } 1715 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1716 if (!write) { 1717 value = (value & mask) >> shift; 1718 memcpy(buf, &value, bytes); 1719 } 1720 } else { 1721 bytes = (nodes->start + nodes->size) << PAGE_SHIFT; 1722 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); 1723 1724 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, 1725 bytes, write); 1726 } 1727 1728 ret += bytes; 1729 buf = (uint8_t *)buf + bytes; 1730 pos += bytes; 1731 len -= bytes; 1732 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { 1733 ++nodes; 1734 pos = (nodes->start << PAGE_SHIFT); 1735 } 1736 } 1737 1738 return ret; 1739 } 1740 1741 static struct ttm_bo_driver amdgpu_bo_driver = { 1742 .ttm_tt_create = &amdgpu_ttm_tt_create, 1743 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1744 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1745 .init_mem_type = &amdgpu_init_mem_type, 1746 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1747 .evict_flags = &amdgpu_evict_flags, 1748 .move = &amdgpu_bo_move, 1749 .verify_access = &amdgpu_verify_access, 1750 .move_notify = &amdgpu_bo_move_notify, 1751 .release_notify = &amdgpu_bo_release_notify, 1752 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1753 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1754 .io_mem_free = &amdgpu_ttm_io_mem_free, 1755 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1756 .access_memory = &amdgpu_ttm_access_memory, 1757 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1758 }; 1759 1760 /* 1761 * Firmware Reservation functions 1762 */ 1763 /** 1764 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1765 * 1766 * @adev: amdgpu_device pointer 1767 * 1768 * free fw reserved vram if it has been reserved. 1769 */ 1770 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1771 { 1772 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, 1773 NULL, &adev->fw_vram_usage.va); 1774 } 1775 1776 /** 1777 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1778 * 1779 * @adev: amdgpu_device pointer 1780 * 1781 * create bo vram reservation from fw. 1782 */ 1783 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1784 { 1785 uint64_t vram_size = adev->gmc.visible_vram_size; 1786 1787 adev->fw_vram_usage.va = NULL; 1788 adev->fw_vram_usage.reserved_bo = NULL; 1789 1790 if (adev->fw_vram_usage.size == 0 || 1791 adev->fw_vram_usage.size > vram_size) 1792 return 0; 1793 1794 return amdgpu_bo_create_kernel_at(adev, 1795 adev->fw_vram_usage.start_offset, 1796 adev->fw_vram_usage.size, 1797 AMDGPU_GEM_DOMAIN_VRAM, 1798 &adev->fw_vram_usage.reserved_bo, 1799 &adev->fw_vram_usage.va); 1800 } 1801 1802 /* 1803 * Memoy training reservation functions 1804 */ 1805 1806 /** 1807 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1808 * 1809 * @adev: amdgpu_device pointer 1810 * 1811 * free memory training reserved vram if it has been reserved. 1812 */ 1813 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1814 { 1815 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1816 1817 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1818 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1819 ctx->c2p_bo = NULL; 1820 1821 return 0; 1822 } 1823 1824 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size) 1825 { 1826 if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) ) 1827 vram_size -= SZ_1M; 1828 1829 return ALIGN(vram_size, SZ_1M); 1830 } 1831 1832 /** 1833 * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training 1834 * 1835 * @adev: amdgpu_device pointer 1836 * 1837 * create bo vram reservation from memory training. 1838 */ 1839 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev) 1840 { 1841 int ret; 1842 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1843 1844 memset(ctx, 0, sizeof(*ctx)); 1845 if (!adev->fw_vram_usage.mem_train_support) { 1846 DRM_DEBUG("memory training does not support!\n"); 1847 return 0; 1848 } 1849 1850 ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size); 1851 ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1852 ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1853 1854 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1855 ctx->train_data_size, 1856 ctx->p2c_train_data_offset, 1857 ctx->c2p_train_data_offset); 1858 1859 ret = amdgpu_bo_create_kernel_at(adev, 1860 ctx->c2p_train_data_offset, 1861 ctx->train_data_size, 1862 AMDGPU_GEM_DOMAIN_VRAM, 1863 &ctx->c2p_bo, 1864 NULL); 1865 if (ret) { 1866 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1867 amdgpu_ttm_training_reserve_vram_fini(adev); 1868 return ret; 1869 } 1870 1871 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1872 return 0; 1873 } 1874 1875 /** 1876 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1877 * gtt/vram related fields. 1878 * 1879 * This initializes all of the memory space pools that the TTM layer 1880 * will need such as the GTT space (system memory mapped to the device), 1881 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1882 * can be mapped per VMID. 1883 */ 1884 int amdgpu_ttm_init(struct amdgpu_device *adev) 1885 { 1886 uint64_t gtt_size; 1887 int r; 1888 u64 vis_vram_limit; 1889 void *stolen_vga_buf; 1890 1891 mutex_init(&adev->mman.gtt_window_lock); 1892 1893 /* No others user of address space so set it to 0 */ 1894 r = ttm_bo_device_init(&adev->mman.bdev, 1895 &amdgpu_bo_driver, 1896 adev->ddev->anon_inode->i_mapping, 1897 adev->ddev->vma_offset_manager, 1898 dma_addressing_limited(adev->dev)); 1899 if (r) { 1900 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1901 return r; 1902 } 1903 adev->mman.initialized = true; 1904 1905 /* We opt to avoid OOM on system pages allocations */ 1906 adev->mman.bdev.no_retry = true; 1907 1908 /* Initialize VRAM pool with all of VRAM divided into pages */ 1909 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1910 adev->gmc.real_vram_size >> PAGE_SHIFT); 1911 if (r) { 1912 DRM_ERROR("Failed initializing VRAM heap.\n"); 1913 return r; 1914 } 1915 1916 /* Reduce size of CPU-visible VRAM if requested */ 1917 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1918 if (amdgpu_vis_vram_limit > 0 && 1919 vis_vram_limit <= adev->gmc.visible_vram_size) 1920 adev->gmc.visible_vram_size = vis_vram_limit; 1921 1922 /* Change the size here instead of the init above so only lpfn is affected */ 1923 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1924 #ifdef CONFIG_64BIT 1925 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1926 adev->gmc.visible_vram_size); 1927 #endif 1928 1929 /* 1930 *The reserved vram for firmware must be pinned to the specified 1931 *place on the VRAM, so reserve it early. 1932 */ 1933 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1934 if (r) { 1935 return r; 1936 } 1937 1938 /* 1939 *The reserved vram for memory training must be pinned to the specified 1940 *place on the VRAM, so reserve it early. 1941 */ 1942 if (!amdgpu_sriov_vf(adev)) { 1943 r = amdgpu_ttm_training_reserve_vram_init(adev); 1944 if (r) 1945 return r; 1946 } 1947 1948 /* allocate memory as required for VGA 1949 * This is used for VGA emulation and pre-OS scanout buffers to 1950 * avoid display artifacts while transitioning between pre-OS 1951 * and driver. */ 1952 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, 1953 AMDGPU_GEM_DOMAIN_VRAM, 1954 &adev->stolen_vga_memory, 1955 NULL, &stolen_vga_buf); 1956 if (r) 1957 return r; 1958 1959 /* 1960 * reserve TMR memory at the top of VRAM which holds 1961 * IP Discovery data and is protected by PSP. 1962 */ 1963 if (adev->discovery_tmr_size > 0) { 1964 r = amdgpu_bo_create_kernel_at(adev, 1965 adev->gmc.real_vram_size - adev->discovery_tmr_size, 1966 adev->discovery_tmr_size, 1967 AMDGPU_GEM_DOMAIN_VRAM, 1968 &adev->discovery_memory, 1969 NULL); 1970 if (r) 1971 return r; 1972 } 1973 1974 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1975 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1976 1977 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1978 * or whatever the user passed on module init */ 1979 if (amdgpu_gtt_size == -1) { 1980 struct sysinfo si; 1981 1982 si_meminfo(&si); 1983 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1984 adev->gmc.mc_vram_size), 1985 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1986 } 1987 else 1988 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1989 1990 /* Initialize GTT memory pool */ 1991 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); 1992 if (r) { 1993 DRM_ERROR("Failed initializing GTT heap.\n"); 1994 return r; 1995 } 1996 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1997 (unsigned)(gtt_size / (1024 * 1024))); 1998 1999 /* Initialize various on-chip memory pools */ 2000 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 2001 adev->gds.gds_size); 2002 if (r) { 2003 DRM_ERROR("Failed initializing GDS heap.\n"); 2004 return r; 2005 } 2006 2007 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 2008 adev->gds.gws_size); 2009 if (r) { 2010 DRM_ERROR("Failed initializing gws heap.\n"); 2011 return r; 2012 } 2013 2014 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 2015 adev->gds.oa_size); 2016 if (r) { 2017 DRM_ERROR("Failed initializing oa heap.\n"); 2018 return r; 2019 } 2020 2021 return 0; 2022 } 2023 2024 /** 2025 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm 2026 */ 2027 void amdgpu_ttm_late_init(struct amdgpu_device *adev) 2028 { 2029 void *stolen_vga_buf; 2030 /* return the VGA stolen memory (if any) back to VRAM */ 2031 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 2032 } 2033 2034 /** 2035 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2036 */ 2037 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2038 { 2039 if (!adev->mman.initialized) 2040 return; 2041 2042 amdgpu_ttm_training_reserve_vram_fini(adev); 2043 /* return the IP Discovery TMR memory back to VRAM */ 2044 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL); 2045 amdgpu_ttm_fw_reserve_vram_fini(adev); 2046 2047 if (adev->mman.aper_base_kaddr) 2048 iounmap(adev->mman.aper_base_kaddr); 2049 adev->mman.aper_base_kaddr = NULL; 2050 2051 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 2052 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 2053 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 2054 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 2055 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 2056 ttm_bo_device_release(&adev->mman.bdev); 2057 adev->mman.initialized = false; 2058 DRM_INFO("amdgpu: ttm finalized\n"); 2059 } 2060 2061 /** 2062 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2063 * 2064 * @adev: amdgpu_device pointer 2065 * @enable: true when we can use buffer functions. 2066 * 2067 * Enable/disable use of buffer functions during suspend/resume. This should 2068 * only be called at bootup or when userspace isn't running. 2069 */ 2070 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2071 { 2072 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM]; 2073 uint64_t size; 2074 int r; 2075 2076 if (!adev->mman.initialized || adev->in_gpu_reset || 2077 adev->mman.buffer_funcs_enabled == enable) 2078 return; 2079 2080 if (enable) { 2081 struct amdgpu_ring *ring; 2082 struct drm_gpu_scheduler *sched; 2083 2084 ring = adev->mman.buffer_funcs_ring; 2085 sched = &ring->sched; 2086 r = drm_sched_entity_init(&adev->mman.entity, 2087 DRM_SCHED_PRIORITY_KERNEL, &sched, 2088 1, NULL); 2089 if (r) { 2090 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2091 r); 2092 return; 2093 } 2094 } else { 2095 drm_sched_entity_destroy(&adev->mman.entity); 2096 dma_fence_put(man->move); 2097 man->move = NULL; 2098 } 2099 2100 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2101 if (enable) 2102 size = adev->gmc.real_vram_size; 2103 else 2104 size = adev->gmc.visible_vram_size; 2105 man->size = size >> PAGE_SHIFT; 2106 adev->mman.buffer_funcs_enabled = enable; 2107 } 2108 2109 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 2110 { 2111 struct drm_file *file_priv = filp->private_data; 2112 struct amdgpu_device *adev = file_priv->minor->dev->dev_private; 2113 2114 if (adev == NULL) 2115 return -EINVAL; 2116 2117 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 2118 } 2119 2120 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2121 uint64_t dst_offset, uint32_t byte_count, 2122 struct dma_resv *resv, 2123 struct dma_fence **fence, bool direct_submit, 2124 bool vm_needs_flush, bool tmz) 2125 { 2126 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 2127 AMDGPU_IB_POOL_DELAYED; 2128 struct amdgpu_device *adev = ring->adev; 2129 struct amdgpu_job *job; 2130 2131 uint32_t max_bytes; 2132 unsigned num_loops, num_dw; 2133 unsigned i; 2134 int r; 2135 2136 if (direct_submit && !ring->sched.ready) { 2137 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2138 return -EINVAL; 2139 } 2140 2141 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2142 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2143 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2144 2145 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 2146 if (r) 2147 return r; 2148 2149 if (vm_needs_flush) { 2150 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 2151 job->vm_needs_flush = true; 2152 } 2153 if (resv) { 2154 r = amdgpu_sync_resv(adev, &job->sync, resv, 2155 AMDGPU_SYNC_ALWAYS, 2156 AMDGPU_FENCE_OWNER_UNDEFINED); 2157 if (r) { 2158 DRM_ERROR("sync failed (%d).\n", r); 2159 goto error_free; 2160 } 2161 } 2162 2163 for (i = 0; i < num_loops; i++) { 2164 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2165 2166 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2167 dst_offset, cur_size_in_bytes, tmz); 2168 2169 src_offset += cur_size_in_bytes; 2170 dst_offset += cur_size_in_bytes; 2171 byte_count -= cur_size_in_bytes; 2172 } 2173 2174 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2175 WARN_ON(job->ibs[0].length_dw > num_dw); 2176 if (direct_submit) 2177 r = amdgpu_job_submit_direct(job, ring, fence); 2178 else 2179 r = amdgpu_job_submit(job, &adev->mman.entity, 2180 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2181 if (r) 2182 goto error_free; 2183 2184 return r; 2185 2186 error_free: 2187 amdgpu_job_free(job); 2188 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2189 return r; 2190 } 2191 2192 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2193 uint32_t src_data, 2194 struct dma_resv *resv, 2195 struct dma_fence **fence) 2196 { 2197 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2198 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2199 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2200 2201 struct drm_mm_node *mm_node; 2202 unsigned long num_pages; 2203 unsigned int num_loops, num_dw; 2204 2205 struct amdgpu_job *job; 2206 int r; 2207 2208 if (!adev->mman.buffer_funcs_enabled) { 2209 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2210 return -EINVAL; 2211 } 2212 2213 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2214 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2215 if (r) 2216 return r; 2217 } 2218 2219 num_pages = bo->tbo.num_pages; 2220 mm_node = bo->tbo.mem.mm_node; 2221 num_loops = 0; 2222 while (num_pages) { 2223 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2224 2225 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); 2226 num_pages -= mm_node->size; 2227 ++mm_node; 2228 } 2229 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2230 2231 /* for IB padding */ 2232 num_dw += 64; 2233 2234 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2235 &job); 2236 if (r) 2237 return r; 2238 2239 if (resv) { 2240 r = amdgpu_sync_resv(adev, &job->sync, resv, 2241 AMDGPU_SYNC_ALWAYS, 2242 AMDGPU_FENCE_OWNER_UNDEFINED); 2243 if (r) { 2244 DRM_ERROR("sync failed (%d).\n", r); 2245 goto error_free; 2246 } 2247 } 2248 2249 num_pages = bo->tbo.num_pages; 2250 mm_node = bo->tbo.mem.mm_node; 2251 2252 while (num_pages) { 2253 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2254 uint64_t dst_addr; 2255 2256 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); 2257 while (byte_count) { 2258 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, 2259 max_bytes); 2260 2261 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 2262 dst_addr, cur_size_in_bytes); 2263 2264 dst_addr += cur_size_in_bytes; 2265 byte_count -= cur_size_in_bytes; 2266 } 2267 2268 num_pages -= mm_node->size; 2269 ++mm_node; 2270 } 2271 2272 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2273 WARN_ON(job->ibs[0].length_dw > num_dw); 2274 r = amdgpu_job_submit(job, &adev->mman.entity, 2275 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2276 if (r) 2277 goto error_free; 2278 2279 return 0; 2280 2281 error_free: 2282 amdgpu_job_free(job); 2283 return r; 2284 } 2285 2286 #if defined(CONFIG_DEBUG_FS) 2287 2288 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 2289 { 2290 struct drm_info_node *node = (struct drm_info_node *)m->private; 2291 unsigned ttm_pl = (uintptr_t)node->info_ent->data; 2292 struct drm_device *dev = node->minor->dev; 2293 struct amdgpu_device *adev = dev->dev_private; 2294 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl]; 2295 struct drm_printer p = drm_seq_file_printer(m); 2296 2297 man->func->debug(man, &p); 2298 return 0; 2299 } 2300 2301 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 2302 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, 2303 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, 2304 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, 2305 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, 2306 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, 2307 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 2308 #ifdef CONFIG_SWIOTLB 2309 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 2310 #endif 2311 }; 2312 2313 /** 2314 * amdgpu_ttm_vram_read - Linear read access to VRAM 2315 * 2316 * Accesses VRAM via MMIO for debugging purposes. 2317 */ 2318 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2319 size_t size, loff_t *pos) 2320 { 2321 struct amdgpu_device *adev = file_inode(f)->i_private; 2322 ssize_t result = 0; 2323 2324 if (size & 0x3 || *pos & 0x3) 2325 return -EINVAL; 2326 2327 if (*pos >= adev->gmc.mc_vram_size) 2328 return -ENXIO; 2329 2330 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2331 while (size) { 2332 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2333 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2334 2335 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2336 if (copy_to_user(buf, value, bytes)) 2337 return -EFAULT; 2338 2339 result += bytes; 2340 buf += bytes; 2341 *pos += bytes; 2342 size -= bytes; 2343 } 2344 2345 return result; 2346 } 2347 2348 /** 2349 * amdgpu_ttm_vram_write - Linear write access to VRAM 2350 * 2351 * Accesses VRAM via MMIO for debugging purposes. 2352 */ 2353 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2354 size_t size, loff_t *pos) 2355 { 2356 struct amdgpu_device *adev = file_inode(f)->i_private; 2357 ssize_t result = 0; 2358 int r; 2359 2360 if (size & 0x3 || *pos & 0x3) 2361 return -EINVAL; 2362 2363 if (*pos >= adev->gmc.mc_vram_size) 2364 return -ENXIO; 2365 2366 while (size) { 2367 unsigned long flags; 2368 uint32_t value; 2369 2370 if (*pos >= adev->gmc.mc_vram_size) 2371 return result; 2372 2373 r = get_user(value, (uint32_t *)buf); 2374 if (r) 2375 return r; 2376 2377 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2378 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2379 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2380 WREG32_NO_KIQ(mmMM_DATA, value); 2381 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2382 2383 result += 4; 2384 buf += 4; 2385 *pos += 4; 2386 size -= 4; 2387 } 2388 2389 return result; 2390 } 2391 2392 static const struct file_operations amdgpu_ttm_vram_fops = { 2393 .owner = THIS_MODULE, 2394 .read = amdgpu_ttm_vram_read, 2395 .write = amdgpu_ttm_vram_write, 2396 .llseek = default_llseek, 2397 }; 2398 2399 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2400 2401 /** 2402 * amdgpu_ttm_gtt_read - Linear read access to GTT memory 2403 */ 2404 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 2405 size_t size, loff_t *pos) 2406 { 2407 struct amdgpu_device *adev = file_inode(f)->i_private; 2408 ssize_t result = 0; 2409 int r; 2410 2411 while (size) { 2412 loff_t p = *pos / PAGE_SIZE; 2413 unsigned off = *pos & ~PAGE_MASK; 2414 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 2415 struct page *page; 2416 void *ptr; 2417 2418 if (p >= adev->gart.num_cpu_pages) 2419 return result; 2420 2421 page = adev->gart.pages[p]; 2422 if (page) { 2423 ptr = kmap(page); 2424 ptr += off; 2425 2426 r = copy_to_user(buf, ptr, cur_size); 2427 kunmap(adev->gart.pages[p]); 2428 } else 2429 r = clear_user(buf, cur_size); 2430 2431 if (r) 2432 return -EFAULT; 2433 2434 result += cur_size; 2435 buf += cur_size; 2436 *pos += cur_size; 2437 size -= cur_size; 2438 } 2439 2440 return result; 2441 } 2442 2443 static const struct file_operations amdgpu_ttm_gtt_fops = { 2444 .owner = THIS_MODULE, 2445 .read = amdgpu_ttm_gtt_read, 2446 .llseek = default_llseek 2447 }; 2448 2449 #endif 2450 2451 /** 2452 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2453 * 2454 * This function is used to read memory that has been mapped to the 2455 * GPU and the known addresses are not physical addresses but instead 2456 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2457 */ 2458 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2459 size_t size, loff_t *pos) 2460 { 2461 struct amdgpu_device *adev = file_inode(f)->i_private; 2462 struct iommu_domain *dom; 2463 ssize_t result = 0; 2464 int r; 2465 2466 /* retrieve the IOMMU domain if any for this device */ 2467 dom = iommu_get_domain_for_dev(adev->dev); 2468 2469 while (size) { 2470 phys_addr_t addr = *pos & PAGE_MASK; 2471 loff_t off = *pos & ~PAGE_MASK; 2472 size_t bytes = PAGE_SIZE - off; 2473 unsigned long pfn; 2474 struct page *p; 2475 void *ptr; 2476 2477 bytes = bytes < size ? bytes : size; 2478 2479 /* Translate the bus address to a physical address. If 2480 * the domain is NULL it means there is no IOMMU active 2481 * and the address translation is the identity 2482 */ 2483 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2484 2485 pfn = addr >> PAGE_SHIFT; 2486 if (!pfn_valid(pfn)) 2487 return -EPERM; 2488 2489 p = pfn_to_page(pfn); 2490 if (p->mapping != adev->mman.bdev.dev_mapping) 2491 return -EPERM; 2492 2493 ptr = kmap(p); 2494 r = copy_to_user(buf, ptr + off, bytes); 2495 kunmap(p); 2496 if (r) 2497 return -EFAULT; 2498 2499 size -= bytes; 2500 *pos += bytes; 2501 result += bytes; 2502 } 2503 2504 return result; 2505 } 2506 2507 /** 2508 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2509 * 2510 * This function is used to write memory that has been mapped to the 2511 * GPU and the known addresses are not physical addresses but instead 2512 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2513 */ 2514 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2515 size_t size, loff_t *pos) 2516 { 2517 struct amdgpu_device *adev = file_inode(f)->i_private; 2518 struct iommu_domain *dom; 2519 ssize_t result = 0; 2520 int r; 2521 2522 dom = iommu_get_domain_for_dev(adev->dev); 2523 2524 while (size) { 2525 phys_addr_t addr = *pos & PAGE_MASK; 2526 loff_t off = *pos & ~PAGE_MASK; 2527 size_t bytes = PAGE_SIZE - off; 2528 unsigned long pfn; 2529 struct page *p; 2530 void *ptr; 2531 2532 bytes = bytes < size ? bytes : size; 2533 2534 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2535 2536 pfn = addr >> PAGE_SHIFT; 2537 if (!pfn_valid(pfn)) 2538 return -EPERM; 2539 2540 p = pfn_to_page(pfn); 2541 if (p->mapping != adev->mman.bdev.dev_mapping) 2542 return -EPERM; 2543 2544 ptr = kmap(p); 2545 r = copy_from_user(ptr + off, buf, bytes); 2546 kunmap(p); 2547 if (r) 2548 return -EFAULT; 2549 2550 size -= bytes; 2551 *pos += bytes; 2552 result += bytes; 2553 } 2554 2555 return result; 2556 } 2557 2558 static const struct file_operations amdgpu_ttm_iomem_fops = { 2559 .owner = THIS_MODULE, 2560 .read = amdgpu_iomem_read, 2561 .write = amdgpu_iomem_write, 2562 .llseek = default_llseek 2563 }; 2564 2565 static const struct { 2566 char *name; 2567 const struct file_operations *fops; 2568 int domain; 2569 } ttm_debugfs_entries[] = { 2570 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, 2571 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2572 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, 2573 #endif 2574 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, 2575 }; 2576 2577 #endif 2578 2579 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2580 { 2581 #if defined(CONFIG_DEBUG_FS) 2582 unsigned count; 2583 2584 struct drm_minor *minor = adev->ddev->primary; 2585 struct dentry *ent, *root = minor->debugfs_root; 2586 2587 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { 2588 ent = debugfs_create_file( 2589 ttm_debugfs_entries[count].name, 2590 S_IFREG | S_IRUGO, root, 2591 adev, 2592 ttm_debugfs_entries[count].fops); 2593 if (IS_ERR(ent)) 2594 return PTR_ERR(ent); 2595 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) 2596 i_size_write(ent->d_inode, adev->gmc.mc_vram_size); 2597 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) 2598 i_size_write(ent->d_inode, adev->gmc.gart_size); 2599 adev->mman.debugfs_entries[count] = ent; 2600 } 2601 2602 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 2603 2604 #ifdef CONFIG_SWIOTLB 2605 if (!(adev->need_swiotlb && swiotlb_nr_tbl())) 2606 --count; 2607 #endif 2608 2609 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 2610 #else 2611 return 0; 2612 #endif 2613 } 2614