1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/pagemap.h>
36 #include <linux/sched/task.h>
37 #include <linux/sched/mm.h>
38 #include <linux/seq_file.h>
39 #include <linux/slab.h>
40 #include <linux/swap.h>
41 #include <linux/swiotlb.h>
42 #include <linux/dma-buf.h>
43 #include <linux/sizes.h>
44 #include <linux/module.h>
45 
46 #include <drm/drm_drv.h>
47 #include <drm/ttm/ttm_bo.h>
48 #include <drm/ttm/ttm_placement.h>
49 #include <drm/ttm/ttm_range_manager.h>
50 #include <drm/ttm/ttm_tt.h>
51 
52 #include <drm/amdgpu_drm.h>
53 #include <drm/drm_drv.h>
54 
55 #include "amdgpu.h"
56 #include "amdgpu_object.h"
57 #include "amdgpu_trace.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_sdma.h"
60 #include "amdgpu_ras.h"
61 #include "amdgpu_hmm.h"
62 #include "amdgpu_atomfirmware.h"
63 #include "amdgpu_res_cursor.h"
64 #include "bif/bif_4_1_d.h"
65 
66 MODULE_IMPORT_NS(DMA_BUF);
67 
68 #define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128
69 
70 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
71 				   struct ttm_tt *ttm,
72 				   struct ttm_resource *bo_mem);
73 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
74 				      struct ttm_tt *ttm);
75 
76 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
77 				    unsigned int type,
78 				    uint64_t size_in_page)
79 {
80 	return ttm_range_man_init(&adev->mman.bdev, type,
81 				  false, size_in_page);
82 }
83 
84 /**
85  * amdgpu_evict_flags - Compute placement flags
86  *
87  * @bo: The buffer object to evict
88  * @placement: Possible destination(s) for evicted BO
89  *
90  * Fill in placement data when ttm_bo_evict() is called
91  */
92 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
93 				struct ttm_placement *placement)
94 {
95 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
96 	struct amdgpu_bo *abo;
97 	static const struct ttm_place placements = {
98 		.fpfn = 0,
99 		.lpfn = 0,
100 		.mem_type = TTM_PL_SYSTEM,
101 		.flags = 0
102 	};
103 
104 	/* Don't handle scatter gather BOs */
105 	if (bo->type == ttm_bo_type_sg) {
106 		placement->num_placement = 0;
107 		placement->num_busy_placement = 0;
108 		return;
109 	}
110 
111 	/* Object isn't an AMDGPU object so ignore */
112 	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
113 		placement->placement = &placements;
114 		placement->busy_placement = &placements;
115 		placement->num_placement = 1;
116 		placement->num_busy_placement = 1;
117 		return;
118 	}
119 
120 	abo = ttm_to_amdgpu_bo(bo);
121 	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
122 		placement->num_placement = 0;
123 		placement->num_busy_placement = 0;
124 		return;
125 	}
126 
127 	switch (bo->resource->mem_type) {
128 	case AMDGPU_PL_GDS:
129 	case AMDGPU_PL_GWS:
130 	case AMDGPU_PL_OA:
131 		placement->num_placement = 0;
132 		placement->num_busy_placement = 0;
133 		return;
134 
135 	case TTM_PL_VRAM:
136 		if (!adev->mman.buffer_funcs_enabled) {
137 			/* Move to system memory */
138 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
139 		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
140 			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
141 			   amdgpu_bo_in_cpu_visible_vram(abo)) {
142 
143 			/* Try evicting to the CPU inaccessible part of VRAM
144 			 * first, but only set GTT as busy placement, so this
145 			 * BO will be evicted to GTT rather than causing other
146 			 * BOs to be evicted from VRAM
147 			 */
148 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
149 							AMDGPU_GEM_DOMAIN_GTT |
150 							AMDGPU_GEM_DOMAIN_CPU);
151 			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
152 			abo->placements[0].lpfn = 0;
153 			abo->placement.busy_placement = &abo->placements[1];
154 			abo->placement.num_busy_placement = 1;
155 		} else {
156 			/* Move to GTT memory */
157 			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
158 							AMDGPU_GEM_DOMAIN_CPU);
159 		}
160 		break;
161 	case TTM_PL_TT:
162 	case AMDGPU_PL_PREEMPT:
163 	default:
164 		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
165 		break;
166 	}
167 	*placement = abo->placement;
168 }
169 
170 /**
171  * amdgpu_ttm_map_buffer - Map memory into the GART windows
172  * @bo: buffer object to map
173  * @mem: memory object to map
174  * @mm_cur: range to map
175  * @window: which GART window to use
176  * @ring: DMA ring to use for the copy
177  * @tmz: if we should setup a TMZ enabled mapping
178  * @size: in number of bytes to map, out number of bytes mapped
179  * @addr: resulting address inside the MC address space
180  *
181  * Setup one of the GART windows to access a specific piece of memory or return
182  * the physical address for local memory.
183  */
184 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
185 				 struct ttm_resource *mem,
186 				 struct amdgpu_res_cursor *mm_cur,
187 				 unsigned window, struct amdgpu_ring *ring,
188 				 bool tmz, uint64_t *size, uint64_t *addr)
189 {
190 	struct amdgpu_device *adev = ring->adev;
191 	unsigned offset, num_pages, num_dw, num_bytes;
192 	uint64_t src_addr, dst_addr;
193 	struct amdgpu_job *job;
194 	void *cpu_addr;
195 	uint64_t flags;
196 	unsigned int i;
197 	int r;
198 
199 	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
200 	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
201 
202 	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
203 		return -EINVAL;
204 
205 	/* Map only what can't be accessed directly */
206 	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
207 		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
208 			mm_cur->start;
209 		return 0;
210 	}
211 
212 
213 	/*
214 	 * If start begins at an offset inside the page, then adjust the size
215 	 * and addr accordingly
216 	 */
217 	offset = mm_cur->start & ~PAGE_MASK;
218 
219 	num_pages = PFN_UP(*size + offset);
220 	num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
221 
222 	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
223 
224 	*addr = adev->gmc.gart_start;
225 	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
226 		AMDGPU_GPU_PAGE_SIZE;
227 	*addr += offset;
228 
229 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
230 	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
231 
232 	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
233 				     AMDGPU_FENCE_OWNER_UNDEFINED,
234 				     num_dw * 4 + num_bytes,
235 				     AMDGPU_IB_POOL_DELAYED, &job);
236 	if (r)
237 		return r;
238 
239 	src_addr = num_dw * 4;
240 	src_addr += job->ibs[0].gpu_addr;
241 
242 	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
243 	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
244 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
245 				dst_addr, num_bytes, false);
246 
247 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
248 	WARN_ON(job->ibs[0].length_dw > num_dw);
249 
250 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
251 	if (tmz)
252 		flags |= AMDGPU_PTE_TMZ;
253 
254 	cpu_addr = &job->ibs[0].ptr[num_dw];
255 
256 	if (mem->mem_type == TTM_PL_TT) {
257 		dma_addr_t *dma_addr;
258 
259 		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
260 		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
261 	} else {
262 		dma_addr_t dma_address;
263 
264 		dma_address = mm_cur->start;
265 		dma_address += adev->vm_manager.vram_base_offset;
266 
267 		for (i = 0; i < num_pages; ++i) {
268 			amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
269 					flags, cpu_addr);
270 			dma_address += PAGE_SIZE;
271 		}
272 	}
273 
274 	dma_fence_put(amdgpu_job_submit(job));
275 	return 0;
276 }
277 
278 /**
279  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
280  * @adev: amdgpu device
281  * @src: buffer/address where to read from
282  * @dst: buffer/address where to write to
283  * @size: number of bytes to copy
284  * @tmz: if a secure copy should be used
285  * @resv: resv object to sync to
286  * @f: Returns the last fence if multiple jobs are submitted.
287  *
288  * The function copies @size bytes from {src->mem + src->offset} to
289  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
290  * move and different for a BO to BO copy.
291  *
292  */
293 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
294 			       const struct amdgpu_copy_mem *src,
295 			       const struct amdgpu_copy_mem *dst,
296 			       uint64_t size, bool tmz,
297 			       struct dma_resv *resv,
298 			       struct dma_fence **f)
299 {
300 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
301 	struct amdgpu_res_cursor src_mm, dst_mm;
302 	struct dma_fence *fence = NULL;
303 	int r = 0;
304 
305 	if (!adev->mman.buffer_funcs_enabled) {
306 		DRM_ERROR("Trying to move memory with ring turned off.\n");
307 		return -EINVAL;
308 	}
309 
310 	amdgpu_res_first(src->mem, src->offset, size, &src_mm);
311 	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
312 
313 	mutex_lock(&adev->mman.gtt_window_lock);
314 	while (src_mm.remaining) {
315 		uint64_t from, to, cur_size;
316 		struct dma_fence *next;
317 
318 		/* Never copy more than 256MiB at once to avoid a timeout */
319 		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
320 
321 		/* Map src to window 0 and dst to window 1. */
322 		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
323 					  0, ring, tmz, &cur_size, &from);
324 		if (r)
325 			goto error;
326 
327 		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
328 					  1, ring, tmz, &cur_size, &to);
329 		if (r)
330 			goto error;
331 
332 		r = amdgpu_copy_buffer(ring, from, to, cur_size,
333 				       resv, &next, false, true, tmz);
334 		if (r)
335 			goto error;
336 
337 		dma_fence_put(fence);
338 		fence = next;
339 
340 		amdgpu_res_next(&src_mm, cur_size);
341 		amdgpu_res_next(&dst_mm, cur_size);
342 	}
343 error:
344 	mutex_unlock(&adev->mman.gtt_window_lock);
345 	if (f)
346 		*f = dma_fence_get(fence);
347 	dma_fence_put(fence);
348 	return r;
349 }
350 
351 /*
352  * amdgpu_move_blit - Copy an entire buffer to another buffer
353  *
354  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
355  * help move buffers to and from VRAM.
356  */
357 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
358 			    bool evict,
359 			    struct ttm_resource *new_mem,
360 			    struct ttm_resource *old_mem)
361 {
362 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
363 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
364 	struct amdgpu_copy_mem src, dst;
365 	struct dma_fence *fence = NULL;
366 	int r;
367 
368 	src.bo = bo;
369 	dst.bo = bo;
370 	src.mem = old_mem;
371 	dst.mem = new_mem;
372 	src.offset = 0;
373 	dst.offset = 0;
374 
375 	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
376 				       new_mem->size,
377 				       amdgpu_bo_encrypted(abo),
378 				       bo->base.resv, &fence);
379 	if (r)
380 		goto error;
381 
382 	/* clear the space being freed */
383 	if (old_mem->mem_type == TTM_PL_VRAM &&
384 	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
385 		struct dma_fence *wipe_fence = NULL;
386 
387 		r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence);
388 		if (r) {
389 			goto error;
390 		} else if (wipe_fence) {
391 			dma_fence_put(fence);
392 			fence = wipe_fence;
393 		}
394 	}
395 
396 	/* Always block for VM page tables before committing the new location */
397 	if (bo->type == ttm_bo_type_kernel)
398 		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
399 	else
400 		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
401 	dma_fence_put(fence);
402 	return r;
403 
404 error:
405 	if (fence)
406 		dma_fence_wait(fence, false);
407 	dma_fence_put(fence);
408 	return r;
409 }
410 
411 /*
412  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
413  *
414  * Called by amdgpu_bo_move()
415  */
416 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
417 			       struct ttm_resource *mem)
418 {
419 	u64 mem_size = (u64)mem->size;
420 	struct amdgpu_res_cursor cursor;
421 	u64 end;
422 
423 	if (mem->mem_type == TTM_PL_SYSTEM ||
424 	    mem->mem_type == TTM_PL_TT)
425 		return true;
426 	if (mem->mem_type != TTM_PL_VRAM)
427 		return false;
428 
429 	amdgpu_res_first(mem, 0, mem_size, &cursor);
430 	end = cursor.start + cursor.size;
431 	while (cursor.remaining) {
432 		amdgpu_res_next(&cursor, cursor.size);
433 
434 		if (!cursor.remaining)
435 			break;
436 
437 		/* ttm_resource_ioremap only supports contiguous memory */
438 		if (end != cursor.start)
439 			return false;
440 
441 		end = cursor.start + cursor.size;
442 	}
443 
444 	return end <= adev->gmc.visible_vram_size;
445 }
446 
447 /*
448  * amdgpu_bo_move - Move a buffer object to a new memory location
449  *
450  * Called by ttm_bo_handle_move_mem()
451  */
452 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
453 			  struct ttm_operation_ctx *ctx,
454 			  struct ttm_resource *new_mem,
455 			  struct ttm_place *hop)
456 {
457 	struct amdgpu_device *adev;
458 	struct amdgpu_bo *abo;
459 	struct ttm_resource *old_mem = bo->resource;
460 	int r;
461 
462 	if (new_mem->mem_type == TTM_PL_TT ||
463 	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
464 		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
465 		if (r)
466 			return r;
467 	}
468 
469 	abo = ttm_to_amdgpu_bo(bo);
470 	adev = amdgpu_ttm_adev(bo->bdev);
471 
472 	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
473 			 bo->ttm == NULL)) {
474 		ttm_bo_move_null(bo, new_mem);
475 		goto out;
476 	}
477 	if (old_mem->mem_type == TTM_PL_SYSTEM &&
478 	    (new_mem->mem_type == TTM_PL_TT ||
479 	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
480 		ttm_bo_move_null(bo, new_mem);
481 		goto out;
482 	}
483 	if ((old_mem->mem_type == TTM_PL_TT ||
484 	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
485 	    new_mem->mem_type == TTM_PL_SYSTEM) {
486 		r = ttm_bo_wait_ctx(bo, ctx);
487 		if (r)
488 			return r;
489 
490 		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
491 		ttm_resource_free(bo, &bo->resource);
492 		ttm_bo_assign_mem(bo, new_mem);
493 		goto out;
494 	}
495 
496 	if (old_mem->mem_type == AMDGPU_PL_GDS ||
497 	    old_mem->mem_type == AMDGPU_PL_GWS ||
498 	    old_mem->mem_type == AMDGPU_PL_OA ||
499 	    new_mem->mem_type == AMDGPU_PL_GDS ||
500 	    new_mem->mem_type == AMDGPU_PL_GWS ||
501 	    new_mem->mem_type == AMDGPU_PL_OA) {
502 		/* Nothing to save here */
503 		ttm_bo_move_null(bo, new_mem);
504 		goto out;
505 	}
506 
507 	if (bo->type == ttm_bo_type_device &&
508 	    new_mem->mem_type == TTM_PL_VRAM &&
509 	    old_mem->mem_type != TTM_PL_VRAM) {
510 		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
511 		 * accesses the BO after it's moved.
512 		 */
513 		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
514 	}
515 
516 	if (adev->mman.buffer_funcs_enabled) {
517 		if (((old_mem->mem_type == TTM_PL_SYSTEM &&
518 		      new_mem->mem_type == TTM_PL_VRAM) ||
519 		     (old_mem->mem_type == TTM_PL_VRAM &&
520 		      new_mem->mem_type == TTM_PL_SYSTEM))) {
521 			hop->fpfn = 0;
522 			hop->lpfn = 0;
523 			hop->mem_type = TTM_PL_TT;
524 			hop->flags = TTM_PL_FLAG_TEMPORARY;
525 			return -EMULTIHOP;
526 		}
527 
528 		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
529 	} else {
530 		r = -ENODEV;
531 	}
532 
533 	if (r) {
534 		/* Check that all memory is CPU accessible */
535 		if (!amdgpu_mem_visible(adev, old_mem) ||
536 		    !amdgpu_mem_visible(adev, new_mem)) {
537 			pr_err("Move buffer fallback to memcpy unavailable\n");
538 			return r;
539 		}
540 
541 		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
542 		if (r)
543 			return r;
544 	}
545 
546 out:
547 	/* update statistics */
548 	atomic64_add(bo->base.size, &adev->num_bytes_moved);
549 	amdgpu_bo_move_notify(bo, evict, new_mem);
550 	return 0;
551 }
552 
553 /*
554  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
555  *
556  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
557  */
558 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
559 				     struct ttm_resource *mem)
560 {
561 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
562 	size_t bus_size = (size_t)mem->size;
563 
564 	switch (mem->mem_type) {
565 	case TTM_PL_SYSTEM:
566 		/* system memory */
567 		return 0;
568 	case TTM_PL_TT:
569 	case AMDGPU_PL_PREEMPT:
570 		break;
571 	case TTM_PL_VRAM:
572 		mem->bus.offset = mem->start << PAGE_SHIFT;
573 		/* check if it's visible */
574 		if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
575 			return -EINVAL;
576 
577 		if (adev->mman.aper_base_kaddr &&
578 		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
579 			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
580 					mem->bus.offset;
581 
582 		mem->bus.offset += adev->gmc.aper_base;
583 		mem->bus.is_iomem = true;
584 		break;
585 	default:
586 		return -EINVAL;
587 	}
588 	return 0;
589 }
590 
591 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
592 					   unsigned long page_offset)
593 {
594 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
595 	struct amdgpu_res_cursor cursor;
596 
597 	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
598 			 &cursor);
599 	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
600 }
601 
602 /**
603  * amdgpu_ttm_domain_start - Returns GPU start address
604  * @adev: amdgpu device object
605  * @type: type of the memory
606  *
607  * Returns:
608  * GPU start address of a memory domain
609  */
610 
611 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
612 {
613 	switch (type) {
614 	case TTM_PL_TT:
615 		return adev->gmc.gart_start;
616 	case TTM_PL_VRAM:
617 		return adev->gmc.vram_start;
618 	}
619 
620 	return 0;
621 }
622 
623 /*
624  * TTM backend functions.
625  */
626 struct amdgpu_ttm_tt {
627 	struct ttm_tt	ttm;
628 	struct drm_gem_object	*gobj;
629 	u64			offset;
630 	uint64_t		userptr;
631 	struct task_struct	*usertask;
632 	uint32_t		userflags;
633 	bool			bound;
634 };
635 
636 #define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)
637 
638 #ifdef CONFIG_DRM_AMDGPU_USERPTR
639 /*
640  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
641  * memory and start HMM tracking CPU page table update
642  *
643  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
644  * once afterwards to stop HMM tracking
645  */
646 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
647 				 struct hmm_range **range)
648 {
649 	struct ttm_tt *ttm = bo->tbo.ttm;
650 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
651 	unsigned long start = gtt->userptr;
652 	struct vm_area_struct *vma;
653 	struct mm_struct *mm;
654 	bool readonly;
655 	int r = 0;
656 
657 	/* Make sure get_user_pages_done() can cleanup gracefully */
658 	*range = NULL;
659 
660 	mm = bo->notifier.mm;
661 	if (unlikely(!mm)) {
662 		DRM_DEBUG_DRIVER("BO is not registered?\n");
663 		return -EFAULT;
664 	}
665 
666 	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
667 		return -ESRCH;
668 
669 	mmap_read_lock(mm);
670 	vma = vma_lookup(mm, start);
671 	if (unlikely(!vma)) {
672 		r = -EFAULT;
673 		goto out_unlock;
674 	}
675 	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
676 		vma->vm_file)) {
677 		r = -EPERM;
678 		goto out_unlock;
679 	}
680 
681 	readonly = amdgpu_ttm_tt_is_readonly(ttm);
682 	r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
683 				       readonly, NULL, pages, range);
684 out_unlock:
685 	mmap_read_unlock(mm);
686 	if (r)
687 		pr_debug("failed %d to get user pages 0x%lx\n", r, start);
688 
689 	mmput(mm);
690 
691 	return r;
692 }
693 
694 /* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
695  */
696 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
697 				      struct hmm_range *range)
698 {
699 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
700 
701 	if (gtt && gtt->userptr && range)
702 		amdgpu_hmm_range_get_pages_done(range);
703 }
704 
705 /*
706  * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
707  * Check if the pages backing this ttm range have been invalidated
708  *
709  * Returns: true if pages are still valid
710  */
711 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
712 				       struct hmm_range *range)
713 {
714 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
715 
716 	if (!gtt || !gtt->userptr || !range)
717 		return false;
718 
719 	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
720 		gtt->userptr, ttm->num_pages);
721 
722 	WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
723 
724 	return !amdgpu_hmm_range_get_pages_done(range);
725 }
726 #endif
727 
728 /*
729  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
730  *
731  * Called by amdgpu_cs_list_validate(). This creates the page list
732  * that backs user memory and will ultimately be mapped into the device
733  * address space.
734  */
735 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
736 {
737 	unsigned long i;
738 
739 	for (i = 0; i < ttm->num_pages; ++i)
740 		ttm->pages[i] = pages ? pages[i] : NULL;
741 }
742 
743 /*
744  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
745  *
746  * Called by amdgpu_ttm_backend_bind()
747  **/
748 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
749 				     struct ttm_tt *ttm)
750 {
751 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
752 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
753 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
754 	enum dma_data_direction direction = write ?
755 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
756 	int r;
757 
758 	/* Allocate an SG array and squash pages into it */
759 	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
760 				      (u64)ttm->num_pages << PAGE_SHIFT,
761 				      GFP_KERNEL);
762 	if (r)
763 		goto release_sg;
764 
765 	/* Map SG to device */
766 	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
767 	if (r)
768 		goto release_sg;
769 
770 	/* convert SG to linear array of pages and dma addresses */
771 	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
772 				       ttm->num_pages);
773 
774 	return 0;
775 
776 release_sg:
777 	kfree(ttm->sg);
778 	ttm->sg = NULL;
779 	return r;
780 }
781 
782 /*
783  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
784  */
785 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
786 					struct ttm_tt *ttm)
787 {
788 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
789 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
790 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
791 	enum dma_data_direction direction = write ?
792 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
793 
794 	/* double check that we don't free the table twice */
795 	if (!ttm->sg || !ttm->sg->sgl)
796 		return;
797 
798 	/* unmap the pages mapped to the device */
799 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
800 	sg_free_table(ttm->sg);
801 }
802 
803 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
804 				 struct ttm_buffer_object *tbo,
805 				 uint64_t flags)
806 {
807 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
808 	struct ttm_tt *ttm = tbo->ttm;
809 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
810 
811 	if (amdgpu_bo_encrypted(abo))
812 		flags |= AMDGPU_PTE_TMZ;
813 
814 	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
815 		uint64_t page_idx = 1;
816 
817 		amdgpu_gart_bind(adev, gtt->offset, page_idx,
818 				 gtt->ttm.dma_address, flags);
819 
820 		/* The memory type of the first page defaults to UC. Now
821 		 * modify the memory type to NC from the second page of
822 		 * the BO onward.
823 		 */
824 		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
825 		flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
826 
827 		amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT),
828 				 ttm->num_pages - page_idx,
829 				 &(gtt->ttm.dma_address[page_idx]), flags);
830 	} else {
831 		amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
832 				 gtt->ttm.dma_address, flags);
833 	}
834 }
835 
836 /*
837  * amdgpu_ttm_backend_bind - Bind GTT memory
838  *
839  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
840  * This handles binding GTT memory to the device address space.
841  */
842 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
843 				   struct ttm_tt *ttm,
844 				   struct ttm_resource *bo_mem)
845 {
846 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
847 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
848 	uint64_t flags;
849 	int r;
850 
851 	if (!bo_mem)
852 		return -EINVAL;
853 
854 	if (gtt->bound)
855 		return 0;
856 
857 	if (gtt->userptr) {
858 		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
859 		if (r) {
860 			DRM_ERROR("failed to pin userptr\n");
861 			return r;
862 		}
863 	} else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
864 		if (!ttm->sg) {
865 			struct dma_buf_attachment *attach;
866 			struct sg_table *sgt;
867 
868 			attach = gtt->gobj->import_attach;
869 			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
870 			if (IS_ERR(sgt))
871 				return PTR_ERR(sgt);
872 
873 			ttm->sg = sgt;
874 		}
875 
876 		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
877 					       ttm->num_pages);
878 	}
879 
880 	if (!ttm->num_pages) {
881 		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
882 		     ttm->num_pages, bo_mem, ttm);
883 	}
884 
885 	if (bo_mem->mem_type != TTM_PL_TT ||
886 	    !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
887 		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
888 		return 0;
889 	}
890 
891 	/* compute PTE flags relevant to this BO memory */
892 	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
893 
894 	/* bind pages into GART page tables */
895 	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
896 	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
897 			 gtt->ttm.dma_address, flags);
898 	gtt->bound = true;
899 	return 0;
900 }
901 
902 /*
903  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
904  * through AGP or GART aperture.
905  *
906  * If bo is accessible through AGP aperture, then use AGP aperture
907  * to access bo; otherwise allocate logical space in GART aperture
908  * and map bo to GART aperture.
909  */
910 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
911 {
912 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
913 	struct ttm_operation_ctx ctx = { false, false };
914 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
915 	struct ttm_placement placement;
916 	struct ttm_place placements;
917 	struct ttm_resource *tmp;
918 	uint64_t addr, flags;
919 	int r;
920 
921 	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
922 		return 0;
923 
924 	addr = amdgpu_gmc_agp_addr(bo);
925 	if (addr != AMDGPU_BO_INVALID_OFFSET) {
926 		bo->resource->start = addr >> PAGE_SHIFT;
927 		return 0;
928 	}
929 
930 	/* allocate GART space */
931 	placement.num_placement = 1;
932 	placement.placement = &placements;
933 	placement.num_busy_placement = 1;
934 	placement.busy_placement = &placements;
935 	placements.fpfn = 0;
936 	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
937 	placements.mem_type = TTM_PL_TT;
938 	placements.flags = bo->resource->placement;
939 
940 	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
941 	if (unlikely(r))
942 		return r;
943 
944 	/* compute PTE flags for this buffer object */
945 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
946 
947 	/* Bind pages */
948 	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
949 	amdgpu_ttm_gart_bind(adev, bo, flags);
950 	amdgpu_gart_invalidate_tlb(adev);
951 	ttm_resource_free(bo, &bo->resource);
952 	ttm_bo_assign_mem(bo, tmp);
953 
954 	return 0;
955 }
956 
957 /*
958  * amdgpu_ttm_recover_gart - Rebind GTT pages
959  *
960  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
961  * rebind GTT pages during a GPU reset.
962  */
963 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
964 {
965 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
966 	uint64_t flags;
967 
968 	if (!tbo->ttm)
969 		return;
970 
971 	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
972 	amdgpu_ttm_gart_bind(adev, tbo, flags);
973 }
974 
975 /*
976  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
977  *
978  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
979  * ttm_tt_destroy().
980  */
981 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
982 				      struct ttm_tt *ttm)
983 {
984 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
985 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
986 
987 	/* if the pages have userptr pinning then clear that first */
988 	if (gtt->userptr) {
989 		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
990 	} else if (ttm->sg && gtt->gobj->import_attach) {
991 		struct dma_buf_attachment *attach;
992 
993 		attach = gtt->gobj->import_attach;
994 		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
995 		ttm->sg = NULL;
996 	}
997 
998 	if (!gtt->bound)
999 		return;
1000 
1001 	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1002 		return;
1003 
1004 	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1005 	amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1006 	gtt->bound = false;
1007 }
1008 
1009 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1010 				       struct ttm_tt *ttm)
1011 {
1012 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1013 
1014 	if (gtt->usertask)
1015 		put_task_struct(gtt->usertask);
1016 
1017 	ttm_tt_fini(&gtt->ttm);
1018 	kfree(gtt);
1019 }
1020 
1021 /**
1022  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1023  *
1024  * @bo: The buffer object to create a GTT ttm_tt object around
1025  * @page_flags: Page flags to be added to the ttm_tt object
1026  *
1027  * Called by ttm_tt_create().
1028  */
1029 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1030 					   uint32_t page_flags)
1031 {
1032 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1033 	struct amdgpu_ttm_tt *gtt;
1034 	enum ttm_caching caching;
1035 
1036 	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1037 	if (gtt == NULL) {
1038 		return NULL;
1039 	}
1040 	gtt->gobj = &bo->base;
1041 
1042 	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1043 		caching = ttm_write_combined;
1044 	else
1045 		caching = ttm_cached;
1046 
1047 	/* allocate space for the uninitialized page entries */
1048 	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1049 		kfree(gtt);
1050 		return NULL;
1051 	}
1052 	return &gtt->ttm;
1053 }
1054 
1055 /*
1056  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1057  *
1058  * Map the pages of a ttm_tt object to an address space visible
1059  * to the underlying device.
1060  */
1061 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1062 				  struct ttm_tt *ttm,
1063 				  struct ttm_operation_ctx *ctx)
1064 {
1065 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1066 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1067 	pgoff_t i;
1068 	int ret;
1069 
1070 	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1071 	if (gtt->userptr) {
1072 		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1073 		if (!ttm->sg)
1074 			return -ENOMEM;
1075 		return 0;
1076 	}
1077 
1078 	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1079 		return 0;
1080 
1081 	ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1082 	if (ret)
1083 		return ret;
1084 
1085 	for (i = 0; i < ttm->num_pages; ++i)
1086 		ttm->pages[i]->mapping = bdev->dev_mapping;
1087 
1088 	return 0;
1089 }
1090 
1091 /*
1092  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1093  *
1094  * Unmaps pages of a ttm_tt object from the device address space and
1095  * unpopulates the page array backing it.
1096  */
1097 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1098 				     struct ttm_tt *ttm)
1099 {
1100 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1101 	struct amdgpu_device *adev;
1102 	pgoff_t i;
1103 
1104 	amdgpu_ttm_backend_unbind(bdev, ttm);
1105 
1106 	if (gtt->userptr) {
1107 		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1108 		kfree(ttm->sg);
1109 		ttm->sg = NULL;
1110 		return;
1111 	}
1112 
1113 	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1114 		return;
1115 
1116 	for (i = 0; i < ttm->num_pages; ++i)
1117 		ttm->pages[i]->mapping = NULL;
1118 
1119 	adev = amdgpu_ttm_adev(bdev);
1120 	return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1121 }
1122 
1123 /**
1124  * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1125  * task
1126  *
1127  * @tbo: The ttm_buffer_object that contains the userptr
1128  * @user_addr:  The returned value
1129  */
1130 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1131 			      uint64_t *user_addr)
1132 {
1133 	struct amdgpu_ttm_tt *gtt;
1134 
1135 	if (!tbo->ttm)
1136 		return -EINVAL;
1137 
1138 	gtt = (void *)tbo->ttm;
1139 	*user_addr = gtt->userptr;
1140 	return 0;
1141 }
1142 
1143 /**
1144  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1145  * task
1146  *
1147  * @bo: The ttm_buffer_object to bind this userptr to
1148  * @addr:  The address in the current tasks VM space to use
1149  * @flags: Requirements of userptr object.
1150  *
1151  * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1152  * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1153  * initialize GPU VM for a KFD process.
1154  */
1155 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1156 			      uint64_t addr, uint32_t flags)
1157 {
1158 	struct amdgpu_ttm_tt *gtt;
1159 
1160 	if (!bo->ttm) {
1161 		/* TODO: We want a separate TTM object type for userptrs */
1162 		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1163 		if (bo->ttm == NULL)
1164 			return -ENOMEM;
1165 	}
1166 
1167 	/* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1168 	bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1169 
1170 	gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1171 	gtt->userptr = addr;
1172 	gtt->userflags = flags;
1173 
1174 	if (gtt->usertask)
1175 		put_task_struct(gtt->usertask);
1176 	gtt->usertask = current->group_leader;
1177 	get_task_struct(gtt->usertask);
1178 
1179 	return 0;
1180 }
1181 
1182 /*
1183  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1184  */
1185 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1186 {
1187 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1188 
1189 	if (gtt == NULL)
1190 		return NULL;
1191 
1192 	if (gtt->usertask == NULL)
1193 		return NULL;
1194 
1195 	return gtt->usertask->mm;
1196 }
1197 
1198 /*
1199  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1200  * address range for the current task.
1201  *
1202  */
1203 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1204 				  unsigned long end, unsigned long *userptr)
1205 {
1206 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1207 	unsigned long size;
1208 
1209 	if (gtt == NULL || !gtt->userptr)
1210 		return false;
1211 
1212 	/* Return false if no part of the ttm_tt object lies within
1213 	 * the range
1214 	 */
1215 	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1216 	if (gtt->userptr > end || gtt->userptr + size <= start)
1217 		return false;
1218 
1219 	if (userptr)
1220 		*userptr = gtt->userptr;
1221 	return true;
1222 }
1223 
1224 /*
1225  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1226  */
1227 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1228 {
1229 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1230 
1231 	if (gtt == NULL || !gtt->userptr)
1232 		return false;
1233 
1234 	return true;
1235 }
1236 
1237 /*
1238  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1239  */
1240 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1241 {
1242 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1243 
1244 	if (gtt == NULL)
1245 		return false;
1246 
1247 	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1248 }
1249 
1250 /**
1251  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1252  *
1253  * @ttm: The ttm_tt object to compute the flags for
1254  * @mem: The memory registry backing this ttm_tt object
1255  *
1256  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1257  */
1258 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1259 {
1260 	uint64_t flags = 0;
1261 
1262 	if (mem && mem->mem_type != TTM_PL_SYSTEM)
1263 		flags |= AMDGPU_PTE_VALID;
1264 
1265 	if (mem && (mem->mem_type == TTM_PL_TT ||
1266 		    mem->mem_type == AMDGPU_PL_PREEMPT)) {
1267 		flags |= AMDGPU_PTE_SYSTEM;
1268 
1269 		if (ttm->caching == ttm_cached)
1270 			flags |= AMDGPU_PTE_SNOOPED;
1271 	}
1272 
1273 	if (mem && mem->mem_type == TTM_PL_VRAM &&
1274 			mem->bus.caching == ttm_cached)
1275 		flags |= AMDGPU_PTE_SNOOPED;
1276 
1277 	return flags;
1278 }
1279 
1280 /**
1281  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1282  *
1283  * @adev: amdgpu_device pointer
1284  * @ttm: The ttm_tt object to compute the flags for
1285  * @mem: The memory registry backing this ttm_tt object
1286  *
1287  * Figure out the flags to use for a VM PTE (Page Table Entry).
1288  */
1289 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1290 				 struct ttm_resource *mem)
1291 {
1292 	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1293 
1294 	flags |= adev->gart.gart_pte_flags;
1295 	flags |= AMDGPU_PTE_READABLE;
1296 
1297 	if (!amdgpu_ttm_tt_is_readonly(ttm))
1298 		flags |= AMDGPU_PTE_WRITEABLE;
1299 
1300 	return flags;
1301 }
1302 
1303 /*
1304  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1305  * object.
1306  *
1307  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1308  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1309  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1310  * used to clean out a memory space.
1311  */
1312 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1313 					    const struct ttm_place *place)
1314 {
1315 	struct dma_resv_iter resv_cursor;
1316 	struct dma_fence *f;
1317 
1318 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1319 		return ttm_bo_eviction_valuable(bo, place);
1320 
1321 	/* Swapout? */
1322 	if (bo->resource->mem_type == TTM_PL_SYSTEM)
1323 		return true;
1324 
1325 	if (bo->type == ttm_bo_type_kernel &&
1326 	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1327 		return false;
1328 
1329 	/* If bo is a KFD BO, check if the bo belongs to the current process.
1330 	 * If true, then return false as any KFD process needs all its BOs to
1331 	 * be resident to run successfully
1332 	 */
1333 	dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1334 				DMA_RESV_USAGE_BOOKKEEP, f) {
1335 		if (amdkfd_fence_check_mm(f, current->mm))
1336 			return false;
1337 	}
1338 
1339 	/* Preemptible BOs don't own system resources managed by the
1340 	 * driver (pages, VRAM, GART space). They point to resources
1341 	 * owned by someone else (e.g. pageable memory in user mode
1342 	 * or a DMABuf). They are used in a preemptible context so we
1343 	 * can guarantee no deadlocks and good QoS in case of MMU
1344 	 * notifiers or DMABuf move notifiers from the resource owner.
1345 	 */
1346 	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1347 		return false;
1348 
1349 	if (bo->resource->mem_type == TTM_PL_TT &&
1350 	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1351 		return false;
1352 
1353 	return ttm_bo_eviction_valuable(bo, place);
1354 }
1355 
1356 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1357 				      void *buf, size_t size, bool write)
1358 {
1359 	while (size) {
1360 		uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1361 		uint64_t bytes = 4 - (pos & 0x3);
1362 		uint32_t shift = (pos & 0x3) * 8;
1363 		uint32_t mask = 0xffffffff << shift;
1364 		uint32_t value = 0;
1365 
1366 		if (size < bytes) {
1367 			mask &= 0xffffffff >> (bytes - size) * 8;
1368 			bytes = size;
1369 		}
1370 
1371 		if (mask != 0xffffffff) {
1372 			amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1373 			if (write) {
1374 				value &= ~mask;
1375 				value |= (*(uint32_t *)buf << shift) & mask;
1376 				amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1377 			} else {
1378 				value = (value & mask) >> shift;
1379 				memcpy(buf, &value, bytes);
1380 			}
1381 		} else {
1382 			amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1383 		}
1384 
1385 		pos += bytes;
1386 		buf += bytes;
1387 		size -= bytes;
1388 	}
1389 }
1390 
1391 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1392 					unsigned long offset, void *buf,
1393 					int len, int write)
1394 {
1395 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1396 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1397 	struct amdgpu_res_cursor src_mm;
1398 	struct amdgpu_job *job;
1399 	struct dma_fence *fence;
1400 	uint64_t src_addr, dst_addr;
1401 	unsigned int num_dw;
1402 	int r, idx;
1403 
1404 	if (len != PAGE_SIZE)
1405 		return -EINVAL;
1406 
1407 	if (!adev->mman.sdma_access_ptr)
1408 		return -EACCES;
1409 
1410 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1411 		return -ENODEV;
1412 
1413 	if (write)
1414 		memcpy(adev->mman.sdma_access_ptr, buf, len);
1415 
1416 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1417 	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
1418 				     AMDGPU_FENCE_OWNER_UNDEFINED,
1419 				     num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1420 				     &job);
1421 	if (r)
1422 		goto out;
1423 
1424 	amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1425 	src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1426 		src_mm.start;
1427 	dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1428 	if (write)
1429 		swap(src_addr, dst_addr);
1430 
1431 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1432 				PAGE_SIZE, false);
1433 
1434 	amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1435 	WARN_ON(job->ibs[0].length_dw > num_dw);
1436 
1437 	fence = amdgpu_job_submit(job);
1438 
1439 	if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1440 		r = -ETIMEDOUT;
1441 	dma_fence_put(fence);
1442 
1443 	if (!(r || write))
1444 		memcpy(buf, adev->mman.sdma_access_ptr, len);
1445 out:
1446 	drm_dev_exit(idx);
1447 	return r;
1448 }
1449 
1450 /**
1451  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1452  *
1453  * @bo:  The buffer object to read/write
1454  * @offset:  Offset into buffer object
1455  * @buf:  Secondary buffer to write/read from
1456  * @len: Length in bytes of access
1457  * @write:  true if writing
1458  *
1459  * This is used to access VRAM that backs a buffer object via MMIO
1460  * access for debugging purposes.
1461  */
1462 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1463 				    unsigned long offset, void *buf, int len,
1464 				    int write)
1465 {
1466 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1467 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1468 	struct amdgpu_res_cursor cursor;
1469 	int ret = 0;
1470 
1471 	if (bo->resource->mem_type != TTM_PL_VRAM)
1472 		return -EIO;
1473 
1474 	if (amdgpu_device_has_timeouts_enabled(adev) &&
1475 			!amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1476 		return len;
1477 
1478 	amdgpu_res_first(bo->resource, offset, len, &cursor);
1479 	while (cursor.remaining) {
1480 		size_t count, size = cursor.size;
1481 		loff_t pos = cursor.start;
1482 
1483 		count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1484 		size -= count;
1485 		if (size) {
1486 			/* using MM to access rest vram and handle un-aligned address */
1487 			pos += count;
1488 			buf += count;
1489 			amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1490 		}
1491 
1492 		ret += cursor.size;
1493 		buf += cursor.size;
1494 		amdgpu_res_next(&cursor, cursor.size);
1495 	}
1496 
1497 	return ret;
1498 }
1499 
1500 static void
1501 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1502 {
1503 	amdgpu_bo_move_notify(bo, false, NULL);
1504 }
1505 
1506 static struct ttm_device_funcs amdgpu_bo_driver = {
1507 	.ttm_tt_create = &amdgpu_ttm_tt_create,
1508 	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
1509 	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1510 	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1511 	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1512 	.evict_flags = &amdgpu_evict_flags,
1513 	.move = &amdgpu_bo_move,
1514 	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1515 	.release_notify = &amdgpu_bo_release_notify,
1516 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1517 	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1518 	.access_memory = &amdgpu_ttm_access_memory,
1519 };
1520 
1521 /*
1522  * Firmware Reservation functions
1523  */
1524 /**
1525  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1526  *
1527  * @adev: amdgpu_device pointer
1528  *
1529  * free fw reserved vram if it has been reserved.
1530  */
1531 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1532 {
1533 	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1534 		NULL, &adev->mman.fw_vram_usage_va);
1535 }
1536 
1537 /*
1538  * Driver Reservation functions
1539  */
1540 /**
1541  * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1542  *
1543  * @adev: amdgpu_device pointer
1544  *
1545  * free drv reserved vram if it has been reserved.
1546  */
1547 static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1548 {
1549 	amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1550 						  NULL,
1551 						  &adev->mman.drv_vram_usage_va);
1552 }
1553 
1554 /**
1555  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1556  *
1557  * @adev: amdgpu_device pointer
1558  *
1559  * create bo vram reservation from fw.
1560  */
1561 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1562 {
1563 	uint64_t vram_size = adev->gmc.visible_vram_size;
1564 
1565 	adev->mman.fw_vram_usage_va = NULL;
1566 	adev->mman.fw_vram_usage_reserved_bo = NULL;
1567 
1568 	if (adev->mman.fw_vram_usage_size == 0 ||
1569 	    adev->mman.fw_vram_usage_size > vram_size)
1570 		return 0;
1571 
1572 	return amdgpu_bo_create_kernel_at(adev,
1573 					  adev->mman.fw_vram_usage_start_offset,
1574 					  adev->mman.fw_vram_usage_size,
1575 					  &adev->mman.fw_vram_usage_reserved_bo,
1576 					  &adev->mman.fw_vram_usage_va);
1577 }
1578 
1579 /**
1580  * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1581  *
1582  * @adev: amdgpu_device pointer
1583  *
1584  * create bo vram reservation from drv.
1585  */
1586 static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1587 {
1588 	u64 vram_size = adev->gmc.visible_vram_size;
1589 
1590 	adev->mman.drv_vram_usage_va = NULL;
1591 	adev->mman.drv_vram_usage_reserved_bo = NULL;
1592 
1593 	if (adev->mman.drv_vram_usage_size == 0 ||
1594 	    adev->mman.drv_vram_usage_size > vram_size)
1595 		return 0;
1596 
1597 	return amdgpu_bo_create_kernel_at(adev,
1598 					  adev->mman.drv_vram_usage_start_offset,
1599 					  adev->mman.drv_vram_usage_size,
1600 					  &adev->mman.drv_vram_usage_reserved_bo,
1601 					  &adev->mman.drv_vram_usage_va);
1602 }
1603 
1604 /*
1605  * Memoy training reservation functions
1606  */
1607 
1608 /**
1609  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1610  *
1611  * @adev: amdgpu_device pointer
1612  *
1613  * free memory training reserved vram if it has been reserved.
1614  */
1615 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1616 {
1617 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1618 
1619 	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1620 	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1621 	ctx->c2p_bo = NULL;
1622 
1623 	return 0;
1624 }
1625 
1626 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1627 {
1628 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1629 
1630 	memset(ctx, 0, sizeof(*ctx));
1631 
1632 	ctx->c2p_train_data_offset =
1633 		ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1634 	ctx->p2c_train_data_offset =
1635 		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1636 	ctx->train_data_size =
1637 		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1638 
1639 	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1640 			ctx->train_data_size,
1641 			ctx->p2c_train_data_offset,
1642 			ctx->c2p_train_data_offset);
1643 }
1644 
1645 /*
1646  * reserve TMR memory at the top of VRAM which holds
1647  * IP Discovery data and is protected by PSP.
1648  */
1649 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1650 {
1651 	int ret;
1652 	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1653 	bool mem_train_support = false;
1654 
1655 	if (!amdgpu_sriov_vf(adev)) {
1656 		if (amdgpu_atomfirmware_mem_training_supported(adev))
1657 			mem_train_support = true;
1658 		else
1659 			DRM_DEBUG("memory training does not support!\n");
1660 	}
1661 
1662 	/*
1663 	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1664 	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1665 	 *
1666 	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1667 	 * discovery data and G6 memory training data respectively
1668 	 */
1669 	adev->mman.discovery_tmr_size =
1670 		amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1671 	if (!adev->mman.discovery_tmr_size)
1672 		adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1673 
1674 	if (mem_train_support) {
1675 		/* reserve vram for mem train according to TMR location */
1676 		amdgpu_ttm_training_data_block_init(adev);
1677 		ret = amdgpu_bo_create_kernel_at(adev,
1678 						 ctx->c2p_train_data_offset,
1679 						 ctx->train_data_size,
1680 						 &ctx->c2p_bo,
1681 						 NULL);
1682 		if (ret) {
1683 			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1684 			amdgpu_ttm_training_reserve_vram_fini(adev);
1685 			return ret;
1686 		}
1687 		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1688 	}
1689 
1690 	ret = amdgpu_bo_create_kernel_at(adev,
1691 					 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1692 					 adev->mman.discovery_tmr_size,
1693 					 &adev->mman.discovery_memory,
1694 					 NULL);
1695 	if (ret) {
1696 		DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1697 		amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1698 		return ret;
1699 	}
1700 
1701 	return 0;
1702 }
1703 
1704 /*
1705  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1706  * gtt/vram related fields.
1707  *
1708  * This initializes all of the memory space pools that the TTM layer
1709  * will need such as the GTT space (system memory mapped to the device),
1710  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1711  * can be mapped per VMID.
1712  */
1713 int amdgpu_ttm_init(struct amdgpu_device *adev)
1714 {
1715 	uint64_t gtt_size;
1716 	int r;
1717 
1718 	mutex_init(&adev->mman.gtt_window_lock);
1719 
1720 	/* No others user of address space so set it to 0 */
1721 	r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1722 			       adev_to_drm(adev)->anon_inode->i_mapping,
1723 			       adev_to_drm(adev)->vma_offset_manager,
1724 			       adev->need_swiotlb,
1725 			       dma_addressing_limited(adev->dev));
1726 	if (r) {
1727 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1728 		return r;
1729 	}
1730 	adev->mman.initialized = true;
1731 
1732 	/* Initialize VRAM pool with all of VRAM divided into pages */
1733 	r = amdgpu_vram_mgr_init(adev);
1734 	if (r) {
1735 		DRM_ERROR("Failed initializing VRAM heap.\n");
1736 		return r;
1737 	}
1738 
1739 	/* Change the size here instead of the init above so only lpfn is affected */
1740 	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1741 #ifdef CONFIG_64BIT
1742 #ifdef CONFIG_X86
1743 	if (adev->gmc.xgmi.connected_to_cpu)
1744 		adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1745 				adev->gmc.visible_vram_size);
1746 
1747 	else
1748 #endif
1749 		adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1750 				adev->gmc.visible_vram_size);
1751 #endif
1752 
1753 	/*
1754 	 *The reserved vram for firmware must be pinned to the specified
1755 	 *place on the VRAM, so reserve it early.
1756 	 */
1757 	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1758 	if (r) {
1759 		return r;
1760 	}
1761 
1762 	/*
1763 	 *The reserved vram for driver must be pinned to the specified
1764 	 *place on the VRAM, so reserve it early.
1765 	 */
1766 	r = amdgpu_ttm_drv_reserve_vram_init(adev);
1767 	if (r)
1768 		return r;
1769 
1770 	/*
1771 	 * only NAVI10 and onwards ASIC support for IP discovery.
1772 	 * If IP discovery enabled, a block of memory should be
1773 	 * reserved for IP discovey.
1774 	 */
1775 	if (adev->mman.discovery_bin) {
1776 		r = amdgpu_ttm_reserve_tmr(adev);
1777 		if (r)
1778 			return r;
1779 	}
1780 
1781 	/* allocate memory as required for VGA
1782 	 * This is used for VGA emulation and pre-OS scanout buffers to
1783 	 * avoid display artifacts while transitioning between pre-OS
1784 	 * and driver.  */
1785 	r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1786 				       &adev->mman.stolen_vga_memory,
1787 				       NULL);
1788 	if (r)
1789 		return r;
1790 	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1791 				       adev->mman.stolen_extended_size,
1792 				       &adev->mman.stolen_extended_memory,
1793 				       NULL);
1794 	if (r)
1795 		return r;
1796 	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1797 				       adev->mman.stolen_reserved_size,
1798 				       &adev->mman.stolen_reserved_memory,
1799 				       NULL);
1800 	if (r)
1801 		return r;
1802 
1803 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1804 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1805 
1806 	/* Compute GTT size, either based on 1/2 the size of RAM size
1807 	 * or whatever the user passed on module init */
1808 	if (amdgpu_gtt_size == -1) {
1809 		struct sysinfo si;
1810 
1811 		si_meminfo(&si);
1812 		/* Certain GL unit tests for large textures can cause problems
1813 		 * with the OOM killer since there is no way to link this memory
1814 		 * to a process.  This was originally mitigated (but not necessarily
1815 		 * eliminated) by limiting the GTT size.  The problem is this limit
1816 		 * is often too low for many modern games so just make the limit 1/2
1817 		 * of system memory which aligns with TTM. The OOM accounting needs
1818 		 * to be addressed, but we shouldn't prevent common 3D applications
1819 		 * from being usable just to potentially mitigate that corner case.
1820 		 */
1821 		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1822 			       (u64)si.totalram * si.mem_unit / 2);
1823 	} else {
1824 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1825 	}
1826 
1827 	/* Initialize GTT memory pool */
1828 	r = amdgpu_gtt_mgr_init(adev, gtt_size);
1829 	if (r) {
1830 		DRM_ERROR("Failed initializing GTT heap.\n");
1831 		return r;
1832 	}
1833 	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1834 		 (unsigned)(gtt_size / (1024 * 1024)));
1835 
1836 	/* Initialize preemptible memory pool */
1837 	r = amdgpu_preempt_mgr_init(adev);
1838 	if (r) {
1839 		DRM_ERROR("Failed initializing PREEMPT heap.\n");
1840 		return r;
1841 	}
1842 
1843 	/* Initialize various on-chip memory pools */
1844 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1845 	if (r) {
1846 		DRM_ERROR("Failed initializing GDS heap.\n");
1847 		return r;
1848 	}
1849 
1850 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1851 	if (r) {
1852 		DRM_ERROR("Failed initializing gws heap.\n");
1853 		return r;
1854 	}
1855 
1856 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1857 	if (r) {
1858 		DRM_ERROR("Failed initializing oa heap.\n");
1859 		return r;
1860 	}
1861 
1862 	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1863 				AMDGPU_GEM_DOMAIN_GTT,
1864 				&adev->mman.sdma_access_bo, NULL,
1865 				&adev->mman.sdma_access_ptr))
1866 		DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1867 
1868 	return 0;
1869 }
1870 
1871 /*
1872  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1873  */
1874 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1875 {
1876 	int idx;
1877 	if (!adev->mman.initialized)
1878 		return;
1879 
1880 	amdgpu_ttm_training_reserve_vram_fini(adev);
1881 	/* return the stolen vga memory back to VRAM */
1882 	amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1883 	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1884 	/* return the IP Discovery TMR memory back to VRAM */
1885 	amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1886 	if (adev->mman.stolen_reserved_size)
1887 		amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1888 				      NULL, NULL);
1889 	amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
1890 					&adev->mman.sdma_access_ptr);
1891 	amdgpu_ttm_fw_reserve_vram_fini(adev);
1892 	amdgpu_ttm_drv_reserve_vram_fini(adev);
1893 
1894 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1895 
1896 		if (adev->mman.aper_base_kaddr)
1897 			iounmap(adev->mman.aper_base_kaddr);
1898 		adev->mman.aper_base_kaddr = NULL;
1899 
1900 		drm_dev_exit(idx);
1901 	}
1902 
1903 	amdgpu_vram_mgr_fini(adev);
1904 	amdgpu_gtt_mgr_fini(adev);
1905 	amdgpu_preempt_mgr_fini(adev);
1906 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1907 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1908 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1909 	ttm_device_fini(&adev->mman.bdev);
1910 	adev->mman.initialized = false;
1911 	DRM_INFO("amdgpu: ttm finalized\n");
1912 }
1913 
1914 /**
1915  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1916  *
1917  * @adev: amdgpu_device pointer
1918  * @enable: true when we can use buffer functions.
1919  *
1920  * Enable/disable use of buffer functions during suspend/resume. This should
1921  * only be called at bootup or when userspace isn't running.
1922  */
1923 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1924 {
1925 	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1926 	uint64_t size;
1927 	int r;
1928 
1929 	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1930 	    adev->mman.buffer_funcs_enabled == enable)
1931 		return;
1932 
1933 	if (enable) {
1934 		struct amdgpu_ring *ring;
1935 		struct drm_gpu_scheduler *sched;
1936 
1937 		ring = adev->mman.buffer_funcs_ring;
1938 		sched = &ring->sched;
1939 		r = drm_sched_entity_init(&adev->mman.entity,
1940 					  DRM_SCHED_PRIORITY_KERNEL, &sched,
1941 					  1, NULL);
1942 		if (r) {
1943 			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1944 				  r);
1945 			return;
1946 		}
1947 	} else {
1948 		drm_sched_entity_destroy(&adev->mman.entity);
1949 		dma_fence_put(man->move);
1950 		man->move = NULL;
1951 	}
1952 
1953 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
1954 	if (enable)
1955 		size = adev->gmc.real_vram_size;
1956 	else
1957 		size = adev->gmc.visible_vram_size;
1958 	man->size = size;
1959 	adev->mman.buffer_funcs_enabled = enable;
1960 }
1961 
1962 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
1963 				  bool direct_submit,
1964 				  unsigned int num_dw,
1965 				  struct dma_resv *resv,
1966 				  bool vm_needs_flush,
1967 				  struct amdgpu_job **job)
1968 {
1969 	enum amdgpu_ib_pool_type pool = direct_submit ?
1970 		AMDGPU_IB_POOL_DIRECT :
1971 		AMDGPU_IB_POOL_DELAYED;
1972 	int r;
1973 
1974 	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
1975 				     AMDGPU_FENCE_OWNER_UNDEFINED,
1976 				     num_dw * 4, pool, job);
1977 	if (r)
1978 		return r;
1979 
1980 	if (vm_needs_flush) {
1981 		(*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1982 							adev->gmc.pdb0_bo :
1983 							adev->gart.bo);
1984 		(*job)->vm_needs_flush = true;
1985 	}
1986 	if (!resv)
1987 		return 0;
1988 
1989 	return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
1990 						   DMA_RESV_USAGE_BOOKKEEP);
1991 }
1992 
1993 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1994 		       uint64_t dst_offset, uint32_t byte_count,
1995 		       struct dma_resv *resv,
1996 		       struct dma_fence **fence, bool direct_submit,
1997 		       bool vm_needs_flush, bool tmz)
1998 {
1999 	struct amdgpu_device *adev = ring->adev;
2000 	unsigned num_loops, num_dw;
2001 	struct amdgpu_job *job;
2002 	uint32_t max_bytes;
2003 	unsigned i;
2004 	int r;
2005 
2006 	if (!direct_submit && !ring->sched.ready) {
2007 		DRM_ERROR("Trying to move memory with ring turned off.\n");
2008 		return -EINVAL;
2009 	}
2010 
2011 	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2012 	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2013 	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2014 	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2015 				   resv, vm_needs_flush, &job);
2016 	if (r)
2017 		return r;
2018 
2019 	for (i = 0; i < num_loops; i++) {
2020 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2021 
2022 		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2023 					dst_offset, cur_size_in_bytes, tmz);
2024 
2025 		src_offset += cur_size_in_bytes;
2026 		dst_offset += cur_size_in_bytes;
2027 		byte_count -= cur_size_in_bytes;
2028 	}
2029 
2030 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2031 	WARN_ON(job->ibs[0].length_dw > num_dw);
2032 	if (direct_submit)
2033 		r = amdgpu_job_submit_direct(job, ring, fence);
2034 	else
2035 		*fence = amdgpu_job_submit(job);
2036 	if (r)
2037 		goto error_free;
2038 
2039 	return r;
2040 
2041 error_free:
2042 	amdgpu_job_free(job);
2043 	DRM_ERROR("Error scheduling IBs (%d)\n", r);
2044 	return r;
2045 }
2046 
2047 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2048 			       uint64_t dst_addr, uint32_t byte_count,
2049 			       struct dma_resv *resv,
2050 			       struct dma_fence **fence,
2051 			       bool vm_needs_flush)
2052 {
2053 	struct amdgpu_device *adev = ring->adev;
2054 	unsigned int num_loops, num_dw;
2055 	struct amdgpu_job *job;
2056 	uint32_t max_bytes;
2057 	unsigned int i;
2058 	int r;
2059 
2060 	max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2061 	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2062 	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2063 	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2064 				   &job);
2065 	if (r)
2066 		return r;
2067 
2068 	for (i = 0; i < num_loops; i++) {
2069 		uint32_t cur_size = min(byte_count, max_bytes);
2070 
2071 		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2072 					cur_size);
2073 
2074 		dst_addr += cur_size;
2075 		byte_count -= cur_size;
2076 	}
2077 
2078 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2079 	WARN_ON(job->ibs[0].length_dw > num_dw);
2080 	*fence = amdgpu_job_submit(job);
2081 	return 0;
2082 }
2083 
2084 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2085 			uint32_t src_data,
2086 			struct dma_resv *resv,
2087 			struct dma_fence **f)
2088 {
2089 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2090 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2091 	struct dma_fence *fence = NULL;
2092 	struct amdgpu_res_cursor dst;
2093 	int r;
2094 
2095 	if (!adev->mman.buffer_funcs_enabled) {
2096 		DRM_ERROR("Trying to clear memory with ring turned off.\n");
2097 		return -EINVAL;
2098 	}
2099 
2100 	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2101 
2102 	mutex_lock(&adev->mman.gtt_window_lock);
2103 	while (dst.remaining) {
2104 		struct dma_fence *next;
2105 		uint64_t cur_size, to;
2106 
2107 		/* Never fill more than 256MiB at once to avoid timeouts */
2108 		cur_size = min(dst.size, 256ULL << 20);
2109 
2110 		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2111 					  1, ring, false, &cur_size, &to);
2112 		if (r)
2113 			goto error;
2114 
2115 		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2116 					&next, true);
2117 		if (r)
2118 			goto error;
2119 
2120 		dma_fence_put(fence);
2121 		fence = next;
2122 
2123 		amdgpu_res_next(&dst, cur_size);
2124 	}
2125 error:
2126 	mutex_unlock(&adev->mman.gtt_window_lock);
2127 	if (f)
2128 		*f = dma_fence_get(fence);
2129 	dma_fence_put(fence);
2130 	return r;
2131 }
2132 
2133 /**
2134  * amdgpu_ttm_evict_resources - evict memory buffers
2135  * @adev: amdgpu device object
2136  * @mem_type: evicted BO's memory type
2137  *
2138  * Evicts all @mem_type buffers on the lru list of the memory type.
2139  *
2140  * Returns:
2141  * 0 for success or a negative error code on failure.
2142  */
2143 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2144 {
2145 	struct ttm_resource_manager *man;
2146 
2147 	switch (mem_type) {
2148 	case TTM_PL_VRAM:
2149 	case TTM_PL_TT:
2150 	case AMDGPU_PL_GWS:
2151 	case AMDGPU_PL_GDS:
2152 	case AMDGPU_PL_OA:
2153 		man = ttm_manager_type(&adev->mman.bdev, mem_type);
2154 		break;
2155 	default:
2156 		DRM_ERROR("Trying to evict invalid memory type\n");
2157 		return -EINVAL;
2158 	}
2159 
2160 	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2161 }
2162 
2163 #if defined(CONFIG_DEBUG_FS)
2164 
2165 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2166 {
2167 	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2168 
2169 	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2170 }
2171 
2172 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2173 
2174 /*
2175  * amdgpu_ttm_vram_read - Linear read access to VRAM
2176  *
2177  * Accesses VRAM via MMIO for debugging purposes.
2178  */
2179 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2180 				    size_t size, loff_t *pos)
2181 {
2182 	struct amdgpu_device *adev = file_inode(f)->i_private;
2183 	ssize_t result = 0;
2184 
2185 	if (size & 0x3 || *pos & 0x3)
2186 		return -EINVAL;
2187 
2188 	if (*pos >= adev->gmc.mc_vram_size)
2189 		return -ENXIO;
2190 
2191 	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2192 	while (size) {
2193 		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2194 		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2195 
2196 		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2197 		if (copy_to_user(buf, value, bytes))
2198 			return -EFAULT;
2199 
2200 		result += bytes;
2201 		buf += bytes;
2202 		*pos += bytes;
2203 		size -= bytes;
2204 	}
2205 
2206 	return result;
2207 }
2208 
2209 /*
2210  * amdgpu_ttm_vram_write - Linear write access to VRAM
2211  *
2212  * Accesses VRAM via MMIO for debugging purposes.
2213  */
2214 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2215 				    size_t size, loff_t *pos)
2216 {
2217 	struct amdgpu_device *adev = file_inode(f)->i_private;
2218 	ssize_t result = 0;
2219 	int r;
2220 
2221 	if (size & 0x3 || *pos & 0x3)
2222 		return -EINVAL;
2223 
2224 	if (*pos >= adev->gmc.mc_vram_size)
2225 		return -ENXIO;
2226 
2227 	while (size) {
2228 		uint32_t value;
2229 
2230 		if (*pos >= adev->gmc.mc_vram_size)
2231 			return result;
2232 
2233 		r = get_user(value, (uint32_t *)buf);
2234 		if (r)
2235 			return r;
2236 
2237 		amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2238 
2239 		result += 4;
2240 		buf += 4;
2241 		*pos += 4;
2242 		size -= 4;
2243 	}
2244 
2245 	return result;
2246 }
2247 
2248 static const struct file_operations amdgpu_ttm_vram_fops = {
2249 	.owner = THIS_MODULE,
2250 	.read = amdgpu_ttm_vram_read,
2251 	.write = amdgpu_ttm_vram_write,
2252 	.llseek = default_llseek,
2253 };
2254 
2255 /*
2256  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2257  *
2258  * This function is used to read memory that has been mapped to the
2259  * GPU and the known addresses are not physical addresses but instead
2260  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2261  */
2262 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2263 				 size_t size, loff_t *pos)
2264 {
2265 	struct amdgpu_device *adev = file_inode(f)->i_private;
2266 	struct iommu_domain *dom;
2267 	ssize_t result = 0;
2268 	int r;
2269 
2270 	/* retrieve the IOMMU domain if any for this device */
2271 	dom = iommu_get_domain_for_dev(adev->dev);
2272 
2273 	while (size) {
2274 		phys_addr_t addr = *pos & PAGE_MASK;
2275 		loff_t off = *pos & ~PAGE_MASK;
2276 		size_t bytes = PAGE_SIZE - off;
2277 		unsigned long pfn;
2278 		struct page *p;
2279 		void *ptr;
2280 
2281 		bytes = bytes < size ? bytes : size;
2282 
2283 		/* Translate the bus address to a physical address.  If
2284 		 * the domain is NULL it means there is no IOMMU active
2285 		 * and the address translation is the identity
2286 		 */
2287 		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2288 
2289 		pfn = addr >> PAGE_SHIFT;
2290 		if (!pfn_valid(pfn))
2291 			return -EPERM;
2292 
2293 		p = pfn_to_page(pfn);
2294 		if (p->mapping != adev->mman.bdev.dev_mapping)
2295 			return -EPERM;
2296 
2297 		ptr = kmap_local_page(p);
2298 		r = copy_to_user(buf, ptr + off, bytes);
2299 		kunmap_local(ptr);
2300 		if (r)
2301 			return -EFAULT;
2302 
2303 		size -= bytes;
2304 		*pos += bytes;
2305 		result += bytes;
2306 	}
2307 
2308 	return result;
2309 }
2310 
2311 /*
2312  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2313  *
2314  * This function is used to write memory that has been mapped to the
2315  * GPU and the known addresses are not physical addresses but instead
2316  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2317  */
2318 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2319 				 size_t size, loff_t *pos)
2320 {
2321 	struct amdgpu_device *adev = file_inode(f)->i_private;
2322 	struct iommu_domain *dom;
2323 	ssize_t result = 0;
2324 	int r;
2325 
2326 	dom = iommu_get_domain_for_dev(adev->dev);
2327 
2328 	while (size) {
2329 		phys_addr_t addr = *pos & PAGE_MASK;
2330 		loff_t off = *pos & ~PAGE_MASK;
2331 		size_t bytes = PAGE_SIZE - off;
2332 		unsigned long pfn;
2333 		struct page *p;
2334 		void *ptr;
2335 
2336 		bytes = bytes < size ? bytes : size;
2337 
2338 		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2339 
2340 		pfn = addr >> PAGE_SHIFT;
2341 		if (!pfn_valid(pfn))
2342 			return -EPERM;
2343 
2344 		p = pfn_to_page(pfn);
2345 		if (p->mapping != adev->mman.bdev.dev_mapping)
2346 			return -EPERM;
2347 
2348 		ptr = kmap_local_page(p);
2349 		r = copy_from_user(ptr + off, buf, bytes);
2350 		kunmap_local(ptr);
2351 		if (r)
2352 			return -EFAULT;
2353 
2354 		size -= bytes;
2355 		*pos += bytes;
2356 		result += bytes;
2357 	}
2358 
2359 	return result;
2360 }
2361 
2362 static const struct file_operations amdgpu_ttm_iomem_fops = {
2363 	.owner = THIS_MODULE,
2364 	.read = amdgpu_iomem_read,
2365 	.write = amdgpu_iomem_write,
2366 	.llseek = default_llseek
2367 };
2368 
2369 #endif
2370 
2371 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2372 {
2373 #if defined(CONFIG_DEBUG_FS)
2374 	struct drm_minor *minor = adev_to_drm(adev)->primary;
2375 	struct dentry *root = minor->debugfs_root;
2376 
2377 	debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2378 				 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2379 	debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2380 			    &amdgpu_ttm_iomem_fops);
2381 	debugfs_create_file("ttm_page_pool", 0444, root, adev,
2382 			    &amdgpu_ttm_page_pool_fops);
2383 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2384 							     TTM_PL_VRAM),
2385 					    root, "amdgpu_vram_mm");
2386 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2387 							     TTM_PL_TT),
2388 					    root, "amdgpu_gtt_mm");
2389 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2390 							     AMDGPU_PL_GDS),
2391 					    root, "amdgpu_gds_mm");
2392 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2393 							     AMDGPU_PL_GWS),
2394 					    root, "amdgpu_gws_mm");
2395 	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2396 							     AMDGPU_PL_OA),
2397 					    root, "amdgpu_oa_mm");
2398 
2399 #endif
2400 }
2401