157b3ec35SLeo Li /* 257b3ec35SLeo Li * Copyright 2019 Advanced Micro Devices, Inc. 357b3ec35SLeo Li * 457b3ec35SLeo Li * Permission is hereby granted, free of charge, to any person obtaining a 557b3ec35SLeo Li * copy of this software and associated documentation files (the "Software"), 657b3ec35SLeo Li * to deal in the Software without restriction, including without limitation 757b3ec35SLeo Li * the rights to use, copy, modify, merge, publish, distribute, sublicense, 857b3ec35SLeo Li * and/or sell copies of the Software, and to permit persons to whom the 957b3ec35SLeo Li * Software is furnished to do so, subject to the following conditions: 1057b3ec35SLeo Li * 1157b3ec35SLeo Li * The above copyright notice and this permission notice shall be included in 1257b3ec35SLeo Li * all copies or substantial portions of the Software. 1357b3ec35SLeo Li * 1457b3ec35SLeo Li * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1557b3ec35SLeo Li * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1657b3ec35SLeo Li * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1757b3ec35SLeo Li * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1857b3ec35SLeo Li * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1957b3ec35SLeo Li * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2057b3ec35SLeo Li * OTHER DEALINGS IN THE SOFTWARE. 2157b3ec35SLeo Li * 2257b3ec35SLeo Li */ 2357b3ec35SLeo Li #ifndef __AMDGPU_SOCBB_H__ 2457b3ec35SLeo Li #define __AMDGPU_SOCBB_H__ 2557b3ec35SLeo Li 2657b3ec35SLeo Li struct gpu_info_voltage_scaling_v1_0 { 2776b743f4SXiaojie Yuan uint32_t state; 2857b3ec35SLeo Li uint32_t dscclk_mhz; 2957b3ec35SLeo Li uint32_t dcfclk_mhz; 3057b3ec35SLeo Li uint32_t socclk_mhz; 3157b3ec35SLeo Li uint32_t dram_speed_mts; 3257b3ec35SLeo Li uint32_t fabricclk_mhz; 3357b3ec35SLeo Li uint32_t dispclk_mhz; 3457b3ec35SLeo Li uint32_t phyclk_mhz; 3557b3ec35SLeo Li uint32_t dppclk_mhz; 3657b3ec35SLeo Li }; 3757b3ec35SLeo Li 3857b3ec35SLeo Li struct gpu_info_soc_bounding_box_v1_0 { 3957b3ec35SLeo Li uint32_t sr_exit_time_us; 4057b3ec35SLeo Li uint32_t sr_enter_plus_exit_time_us; 4157b3ec35SLeo Li uint32_t urgent_latency_us; 4257b3ec35SLeo Li uint32_t urgent_latency_pixel_data_only_us; 4357b3ec35SLeo Li uint32_t urgent_latency_pixel_mixed_with_vm_data_us; 4457b3ec35SLeo Li uint32_t urgent_latency_vm_data_only_us; 4557b3ec35SLeo Li uint32_t writeback_latency_us; 4657b3ec35SLeo Li uint32_t ideal_dram_bw_after_urgent_percent; 4757b3ec35SLeo Li uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 4857b3ec35SLeo Li uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 4957b3ec35SLeo Li uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only; 5057b3ec35SLeo Li uint32_t max_avg_sdp_bw_use_normal_percent; 5157b3ec35SLeo Li uint32_t max_avg_dram_bw_use_normal_percent; 5276b743f4SXiaojie Yuan uint32_t max_request_size_bytes; 5357b3ec35SLeo Li uint32_t downspread_percent; 5457b3ec35SLeo Li uint32_t dram_page_open_time_ns; 5557b3ec35SLeo Li uint32_t dram_rw_turnaround_time_ns; 5657b3ec35SLeo Li uint32_t dram_return_buffer_per_channel_bytes; 5757b3ec35SLeo Li uint32_t dram_channel_width_bytes; 5857b3ec35SLeo Li uint32_t fabric_datapath_to_dcn_data_return_bytes; 5957b3ec35SLeo Li uint32_t dcn_downspread_percent; 6057b3ec35SLeo Li uint32_t dispclk_dppclk_vco_speed_mhz; 6157b3ec35SLeo Li uint32_t dfs_vco_period_ps; 6276b743f4SXiaojie Yuan uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes; 6376b743f4SXiaojie Yuan uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 6476b743f4SXiaojie Yuan uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes; 6576b743f4SXiaojie Yuan uint32_t round_trip_ping_latency_dcfclk_cycles; 6676b743f4SXiaojie Yuan uint32_t urgent_out_of_order_return_per_channel_bytes; 6776b743f4SXiaojie Yuan uint32_t channel_interleave_bytes; 6876b743f4SXiaojie Yuan uint32_t num_banks; 6976b743f4SXiaojie Yuan uint32_t num_chans; 7076b743f4SXiaojie Yuan uint32_t vmm_page_size_bytes; 7157b3ec35SLeo Li uint32_t dram_clock_change_latency_us; 7257b3ec35SLeo Li uint32_t writeback_dram_clock_change_latency_us; 7376b743f4SXiaojie Yuan uint32_t return_bus_width_bytes; 7476b743f4SXiaojie Yuan uint32_t voltage_override; 7557b3ec35SLeo Li uint32_t xfc_bus_transport_time_us; 7657b3ec35SLeo Li uint32_t xfc_xbuf_latency_tolerance_us; 7776b743f4SXiaojie Yuan uint32_t use_urgent_burst_bw; 7876b743f4SXiaojie Yuan uint32_t num_states; 7957b3ec35SLeo Li struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; 8057b3ec35SLeo Li }; 8157b3ec35SLeo Li 8257b3ec35SLeo Li #endif 83