1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_SDMA_H__ 25 #define __AMDGPU_SDMA_H__ 26 27 /* max number of IP instances */ 28 #define AMDGPU_MAX_SDMA_INSTANCES 2 29 30 enum amdgpu_sdma_irq { 31 AMDGPU_SDMA_IRQ_TRAP0 = 0, 32 AMDGPU_SDMA_IRQ_TRAP1, 33 34 AMDGPU_SDMA_IRQ_LAST 35 }; 36 37 struct amdgpu_sdma_instance { 38 /* SDMA firmware */ 39 const struct firmware *fw; 40 uint32_t fw_version; 41 uint32_t feature_version; 42 43 struct amdgpu_ring ring; 44 bool burst_nop; 45 }; 46 47 struct amdgpu_sdma { 48 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 49 #ifdef CONFIG_DRM_AMDGPU_SI 50 //SI DMA has a difference trap irq number for the second engine 51 struct amdgpu_irq_src trap_irq_1; 52 #endif 53 struct amdgpu_irq_src trap_irq; 54 struct amdgpu_irq_src illegal_inst_irq; 55 int num_instances; 56 uint32_t srbm_soft_reset; 57 }; 58 59 /* 60 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma 61 * But currently, we use sdma to move data. 62 */ 63 struct amdgpu_buffer_funcs { 64 /* maximum bytes in a single operation */ 65 uint32_t copy_max_bytes; 66 67 /* number of dw to reserve per operation */ 68 unsigned copy_num_dw; 69 70 /* used for buffer migration */ 71 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 72 /* src addr in bytes */ 73 uint64_t src_offset, 74 /* dst addr in bytes */ 75 uint64_t dst_offset, 76 /* number of byte to transfer */ 77 uint32_t byte_count); 78 79 /* maximum bytes in a single operation */ 80 uint32_t fill_max_bytes; 81 82 /* number of dw to reserve per operation */ 83 unsigned fill_num_dw; 84 85 /* used for buffer clearing */ 86 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 87 /* value to write to memory */ 88 uint32_t src_data, 89 /* dst addr in bytes */ 90 uint64_t dst_offset, 91 /* number of byte to fill */ 92 uint32_t byte_count); 93 }; 94 95 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 96 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 97 98 struct amdgpu_sdma_instance * 99 amdgpu_get_sdma_instance(struct amdgpu_ring *ring); 100 101 #endif 102