1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_SDMA_H__ 25 #define __AMDGPU_SDMA_H__ 26 27 /* max number of IP instances */ 28 #define AMDGPU_MAX_SDMA_INSTANCES 2 29 30 enum amdgpu_sdma_irq { 31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0, 32 AMDGPU_SDMA_IRQ_INSTANCE1, 33 AMDGPU_SDMA_IRQ_LAST 34 }; 35 36 struct amdgpu_sdma_instance { 37 /* SDMA firmware */ 38 const struct firmware *fw; 39 uint32_t fw_version; 40 uint32_t feature_version; 41 42 struct amdgpu_ring ring; 43 struct amdgpu_ring page; 44 bool burst_nop; 45 }; 46 47 struct amdgpu_sdma { 48 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 49 struct amdgpu_irq_src trap_irq; 50 struct amdgpu_irq_src illegal_inst_irq; 51 struct amdgpu_irq_src ecc_irq; 52 int num_instances; 53 uint32_t srbm_soft_reset; 54 bool has_page_queue; 55 struct ras_common_if *ras_if; 56 }; 57 58 /* 59 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma 60 * But currently, we use sdma to move data. 61 */ 62 struct amdgpu_buffer_funcs { 63 /* maximum bytes in a single operation */ 64 uint32_t copy_max_bytes; 65 66 /* number of dw to reserve per operation */ 67 unsigned copy_num_dw; 68 69 /* used for buffer migration */ 70 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 71 /* src addr in bytes */ 72 uint64_t src_offset, 73 /* dst addr in bytes */ 74 uint64_t dst_offset, 75 /* number of byte to transfer */ 76 uint32_t byte_count); 77 78 /* maximum bytes in a single operation */ 79 uint32_t fill_max_bytes; 80 81 /* number of dw to reserve per operation */ 82 unsigned fill_num_dw; 83 84 /* used for buffer clearing */ 85 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 86 /* value to write to memory */ 87 uint32_t src_data, 88 /* dst addr in bytes */ 89 uint64_t dst_offset, 90 /* number of byte to fill */ 91 uint32_t byte_count); 92 }; 93 94 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 95 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 96 97 struct amdgpu_sdma_instance * 98 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); 99 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index); 100 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid); 101 #endif 102