1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_SDMA_H__ 25 #define __AMDGPU_SDMA_H__ 26 27 /* max number of IP instances */ 28 #define AMDGPU_MAX_SDMA_INSTANCES 2 29 30 enum amdgpu_sdma_irq { 31 AMDGPU_SDMA_IRQ_TRAP0 = 0, 32 AMDGPU_SDMA_IRQ_TRAP1, 33 AMDGPU_SDMA_IRQ_ECC0, 34 AMDGPU_SDMA_IRQ_ECC1, 35 36 AMDGPU_SDMA_IRQ_LAST 37 }; 38 39 struct amdgpu_sdma_instance { 40 /* SDMA firmware */ 41 const struct firmware *fw; 42 uint32_t fw_version; 43 uint32_t feature_version; 44 45 struct amdgpu_ring ring; 46 struct amdgpu_ring page; 47 bool burst_nop; 48 }; 49 50 struct amdgpu_sdma { 51 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 52 struct amdgpu_irq_src trap_irq; 53 struct amdgpu_irq_src illegal_inst_irq; 54 struct amdgpu_irq_src ecc_irq; 55 int num_instances; 56 uint32_t srbm_soft_reset; 57 bool has_page_queue; 58 struct ras_common_if *ras_if; 59 }; 60 61 /* 62 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma 63 * But currently, we use sdma to move data. 64 */ 65 struct amdgpu_buffer_funcs { 66 /* maximum bytes in a single operation */ 67 uint32_t copy_max_bytes; 68 69 /* number of dw to reserve per operation */ 70 unsigned copy_num_dw; 71 72 /* used for buffer migration */ 73 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 74 /* src addr in bytes */ 75 uint64_t src_offset, 76 /* dst addr in bytes */ 77 uint64_t dst_offset, 78 /* number of byte to transfer */ 79 uint32_t byte_count); 80 81 /* maximum bytes in a single operation */ 82 uint32_t fill_max_bytes; 83 84 /* number of dw to reserve per operation */ 85 unsigned fill_num_dw; 86 87 /* used for buffer clearing */ 88 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 89 /* value to write to memory */ 90 uint32_t src_data, 91 /* dst addr in bytes */ 92 uint64_t dst_offset, 93 /* number of byte to fill */ 94 uint32_t byte_count); 95 }; 96 97 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 98 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 99 100 struct amdgpu_sdma_instance * 101 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); 102 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index); 103 104 #endif 105