1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_SDMA_H__
25 #define __AMDGPU_SDMA_H__
26 #include "amdgpu_ras.h"
27 
28 /* max number of IP instances */
29 #define AMDGPU_MAX_SDMA_INSTANCES		8
30 
31 enum amdgpu_sdma_irq {
32 	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
33 	AMDGPU_SDMA_IRQ_INSTANCE1,
34 	AMDGPU_SDMA_IRQ_INSTANCE2,
35 	AMDGPU_SDMA_IRQ_INSTANCE3,
36 	AMDGPU_SDMA_IRQ_INSTANCE4,
37 	AMDGPU_SDMA_IRQ_INSTANCE5,
38 	AMDGPU_SDMA_IRQ_INSTANCE6,
39 	AMDGPU_SDMA_IRQ_INSTANCE7,
40 	AMDGPU_SDMA_IRQ_LAST
41 };
42 
43 struct amdgpu_sdma_instance {
44 	/* SDMA firmware */
45 	const struct firmware	*fw;
46 	uint32_t		fw_version;
47 	uint32_t		feature_version;
48 
49 	struct amdgpu_ring	ring;
50 	struct amdgpu_ring	page;
51 	bool			burst_nop;
52 };
53 
54 struct amdgpu_sdma_ras {
55 	struct amdgpu_ras_block_object ras_block;
56 };
57 
58 struct amdgpu_sdma {
59 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
60 	struct amdgpu_irq_src	trap_irq;
61 	struct amdgpu_irq_src	illegal_inst_irq;
62 	struct amdgpu_irq_src	ecc_irq;
63 	struct amdgpu_irq_src	vm_hole_irq;
64 	struct amdgpu_irq_src	doorbell_invalid_irq;
65 	struct amdgpu_irq_src	pool_timeout_irq;
66 	struct amdgpu_irq_src	srbm_write_irq;
67 
68 	int			num_instances;
69 	uint32_t                    srbm_soft_reset;
70 	bool			has_page_queue;
71 	struct ras_common_if	*ras_if;
72 	struct amdgpu_sdma_ras	*ras;
73 };
74 
75 /*
76  * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
77  * But currently, we use sdma to move data.
78  */
79 struct amdgpu_buffer_funcs {
80 	/* maximum bytes in a single operation */
81 	uint32_t	copy_max_bytes;
82 
83 	/* number of dw to reserve per operation */
84 	unsigned	copy_num_dw;
85 
86 	/* used for buffer migration */
87 	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
88 				 /* src addr in bytes */
89 				 uint64_t src_offset,
90 				 /* dst addr in bytes */
91 				 uint64_t dst_offset,
92 				 /* number of byte to transfer */
93 				 uint32_t byte_count,
94 				 bool tmz);
95 
96 	/* maximum bytes in a single operation */
97 	uint32_t	fill_max_bytes;
98 
99 	/* number of dw to reserve per operation */
100 	unsigned	fill_num_dw;
101 
102 	/* used for buffer clearing */
103 	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
104 				 /* value to write to memory */
105 				 uint32_t src_data,
106 				 /* dst addr in bytes */
107 				 uint64_t dst_offset,
108 				 /* number of byte to fill */
109 				 uint32_t byte_count);
110 };
111 
112 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
113 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
114 
115 struct amdgpu_sdma_instance *
116 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
117 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
118 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
119 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
120 			      struct ras_common_if *ras_block);
121 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
122 		void *err_data,
123 		struct amdgpu_iv_entry *entry);
124 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
125 				      struct amdgpu_irq_src *source,
126 				      struct amdgpu_iv_entry *entry);
127 int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,
128 			       bool duplicate);
129 void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
130         bool duplicate);
131 void amdgpu_sdma_unset_buffer_funcs_helper(struct amdgpu_device *adev);
132 int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);
133 
134 #endif
135