1 /*
2  * Copyright 2017 Valve Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Andres Rodriguez <andresx7@gmail.com>
23  */
24 
25 #include <linux/fdtable.h>
26 #include <linux/pid.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 
30 #include "amdgpu_vm.h"
31 
32 enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
33 {
34 	switch (amdgpu_priority) {
35 	case AMDGPU_CTX_PRIORITY_VERY_HIGH:
36 		return DRM_SCHED_PRIORITY_HIGH_HW;
37 	case AMDGPU_CTX_PRIORITY_HIGH:
38 		return DRM_SCHED_PRIORITY_HIGH_SW;
39 	case AMDGPU_CTX_PRIORITY_NORMAL:
40 		return DRM_SCHED_PRIORITY_NORMAL;
41 	case AMDGPU_CTX_PRIORITY_LOW:
42 	case AMDGPU_CTX_PRIORITY_VERY_LOW:
43 		return DRM_SCHED_PRIORITY_LOW;
44 	case AMDGPU_CTX_PRIORITY_UNSET:
45 		return DRM_SCHED_PRIORITY_UNSET;
46 	default:
47 		WARN(1, "Invalid context priority %d\n", amdgpu_priority);
48 		return DRM_SCHED_PRIORITY_INVALID;
49 	}
50 }
51 
52 static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
53 						  int fd,
54 						  enum drm_sched_priority priority)
55 {
56 	struct fd f = fdget(fd);
57 	struct amdgpu_fpriv *fpriv;
58 	struct amdgpu_ctx *ctx;
59 	uint32_t id;
60 	int r;
61 
62 	if (!f.file)
63 		return -EINVAL;
64 
65 	r = amdgpu_file_to_fpriv(f.file, &fpriv);
66 	if (r) {
67 		fdput(f);
68 		return r;
69 	}
70 
71 	idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
72 		amdgpu_ctx_priority_override(ctx, priority);
73 
74 	fdput(f);
75 	return 0;
76 }
77 
78 static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev,
79 						  int fd,
80 						  unsigned ctx_id,
81 						  enum drm_sched_priority priority)
82 {
83 	struct fd f = fdget(fd);
84 	struct amdgpu_fpriv *fpriv;
85 	struct amdgpu_ctx *ctx;
86 	int r;
87 
88 	if (!f.file)
89 		return -EINVAL;
90 
91 	r = amdgpu_file_to_fpriv(f.file, &fpriv);
92 	if (r) {
93 		fdput(f);
94 		return r;
95 	}
96 
97 	ctx = amdgpu_ctx_get(fpriv, ctx_id);
98 
99 	if (!ctx) {
100 		fdput(f);
101 		return -EINVAL;
102 	}
103 
104 	amdgpu_ctx_priority_override(ctx, priority);
105 	amdgpu_ctx_put(ctx);
106 	fdput(f);
107 
108 	return 0;
109 }
110 
111 int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
112 		       struct drm_file *filp)
113 {
114 	union drm_amdgpu_sched *args = data;
115 	struct amdgpu_device *adev = dev->dev_private;
116 	enum drm_sched_priority priority;
117 	int r;
118 
119 	priority = amdgpu_to_sched_priority(args->in.priority);
120 	if (priority == DRM_SCHED_PRIORITY_INVALID)
121 		return -EINVAL;
122 
123 	switch (args->in.op) {
124 	case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
125 		r = amdgpu_sched_process_priority_override(adev,
126 							   args->in.fd,
127 							   priority);
128 		break;
129 	case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE:
130 		r = amdgpu_sched_context_priority_override(adev,
131 							   args->in.fd,
132 							   args->in.ctx_id,
133 							   priority);
134 		break;
135 	default:
136 		DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
137 		r = -EINVAL;
138 		break;
139 	}
140 
141 	return r;
142 }
143