188dfc9a3SLikun Gao /* 288dfc9a3SLikun Gao * Copyright 2014 Advanced Micro Devices, Inc. 388dfc9a3SLikun Gao * 488dfc9a3SLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 588dfc9a3SLikun Gao * copy of this software and associated documentation files (the "Software"), 688dfc9a3SLikun Gao * to deal in the Software without restriction, including without limitation 788dfc9a3SLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 888dfc9a3SLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 988dfc9a3SLikun Gao * Software is furnished to do so, subject to the following conditions: 1088dfc9a3SLikun Gao * 1188dfc9a3SLikun Gao * The above copyright notice and this permission notice shall be included in 1288dfc9a3SLikun Gao * all copies or substantial portions of the Software. 1388dfc9a3SLikun Gao * 1488dfc9a3SLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1588dfc9a3SLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1688dfc9a3SLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1788dfc9a3SLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1888dfc9a3SLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1988dfc9a3SLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2088dfc9a3SLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 2188dfc9a3SLikun Gao * 2288dfc9a3SLikun Gao */ 2388dfc9a3SLikun Gao 2488dfc9a3SLikun Gao #ifndef __AMDGPU_RLC_H__ 2588dfc9a3SLikun Gao #define __AMDGPU_RLC_H__ 2688dfc9a3SLikun Gao 2788dfc9a3SLikun Gao #include "clearstate_defs.h" 2888dfc9a3SLikun Gao 2952718c84SHawking Zhang /* firmware ID used in rlc toc */ 3052718c84SHawking Zhang typedef enum _FIRMWARE_ID_ { 3152718c84SHawking Zhang FIRMWARE_ID_INVALID = 0, 3252718c84SHawking Zhang FIRMWARE_ID_RLC_G_UCODE = 1, 3352718c84SHawking Zhang FIRMWARE_ID_RLC_TOC = 2, 3452718c84SHawking Zhang FIRMWARE_ID_RLCG_SCRATCH = 3, 3552718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_ARAM = 4, 3652718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_INDEX_ADDR = 5, 3752718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_INDEX_DATA = 6, 3852718c84SHawking Zhang FIRMWARE_ID_RLC_P_UCODE = 7, 3952718c84SHawking Zhang FIRMWARE_ID_RLC_V_UCODE = 8, 4052718c84SHawking Zhang FIRMWARE_ID_RLX6_UCODE = 9, 4152718c84SHawking Zhang FIRMWARE_ID_RLX6_DRAM_BOOT = 10, 4252718c84SHawking Zhang FIRMWARE_ID_GLOBAL_TAP_DELAYS = 11, 4352718c84SHawking Zhang FIRMWARE_ID_SE0_TAP_DELAYS = 12, 4452718c84SHawking Zhang FIRMWARE_ID_SE1_TAP_DELAYS = 13, 4552718c84SHawking Zhang FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS = 14, 4652718c84SHawking Zhang FIRMWARE_ID_SDMA0_UCODE = 15, 4752718c84SHawking Zhang FIRMWARE_ID_SDMA0_JT = 16, 4852718c84SHawking Zhang FIRMWARE_ID_SDMA1_UCODE = 17, 4952718c84SHawking Zhang FIRMWARE_ID_SDMA1_JT = 18, 5052718c84SHawking Zhang FIRMWARE_ID_CP_CE = 19, 5152718c84SHawking Zhang FIRMWARE_ID_CP_PFP = 20, 5252718c84SHawking Zhang FIRMWARE_ID_CP_ME = 21, 5352718c84SHawking Zhang FIRMWARE_ID_CP_MEC = 22, 5452718c84SHawking Zhang FIRMWARE_ID_CP_MES = 23, 5552718c84SHawking Zhang FIRMWARE_ID_MES_STACK = 24, 5652718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_DRAM_SR = 25, 5752718c84SHawking Zhang FIRMWARE_ID_RLCG_SCRATCH_SR = 26, 5852718c84SHawking Zhang FIRMWARE_ID_RLCP_SCRATCH_SR = 27, 5952718c84SHawking Zhang FIRMWARE_ID_RLCV_SCRATCH_SR = 28, 6052718c84SHawking Zhang FIRMWARE_ID_RLX6_DRAM_SR = 29, 6152718c84SHawking Zhang FIRMWARE_ID_SDMA0_PG_CONTEXT = 30, 6252718c84SHawking Zhang FIRMWARE_ID_SDMA1_PG_CONTEXT = 31, 6352718c84SHawking Zhang FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM = 32, 6452718c84SHawking Zhang FIRMWARE_ID_SE0_MUX_SELECT_RAM = 33, 6552718c84SHawking Zhang FIRMWARE_ID_SE1_MUX_SELECT_RAM = 34, 6652718c84SHawking Zhang FIRMWARE_ID_ACCUM_CTRL_RAM = 35, 6752718c84SHawking Zhang FIRMWARE_ID_RLCP_CAM = 36, 6852718c84SHawking Zhang FIRMWARE_ID_RLC_SPP_CAM_EXT = 37, 6952718c84SHawking Zhang FIRMWARE_ID_MAX = 38, 7052718c84SHawking Zhang } FIRMWARE_ID; 7152718c84SHawking Zhang 7252718c84SHawking Zhang typedef struct _RLC_TABLE_OF_CONTENT { 7352718c84SHawking Zhang union { 7452718c84SHawking Zhang unsigned int DW0; 7552718c84SHawking Zhang struct { 7652718c84SHawking Zhang unsigned int offset : 25; 7752718c84SHawking Zhang unsigned int id : 7; 7852718c84SHawking Zhang }; 7952718c84SHawking Zhang }; 8052718c84SHawking Zhang 8152718c84SHawking Zhang union { 8252718c84SHawking Zhang unsigned int DW1; 8352718c84SHawking Zhang struct { 8452718c84SHawking Zhang unsigned int load_at_boot : 1; 8552718c84SHawking Zhang unsigned int load_at_vddgfx : 1; 8652718c84SHawking Zhang unsigned int load_at_reset : 1; 8752718c84SHawking Zhang unsigned int memory_destination : 2; 8852718c84SHawking Zhang unsigned int vfflr_image_code : 4; 8952718c84SHawking Zhang unsigned int load_mode_direct : 1; 9052718c84SHawking Zhang unsigned int save_for_vddgfx : 1; 9152718c84SHawking Zhang unsigned int save_for_vfflr : 1; 9252718c84SHawking Zhang unsigned int reserved : 1; 9352718c84SHawking Zhang unsigned int signed_source : 1; 9452718c84SHawking Zhang unsigned int size : 18; 9552718c84SHawking Zhang }; 9652718c84SHawking Zhang }; 9752718c84SHawking Zhang 9852718c84SHawking Zhang union { 9952718c84SHawking Zhang unsigned int DW2; 10052718c84SHawking Zhang struct { 10152718c84SHawking Zhang unsigned int indirect_addr_reg : 16; 10252718c84SHawking Zhang unsigned int index : 16; 10352718c84SHawking Zhang }; 10452718c84SHawking Zhang }; 10552718c84SHawking Zhang 10652718c84SHawking Zhang union { 10752718c84SHawking Zhang unsigned int DW3; 10852718c84SHawking Zhang struct { 10952718c84SHawking Zhang unsigned int indirect_data_reg : 16; 11052718c84SHawking Zhang unsigned int indirect_start_offset : 16; 11152718c84SHawking Zhang }; 11252718c84SHawking Zhang }; 11352718c84SHawking Zhang } RLC_TABLE_OF_CONTENT; 11452718c84SHawking Zhang 11552718c84SHawking Zhang #define RLC_TOC_MAX_SIZE 64 11652718c84SHawking Zhang 11788dfc9a3SLikun Gao struct amdgpu_rlc_funcs { 118106c7d61SLikun Gao bool (*is_rlc_enabled)(struct amdgpu_device *adev); 119106c7d61SLikun Gao void (*set_safe_mode)(struct amdgpu_device *adev); 120106c7d61SLikun Gao void (*unset_safe_mode)(struct amdgpu_device *adev); 12188dfc9a3SLikun Gao int (*init)(struct amdgpu_device *adev); 122106c7d61SLikun Gao u32 (*get_csb_size)(struct amdgpu_device *adev); 123106c7d61SLikun Gao void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer); 124106c7d61SLikun Gao int (*get_cp_table_num)(struct amdgpu_device *adev); 12588dfc9a3SLikun Gao int (*resume)(struct amdgpu_device *adev); 12688dfc9a3SLikun Gao void (*stop)(struct amdgpu_device *adev); 12788dfc9a3SLikun Gao void (*reset)(struct amdgpu_device *adev); 12888dfc9a3SLikun Gao void (*start)(struct amdgpu_device *adev); 129460c484fSJacob He void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid); 1302e0cc4d4SMonk Liu void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v); 1312e0cc4d4SMonk Liu bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); 13288dfc9a3SLikun Gao }; 13388dfc9a3SLikun Gao 13488dfc9a3SLikun Gao struct amdgpu_rlc { 13588dfc9a3SLikun Gao /* for power gating */ 13688dfc9a3SLikun Gao struct amdgpu_bo *save_restore_obj; 13788dfc9a3SLikun Gao uint64_t save_restore_gpu_addr; 13888dfc9a3SLikun Gao volatile uint32_t *sr_ptr; 13988dfc9a3SLikun Gao const u32 *reg_list; 14088dfc9a3SLikun Gao u32 reg_list_size; 14188dfc9a3SLikun Gao /* for clear state */ 14288dfc9a3SLikun Gao struct amdgpu_bo *clear_state_obj; 14388dfc9a3SLikun Gao uint64_t clear_state_gpu_addr; 14488dfc9a3SLikun Gao volatile uint32_t *cs_ptr; 14588dfc9a3SLikun Gao const struct cs_section_def *cs_data; 14688dfc9a3SLikun Gao u32 clear_state_size; 14788dfc9a3SLikun Gao /* for cp tables */ 14888dfc9a3SLikun Gao struct amdgpu_bo *cp_table_obj; 14988dfc9a3SLikun Gao uint64_t cp_table_gpu_addr; 15088dfc9a3SLikun Gao volatile uint32_t *cp_table_ptr; 15188dfc9a3SLikun Gao u32 cp_table_size; 15288dfc9a3SLikun Gao 15388dfc9a3SLikun Gao /* safe mode for updating CG/PG state */ 15488dfc9a3SLikun Gao bool in_safe_mode; 15588dfc9a3SLikun Gao const struct amdgpu_rlc_funcs *funcs; 15688dfc9a3SLikun Gao 15788dfc9a3SLikun Gao /* for firmware data */ 15888dfc9a3SLikun Gao u32 save_and_restore_offset; 15988dfc9a3SLikun Gao u32 clear_state_descriptor_offset; 16088dfc9a3SLikun Gao u32 avail_scratch_ram_locations; 16188dfc9a3SLikun Gao u32 reg_restore_list_size; 16288dfc9a3SLikun Gao u32 reg_list_format_start; 16388dfc9a3SLikun Gao u32 reg_list_format_separate_start; 16488dfc9a3SLikun Gao u32 starting_offsets_start; 16588dfc9a3SLikun Gao u32 reg_list_format_size_bytes; 16688dfc9a3SLikun Gao u32 reg_list_size_bytes; 16788dfc9a3SLikun Gao u32 reg_list_format_direct_reg_list_length; 16888dfc9a3SLikun Gao u32 save_restore_list_cntl_size_bytes; 16988dfc9a3SLikun Gao u32 save_restore_list_gpm_size_bytes; 17088dfc9a3SLikun Gao u32 save_restore_list_srm_size_bytes; 17188dfc9a3SLikun Gao 17288dfc9a3SLikun Gao u32 *register_list_format; 17388dfc9a3SLikun Gao u32 *register_restore; 17488dfc9a3SLikun Gao u8 *save_restore_list_cntl; 17588dfc9a3SLikun Gao u8 *save_restore_list_gpm; 17688dfc9a3SLikun Gao u8 *save_restore_list_srm; 17788dfc9a3SLikun Gao 17888dfc9a3SLikun Gao bool is_rlc_v2_1; 1792beae55eSLe.Ma 1802beae55eSLe.Ma /* for rlc autoload */ 1812beae55eSLe.Ma struct amdgpu_bo *rlc_autoload_bo; 1822beae55eSLe.Ma u64 rlc_autoload_gpu_addr; 1832beae55eSLe.Ma void *rlc_autoload_ptr; 18452718c84SHawking Zhang 18552718c84SHawking Zhang /* rlc toc buffer */ 18652718c84SHawking Zhang struct amdgpu_bo *rlc_toc_bo; 18752718c84SHawking Zhang uint64_t rlc_toc_gpu_addr; 18852718c84SHawking Zhang void *rlc_toc_buf; 18988dfc9a3SLikun Gao }; 19088dfc9a3SLikun Gao 191106c7d61SLikun Gao void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev); 192106c7d61SLikun Gao void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev); 193106c7d61SLikun Gao int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws); 194106c7d61SLikun Gao int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev); 195106c7d61SLikun Gao int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev); 196106c7d61SLikun Gao void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev); 19788dfc9a3SLikun Gao void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev); 19888dfc9a3SLikun Gao 19988dfc9a3SLikun Gao #endif 200