188dfc9a3SLikun Gao /* 288dfc9a3SLikun Gao * Copyright 2014 Advanced Micro Devices, Inc. 388dfc9a3SLikun Gao * 488dfc9a3SLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 588dfc9a3SLikun Gao * copy of this software and associated documentation files (the "Software"), 688dfc9a3SLikun Gao * to deal in the Software without restriction, including without limitation 788dfc9a3SLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 888dfc9a3SLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 988dfc9a3SLikun Gao * Software is furnished to do so, subject to the following conditions: 1088dfc9a3SLikun Gao * 1188dfc9a3SLikun Gao * The above copyright notice and this permission notice shall be included in 1288dfc9a3SLikun Gao * all copies or substantial portions of the Software. 1388dfc9a3SLikun Gao * 1488dfc9a3SLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1588dfc9a3SLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1688dfc9a3SLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1788dfc9a3SLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1888dfc9a3SLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1988dfc9a3SLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2088dfc9a3SLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 2188dfc9a3SLikun Gao * 2288dfc9a3SLikun Gao */ 2388dfc9a3SLikun Gao 2488dfc9a3SLikun Gao #ifndef __AMDGPU_RLC_H__ 2588dfc9a3SLikun Gao #define __AMDGPU_RLC_H__ 2688dfc9a3SLikun Gao 2788dfc9a3SLikun Gao #include "clearstate_defs.h" 2888dfc9a3SLikun Gao 2988dfc9a3SLikun Gao struct amdgpu_rlc_funcs { 30106c7d61SLikun Gao bool (*is_rlc_enabled)(struct amdgpu_device *adev); 31106c7d61SLikun Gao void (*set_safe_mode)(struct amdgpu_device *adev); 32106c7d61SLikun Gao void (*unset_safe_mode)(struct amdgpu_device *adev); 3388dfc9a3SLikun Gao int (*init)(struct amdgpu_device *adev); 34106c7d61SLikun Gao u32 (*get_csb_size)(struct amdgpu_device *adev); 35106c7d61SLikun Gao void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer); 36106c7d61SLikun Gao int (*get_cp_table_num)(struct amdgpu_device *adev); 3788dfc9a3SLikun Gao int (*resume)(struct amdgpu_device *adev); 3888dfc9a3SLikun Gao void (*stop)(struct amdgpu_device *adev); 3988dfc9a3SLikun Gao void (*reset)(struct amdgpu_device *adev); 4088dfc9a3SLikun Gao void (*start)(struct amdgpu_device *adev); 4188dfc9a3SLikun Gao }; 4288dfc9a3SLikun Gao 4388dfc9a3SLikun Gao struct amdgpu_rlc { 4488dfc9a3SLikun Gao /* for power gating */ 4588dfc9a3SLikun Gao struct amdgpu_bo *save_restore_obj; 4688dfc9a3SLikun Gao uint64_t save_restore_gpu_addr; 4788dfc9a3SLikun Gao volatile uint32_t *sr_ptr; 4888dfc9a3SLikun Gao const u32 *reg_list; 4988dfc9a3SLikun Gao u32 reg_list_size; 5088dfc9a3SLikun Gao /* for clear state */ 5188dfc9a3SLikun Gao struct amdgpu_bo *clear_state_obj; 5288dfc9a3SLikun Gao uint64_t clear_state_gpu_addr; 5388dfc9a3SLikun Gao volatile uint32_t *cs_ptr; 5488dfc9a3SLikun Gao const struct cs_section_def *cs_data; 5588dfc9a3SLikun Gao u32 clear_state_size; 5688dfc9a3SLikun Gao /* for cp tables */ 5788dfc9a3SLikun Gao struct amdgpu_bo *cp_table_obj; 5888dfc9a3SLikun Gao uint64_t cp_table_gpu_addr; 5988dfc9a3SLikun Gao volatile uint32_t *cp_table_ptr; 6088dfc9a3SLikun Gao u32 cp_table_size; 6188dfc9a3SLikun Gao 6288dfc9a3SLikun Gao /* safe mode for updating CG/PG state */ 6388dfc9a3SLikun Gao bool in_safe_mode; 6488dfc9a3SLikun Gao const struct amdgpu_rlc_funcs *funcs; 6588dfc9a3SLikun Gao 6688dfc9a3SLikun Gao /* for firmware data */ 6788dfc9a3SLikun Gao u32 save_and_restore_offset; 6888dfc9a3SLikun Gao u32 clear_state_descriptor_offset; 6988dfc9a3SLikun Gao u32 avail_scratch_ram_locations; 7088dfc9a3SLikun Gao u32 reg_restore_list_size; 7188dfc9a3SLikun Gao u32 reg_list_format_start; 7288dfc9a3SLikun Gao u32 reg_list_format_separate_start; 7388dfc9a3SLikun Gao u32 starting_offsets_start; 7488dfc9a3SLikun Gao u32 reg_list_format_size_bytes; 7588dfc9a3SLikun Gao u32 reg_list_size_bytes; 7688dfc9a3SLikun Gao u32 reg_list_format_direct_reg_list_length; 7788dfc9a3SLikun Gao u32 save_restore_list_cntl_size_bytes; 7888dfc9a3SLikun Gao u32 save_restore_list_gpm_size_bytes; 7988dfc9a3SLikun Gao u32 save_restore_list_srm_size_bytes; 8088dfc9a3SLikun Gao 8188dfc9a3SLikun Gao u32 *register_list_format; 8288dfc9a3SLikun Gao u32 *register_restore; 8388dfc9a3SLikun Gao u8 *save_restore_list_cntl; 8488dfc9a3SLikun Gao u8 *save_restore_list_gpm; 8588dfc9a3SLikun Gao u8 *save_restore_list_srm; 8688dfc9a3SLikun Gao 8788dfc9a3SLikun Gao bool is_rlc_v2_1; 882beae55eSLe.Ma 892beae55eSLe.Ma /* for rlc autoload */ 902beae55eSLe.Ma struct amdgpu_bo *rlc_autoload_bo; 912beae55eSLe.Ma u64 rlc_autoload_gpu_addr; 922beae55eSLe.Ma void *rlc_autoload_ptr; 9388dfc9a3SLikun Gao }; 9488dfc9a3SLikun Gao 95106c7d61SLikun Gao void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev); 96106c7d61SLikun Gao void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev); 97106c7d61SLikun Gao int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws); 98106c7d61SLikun Gao int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev); 99106c7d61SLikun Gao int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev); 100106c7d61SLikun Gao void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev); 10188dfc9a3SLikun Gao void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev); 10288dfc9a3SLikun Gao 10388dfc9a3SLikun Gao #endif 104