188dfc9a3SLikun Gao /* 288dfc9a3SLikun Gao * Copyright 2014 Advanced Micro Devices, Inc. 388dfc9a3SLikun Gao * 488dfc9a3SLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 588dfc9a3SLikun Gao * copy of this software and associated documentation files (the "Software"), 688dfc9a3SLikun Gao * to deal in the Software without restriction, including without limitation 788dfc9a3SLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 888dfc9a3SLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 988dfc9a3SLikun Gao * Software is furnished to do so, subject to the following conditions: 1088dfc9a3SLikun Gao * 1188dfc9a3SLikun Gao * The above copyright notice and this permission notice shall be included in 1288dfc9a3SLikun Gao * all copies or substantial portions of the Software. 1388dfc9a3SLikun Gao * 1488dfc9a3SLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1588dfc9a3SLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1688dfc9a3SLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1788dfc9a3SLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1888dfc9a3SLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1988dfc9a3SLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2088dfc9a3SLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 2188dfc9a3SLikun Gao * 2288dfc9a3SLikun Gao */ 2388dfc9a3SLikun Gao 2488dfc9a3SLikun Gao #ifndef __AMDGPU_RLC_H__ 2588dfc9a3SLikun Gao #define __AMDGPU_RLC_H__ 2688dfc9a3SLikun Gao 2788dfc9a3SLikun Gao #include "clearstate_defs.h" 2888dfc9a3SLikun Gao 29*8ed49dd1SVictor Lu #define AMDGPU_MAX_RLC_INSTANCES 8 30*8ed49dd1SVictor Lu 3152718c84SHawking Zhang /* firmware ID used in rlc toc */ 3252718c84SHawking Zhang typedef enum _FIRMWARE_ID_ { 3352718c84SHawking Zhang FIRMWARE_ID_INVALID = 0, 3452718c84SHawking Zhang FIRMWARE_ID_RLC_G_UCODE = 1, 3552718c84SHawking Zhang FIRMWARE_ID_RLC_TOC = 2, 3652718c84SHawking Zhang FIRMWARE_ID_RLCG_SCRATCH = 3, 3752718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_ARAM = 4, 3852718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_INDEX_ADDR = 5, 3952718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_INDEX_DATA = 6, 4052718c84SHawking Zhang FIRMWARE_ID_RLC_P_UCODE = 7, 4152718c84SHawking Zhang FIRMWARE_ID_RLC_V_UCODE = 8, 4252718c84SHawking Zhang FIRMWARE_ID_RLX6_UCODE = 9, 4352718c84SHawking Zhang FIRMWARE_ID_RLX6_DRAM_BOOT = 10, 4452718c84SHawking Zhang FIRMWARE_ID_GLOBAL_TAP_DELAYS = 11, 4552718c84SHawking Zhang FIRMWARE_ID_SE0_TAP_DELAYS = 12, 4652718c84SHawking Zhang FIRMWARE_ID_SE1_TAP_DELAYS = 13, 4752718c84SHawking Zhang FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS = 14, 4852718c84SHawking Zhang FIRMWARE_ID_SDMA0_UCODE = 15, 4952718c84SHawking Zhang FIRMWARE_ID_SDMA0_JT = 16, 5052718c84SHawking Zhang FIRMWARE_ID_SDMA1_UCODE = 17, 5152718c84SHawking Zhang FIRMWARE_ID_SDMA1_JT = 18, 5252718c84SHawking Zhang FIRMWARE_ID_CP_CE = 19, 5352718c84SHawking Zhang FIRMWARE_ID_CP_PFP = 20, 5452718c84SHawking Zhang FIRMWARE_ID_CP_ME = 21, 5552718c84SHawking Zhang FIRMWARE_ID_CP_MEC = 22, 5652718c84SHawking Zhang FIRMWARE_ID_CP_MES = 23, 5752718c84SHawking Zhang FIRMWARE_ID_MES_STACK = 24, 5852718c84SHawking Zhang FIRMWARE_ID_RLC_SRM_DRAM_SR = 25, 5952718c84SHawking Zhang FIRMWARE_ID_RLCG_SCRATCH_SR = 26, 6052718c84SHawking Zhang FIRMWARE_ID_RLCP_SCRATCH_SR = 27, 6152718c84SHawking Zhang FIRMWARE_ID_RLCV_SCRATCH_SR = 28, 6252718c84SHawking Zhang FIRMWARE_ID_RLX6_DRAM_SR = 29, 6352718c84SHawking Zhang FIRMWARE_ID_SDMA0_PG_CONTEXT = 30, 6452718c84SHawking Zhang FIRMWARE_ID_SDMA1_PG_CONTEXT = 31, 6552718c84SHawking Zhang FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM = 32, 6652718c84SHawking Zhang FIRMWARE_ID_SE0_MUX_SELECT_RAM = 33, 6752718c84SHawking Zhang FIRMWARE_ID_SE1_MUX_SELECT_RAM = 34, 6852718c84SHawking Zhang FIRMWARE_ID_ACCUM_CTRL_RAM = 35, 6952718c84SHawking Zhang FIRMWARE_ID_RLCP_CAM = 36, 7052718c84SHawking Zhang FIRMWARE_ID_RLC_SPP_CAM_EXT = 37, 7152718c84SHawking Zhang FIRMWARE_ID_MAX = 38, 7252718c84SHawking Zhang } FIRMWARE_ID; 7352718c84SHawking Zhang 7489466f49SLikun Gao typedef enum _SOC21_FIRMWARE_ID_ { 7589466f49SLikun Gao SOC21_FIRMWARE_ID_INVALID = 0, 7689466f49SLikun Gao SOC21_FIRMWARE_ID_RLC_G_UCODE = 1, 7789466f49SLikun Gao SOC21_FIRMWARE_ID_RLC_TOC = 2, 7889466f49SLikun Gao SOC21_FIRMWARE_ID_RLCG_SCRATCH = 3, 7989466f49SLikun Gao SOC21_FIRMWARE_ID_RLC_SRM_ARAM = 4, 8089466f49SLikun Gao SOC21_FIRMWARE_ID_RLC_P_UCODE = 5, 8189466f49SLikun Gao SOC21_FIRMWARE_ID_RLC_V_UCODE = 6, 8289466f49SLikun Gao SOC21_FIRMWARE_ID_RLX6_UCODE = 7, 8389466f49SLikun Gao SOC21_FIRMWARE_ID_RLX6_UCODE_CORE1 = 8, 8489466f49SLikun Gao SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT = 9, 8589466f49SLikun Gao SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1 = 10, 8689466f49SLikun Gao SOC21_FIRMWARE_ID_SDMA_UCODE_TH0 = 11, 8789466f49SLikun Gao SOC21_FIRMWARE_ID_SDMA_UCODE_TH1 = 12, 8889466f49SLikun Gao SOC21_FIRMWARE_ID_CP_PFP = 13, 8989466f49SLikun Gao SOC21_FIRMWARE_ID_CP_ME = 14, 9089466f49SLikun Gao SOC21_FIRMWARE_ID_CP_MEC = 15, 9189466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MES_P0 = 16, 9289466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MES_P1 = 17, 9389466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_PFP = 18, 9489466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_ME = 19, 9589466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MEC = 20, 9689466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MES_P0_STACK = 21, 9789466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MES_P1_STACK = 22, 9889466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK = 23, 9989466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK = 24, 10089466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_ME_P0_STACK = 25, 10189466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_ME_P1_STACK = 26, 10289466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK = 27, 10389466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK = 28, 10489466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK = 29, 10589466f49SLikun Gao SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK = 30, 10689466f49SLikun Gao SOC21_FIRMWARE_ID_RLC_SRM_DRAM_SR = 31, 10789466f49SLikun Gao SOC21_FIRMWARE_ID_RLCG_SCRATCH_SR = 32, 10889466f49SLikun Gao SOC21_FIRMWARE_ID_RLCP_SCRATCH_SR = 33, 10989466f49SLikun Gao SOC21_FIRMWARE_ID_RLCV_SCRATCH_SR = 34, 11089466f49SLikun Gao SOC21_FIRMWARE_ID_RLX6_DRAM_SR = 35, 11189466f49SLikun Gao SOC21_FIRMWARE_ID_RLX6_DRAM_SR_CORE1 = 36, 11289466f49SLikun Gao SOC21_FIRMWARE_ID_MAX = 37 11389466f49SLikun Gao } SOC21_FIRMWARE_ID; 11489466f49SLikun Gao 11552718c84SHawking Zhang typedef struct _RLC_TABLE_OF_CONTENT { 11652718c84SHawking Zhang union { 11752718c84SHawking Zhang unsigned int DW0; 11852718c84SHawking Zhang struct { 11952718c84SHawking Zhang unsigned int offset : 25; 12052718c84SHawking Zhang unsigned int id : 7; 12152718c84SHawking Zhang }; 12252718c84SHawking Zhang }; 12352718c84SHawking Zhang 12452718c84SHawking Zhang union { 12552718c84SHawking Zhang unsigned int DW1; 12652718c84SHawking Zhang struct { 12752718c84SHawking Zhang unsigned int load_at_boot : 1; 12852718c84SHawking Zhang unsigned int load_at_vddgfx : 1; 12952718c84SHawking Zhang unsigned int load_at_reset : 1; 13052718c84SHawking Zhang unsigned int memory_destination : 2; 13152718c84SHawking Zhang unsigned int vfflr_image_code : 4; 13252718c84SHawking Zhang unsigned int load_mode_direct : 1; 13352718c84SHawking Zhang unsigned int save_for_vddgfx : 1; 13452718c84SHawking Zhang unsigned int save_for_vfflr : 1; 13552718c84SHawking Zhang unsigned int reserved : 1; 13652718c84SHawking Zhang unsigned int signed_source : 1; 13752718c84SHawking Zhang unsigned int size : 18; 13852718c84SHawking Zhang }; 13952718c84SHawking Zhang }; 14052718c84SHawking Zhang 14152718c84SHawking Zhang union { 14252718c84SHawking Zhang unsigned int DW2; 14352718c84SHawking Zhang struct { 14452718c84SHawking Zhang unsigned int indirect_addr_reg : 16; 14552718c84SHawking Zhang unsigned int index : 16; 14652718c84SHawking Zhang }; 14752718c84SHawking Zhang }; 14852718c84SHawking Zhang 14952718c84SHawking Zhang union { 15052718c84SHawking Zhang unsigned int DW3; 15152718c84SHawking Zhang struct { 15252718c84SHawking Zhang unsigned int indirect_data_reg : 16; 15352718c84SHawking Zhang unsigned int indirect_start_offset : 16; 15452718c84SHawking Zhang }; 15552718c84SHawking Zhang }; 15652718c84SHawking Zhang } RLC_TABLE_OF_CONTENT; 15752718c84SHawking Zhang 15852718c84SHawking Zhang #define RLC_TOC_MAX_SIZE 64 15952718c84SHawking Zhang 16088dfc9a3SLikun Gao struct amdgpu_rlc_funcs { 161106c7d61SLikun Gao bool (*is_rlc_enabled)(struct amdgpu_device *adev); 16286b20703SLe Ma void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id); 16386b20703SLe Ma void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id); 16488dfc9a3SLikun Gao int (*init)(struct amdgpu_device *adev); 165106c7d61SLikun Gao u32 (*get_csb_size)(struct amdgpu_device *adev); 166106c7d61SLikun Gao void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer); 167106c7d61SLikun Gao int (*get_cp_table_num)(struct amdgpu_device *adev); 16888dfc9a3SLikun Gao int (*resume)(struct amdgpu_device *adev); 16988dfc9a3SLikun Gao void (*stop)(struct amdgpu_device *adev); 17088dfc9a3SLikun Gao void (*reset)(struct amdgpu_device *adev); 17188dfc9a3SLikun Gao void (*start)(struct amdgpu_device *adev); 172460c484fSJacob He void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid); 1732e0cc4d4SMonk Liu bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); 17488dfc9a3SLikun Gao }; 17588dfc9a3SLikun Gao 176b12252b0SHawking Zhang struct amdgpu_rlcg_reg_access_ctrl { 177b12252b0SHawking Zhang uint32_t scratch_reg0; 178b12252b0SHawking Zhang uint32_t scratch_reg1; 179b12252b0SHawking Zhang uint32_t scratch_reg2; 180b12252b0SHawking Zhang uint32_t scratch_reg3; 181b12252b0SHawking Zhang uint32_t grbm_cntl; 182b12252b0SHawking Zhang uint32_t grbm_idx; 183b12252b0SHawking Zhang uint32_t spare_int; 184b12252b0SHawking Zhang }; 185b12252b0SHawking Zhang 18688dfc9a3SLikun Gao struct amdgpu_rlc { 18788dfc9a3SLikun Gao /* for power gating */ 18888dfc9a3SLikun Gao struct amdgpu_bo *save_restore_obj; 18988dfc9a3SLikun Gao uint64_t save_restore_gpu_addr; 19088dfc9a3SLikun Gao volatile uint32_t *sr_ptr; 19188dfc9a3SLikun Gao const u32 *reg_list; 19288dfc9a3SLikun Gao u32 reg_list_size; 19388dfc9a3SLikun Gao /* for clear state */ 19488dfc9a3SLikun Gao struct amdgpu_bo *clear_state_obj; 19588dfc9a3SLikun Gao uint64_t clear_state_gpu_addr; 19688dfc9a3SLikun Gao volatile uint32_t *cs_ptr; 19788dfc9a3SLikun Gao const struct cs_section_def *cs_data; 19888dfc9a3SLikun Gao u32 clear_state_size; 19988dfc9a3SLikun Gao /* for cp tables */ 20088dfc9a3SLikun Gao struct amdgpu_bo *cp_table_obj; 20188dfc9a3SLikun Gao uint64_t cp_table_gpu_addr; 20288dfc9a3SLikun Gao volatile uint32_t *cp_table_ptr; 20388dfc9a3SLikun Gao u32 cp_table_size; 20488dfc9a3SLikun Gao 20588dfc9a3SLikun Gao /* safe mode for updating CG/PG state */ 206*8ed49dd1SVictor Lu bool in_safe_mode[AMDGPU_MAX_RLC_INSTANCES]; 20788dfc9a3SLikun Gao const struct amdgpu_rlc_funcs *funcs; 20888dfc9a3SLikun Gao 20988dfc9a3SLikun Gao /* for firmware data */ 21088dfc9a3SLikun Gao u32 save_and_restore_offset; 21188dfc9a3SLikun Gao u32 clear_state_descriptor_offset; 21288dfc9a3SLikun Gao u32 avail_scratch_ram_locations; 21388dfc9a3SLikun Gao u32 reg_restore_list_size; 21488dfc9a3SLikun Gao u32 reg_list_format_start; 21588dfc9a3SLikun Gao u32 reg_list_format_separate_start; 21688dfc9a3SLikun Gao u32 starting_offsets_start; 21788dfc9a3SLikun Gao u32 reg_list_format_size_bytes; 21888dfc9a3SLikun Gao u32 reg_list_size_bytes; 21988dfc9a3SLikun Gao u32 reg_list_format_direct_reg_list_length; 22088dfc9a3SLikun Gao u32 save_restore_list_cntl_size_bytes; 22188dfc9a3SLikun Gao u32 save_restore_list_gpm_size_bytes; 22288dfc9a3SLikun Gao u32 save_restore_list_srm_size_bytes; 223843c7eb2SLikun Gao u32 rlc_iram_ucode_size_bytes; 224843c7eb2SLikun Gao u32 rlc_dram_ucode_size_bytes; 225550bb28eSLikun Gao u32 rlcp_ucode_size_bytes; 226550bb28eSLikun Gao u32 rlcv_ucode_size_bytes; 2272207efddSChengming Gui u32 global_tap_delays_ucode_size_bytes; 2282207efddSChengming Gui u32 se0_tap_delays_ucode_size_bytes; 2292207efddSChengming Gui u32 se1_tap_delays_ucode_size_bytes; 2302207efddSChengming Gui u32 se2_tap_delays_ucode_size_bytes; 2312207efddSChengming Gui u32 se3_tap_delays_ucode_size_bytes; 23288dfc9a3SLikun Gao 23388dfc9a3SLikun Gao u32 *register_list_format; 23488dfc9a3SLikun Gao u32 *register_restore; 23588dfc9a3SLikun Gao u8 *save_restore_list_cntl; 23688dfc9a3SLikun Gao u8 *save_restore_list_gpm; 23788dfc9a3SLikun Gao u8 *save_restore_list_srm; 238843c7eb2SLikun Gao u8 *rlc_iram_ucode; 239843c7eb2SLikun Gao u8 *rlc_dram_ucode; 240550bb28eSLikun Gao u8 *rlcp_ucode; 241550bb28eSLikun Gao u8 *rlcv_ucode; 2422207efddSChengming Gui u8 *global_tap_delays_ucode; 2432207efddSChengming Gui u8 *se0_tap_delays_ucode; 2442207efddSChengming Gui u8 *se1_tap_delays_ucode; 2452207efddSChengming Gui u8 *se2_tap_delays_ucode; 2462207efddSChengming Gui u8 *se3_tap_delays_ucode; 24788dfc9a3SLikun Gao 24888dfc9a3SLikun Gao bool is_rlc_v2_1; 2492beae55eSLe.Ma 2502beae55eSLe.Ma /* for rlc autoload */ 2512beae55eSLe.Ma struct amdgpu_bo *rlc_autoload_bo; 2522beae55eSLe.Ma u64 rlc_autoload_gpu_addr; 2532beae55eSLe.Ma void *rlc_autoload_ptr; 25452718c84SHawking Zhang 25552718c84SHawking Zhang /* rlc toc buffer */ 25652718c84SHawking Zhang struct amdgpu_bo *rlc_toc_bo; 25752718c84SHawking Zhang uint64_t rlc_toc_gpu_addr; 25852718c84SHawking Zhang void *rlc_toc_buf; 259b12252b0SHawking Zhang 260b12252b0SHawking Zhang bool rlcg_reg_access_supported; 261b12252b0SHawking Zhang /* registers for rlcg indirect reg access */ 262*8ed49dd1SVictor Lu struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES]; 26388dfc9a3SLikun Gao }; 26488dfc9a3SLikun Gao 26586b20703SLe Ma void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id); 26686b20703SLe Ma void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id); 267106c7d61SLikun Gao int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws); 268106c7d61SLikun Gao int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev); 269106c7d61SLikun Gao int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev); 270106c7d61SLikun Gao void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev); 27188dfc9a3SLikun Gao void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev); 27204fa38ccSHawking Zhang int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev, 27304fa38ccSHawking Zhang uint16_t version_major, 27404fa38ccSHawking Zhang uint16_t version_minor); 27588dfc9a3SLikun Gao #endif 276