1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 30 /* max number of rings */ 31 #define AMDGPU_MAX_RINGS 18 32 #define AMDGPU_MAX_GFX_RINGS 1 33 #define AMDGPU_MAX_COMPUTE_RINGS 8 34 #define AMDGPU_MAX_VCE_RINGS 3 35 #define AMDGPU_MAX_UVD_ENC_RINGS 2 36 37 /* some special values for the owner field */ 38 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 39 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 40 41 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 42 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 43 44 enum amdgpu_ring_type { 45 AMDGPU_RING_TYPE_GFX, 46 AMDGPU_RING_TYPE_COMPUTE, 47 AMDGPU_RING_TYPE_SDMA, 48 AMDGPU_RING_TYPE_UVD, 49 AMDGPU_RING_TYPE_VCE, 50 AMDGPU_RING_TYPE_KIQ, 51 AMDGPU_RING_TYPE_UVD_ENC, 52 AMDGPU_RING_TYPE_VCN_DEC, 53 AMDGPU_RING_TYPE_VCN_ENC 54 }; 55 56 struct amdgpu_device; 57 struct amdgpu_ring; 58 struct amdgpu_ib; 59 struct amdgpu_cs_parser; 60 struct amdgpu_job; 61 62 /* 63 * Fences. 64 */ 65 struct amdgpu_fence_driver { 66 uint64_t gpu_addr; 67 volatile uint32_t *cpu_addr; 68 /* sync_seq is protected by ring emission lock */ 69 uint32_t sync_seq; 70 atomic_t last_seq; 71 bool initialized; 72 struct amdgpu_irq_src *irq_src; 73 unsigned irq_type; 74 struct timer_list fallback_timer; 75 unsigned num_fences_mask; 76 spinlock_t lock; 77 struct dma_fence **fences; 78 }; 79 80 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 81 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 82 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 83 84 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 85 unsigned num_hw_submission); 86 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 87 struct amdgpu_irq_src *irq_src, 88 unsigned irq_type); 89 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 90 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 91 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence); 92 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); 93 void amdgpu_fence_process(struct amdgpu_ring *ring); 94 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 95 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 96 uint32_t wait_seq, 97 signed long timeout); 98 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 99 100 /* 101 * Rings. 102 */ 103 104 /* provided by hw blocks that expose a ring buffer for commands */ 105 struct amdgpu_ring_funcs { 106 enum amdgpu_ring_type type; 107 uint32_t align_mask; 108 u32 nop; 109 bool support_64bit_ptrs; 110 unsigned vmhub; 111 112 /* ring read/write ptr handling */ 113 u64 (*get_rptr)(struct amdgpu_ring *ring); 114 u64 (*get_wptr)(struct amdgpu_ring *ring); 115 void (*set_wptr)(struct amdgpu_ring *ring); 116 /* validating and patching of IBs */ 117 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 118 /* constants to calculate how many DW are needed for an emit */ 119 unsigned emit_frame_size; 120 unsigned emit_ib_size; 121 /* command emit functions */ 122 void (*emit_ib)(struct amdgpu_ring *ring, 123 struct amdgpu_ib *ib, 124 unsigned vmid, bool ctx_switch); 125 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 126 uint64_t seq, unsigned flags); 127 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 128 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 129 uint64_t pd_addr); 130 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 131 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 132 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 133 uint32_t gds_base, uint32_t gds_size, 134 uint32_t gws_base, uint32_t gws_size, 135 uint32_t oa_base, uint32_t oa_size); 136 /* testing functions */ 137 int (*test_ring)(struct amdgpu_ring *ring); 138 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 139 /* insert NOP packets */ 140 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 141 void (*insert_start)(struct amdgpu_ring *ring); 142 void (*insert_end)(struct amdgpu_ring *ring); 143 /* pad the indirect buffer to the necessary number of dw */ 144 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 145 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 146 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 147 /* note usage for clock and power gating */ 148 void (*begin_use)(struct amdgpu_ring *ring); 149 void (*end_use)(struct amdgpu_ring *ring); 150 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 151 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 152 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); 153 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 154 void (*emit_tmz)(struct amdgpu_ring *ring, bool start); 155 /* priority functions */ 156 void (*set_priority) (struct amdgpu_ring *ring, 157 enum drm_sched_priority priority); 158 }; 159 160 struct amdgpu_ring { 161 struct amdgpu_device *adev; 162 const struct amdgpu_ring_funcs *funcs; 163 struct amdgpu_fence_driver fence_drv; 164 struct drm_gpu_scheduler sched; 165 struct list_head lru_list; 166 167 struct amdgpu_bo *ring_obj; 168 volatile uint32_t *ring; 169 unsigned rptr_offs; 170 u64 wptr; 171 u64 wptr_old; 172 unsigned ring_size; 173 unsigned max_dw; 174 int count_dw; 175 uint64_t gpu_addr; 176 uint64_t ptr_mask; 177 uint32_t buf_mask; 178 bool ready; 179 u32 idx; 180 u32 me; 181 u32 pipe; 182 u32 queue; 183 struct amdgpu_bo *mqd_obj; 184 uint64_t mqd_gpu_addr; 185 void *mqd_ptr; 186 uint64_t eop_gpu_addr; 187 u32 doorbell_index; 188 bool use_doorbell; 189 bool use_pollmem; 190 unsigned wptr_offs; 191 unsigned fence_offs; 192 uint64_t current_ctx; 193 char name[16]; 194 unsigned cond_exe_offs; 195 u64 cond_exe_gpu_addr; 196 volatile u32 *cond_exe_cpu_addr; 197 unsigned vm_inv_eng; 198 bool has_compute_vm_bug; 199 200 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; 201 struct mutex priority_mutex; 202 /* protected by priority_mutex */ 203 int priority; 204 205 #if defined(CONFIG_DEBUG_FS) 206 struct dentry *ent; 207 #endif 208 }; 209 210 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 211 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 212 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 213 void amdgpu_ring_commit(struct amdgpu_ring *ring); 214 void amdgpu_ring_undo(struct amdgpu_ring *ring); 215 void amdgpu_ring_priority_get(struct amdgpu_ring *ring, 216 enum drm_sched_priority priority); 217 void amdgpu_ring_priority_put(struct amdgpu_ring *ring, 218 enum drm_sched_priority priority); 219 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 220 unsigned ring_size, struct amdgpu_irq_src *irq_src, 221 unsigned irq_type); 222 void amdgpu_ring_fini(struct amdgpu_ring *ring); 223 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, 224 int *blacklist, int num_blacklist, 225 bool lru_pipe_order, struct amdgpu_ring **ring); 226 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring); 227 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 228 { 229 int i = 0; 230 while (i <= ring->buf_mask) 231 ring->ring[i++] = ring->funcs->nop; 232 233 } 234 235 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 236 { 237 if (ring->count_dw <= 0) 238 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 239 ring->ring[ring->wptr++ & ring->buf_mask] = v; 240 ring->wptr &= ring->ptr_mask; 241 ring->count_dw--; 242 } 243 244 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 245 void *src, int count_dw) 246 { 247 unsigned occupied, chunk1, chunk2; 248 void *dst; 249 250 if (unlikely(ring->count_dw < count_dw)) 251 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 252 253 occupied = ring->wptr & ring->buf_mask; 254 dst = (void *)&ring->ring[occupied]; 255 chunk1 = ring->buf_mask + 1 - occupied; 256 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 257 chunk2 = count_dw - chunk1; 258 chunk1 <<= 2; 259 chunk2 <<= 2; 260 261 if (chunk1) 262 memcpy(dst, src, chunk1); 263 264 if (chunk2) { 265 src += chunk1; 266 dst = (void *)ring->ring; 267 memcpy(dst, src, chunk2); 268 } 269 270 ring->wptr += count_dw; 271 ring->wptr &= ring->ptr_mask; 272 ring->count_dw -= count_dw; 273 } 274 275 #endif 276