1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include "gpu_scheduler.h" 28 29 /* max number of rings */ 30 #define AMDGPU_MAX_RINGS 18 31 #define AMDGPU_MAX_GFX_RINGS 1 32 #define AMDGPU_MAX_COMPUTE_RINGS 8 33 #define AMDGPU_MAX_VCE_RINGS 3 34 #define AMDGPU_MAX_UVD_ENC_RINGS 2 35 36 /* some special values for the owner field */ 37 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 38 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 39 40 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 41 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 42 43 enum amdgpu_ring_type { 44 AMDGPU_RING_TYPE_GFX, 45 AMDGPU_RING_TYPE_COMPUTE, 46 AMDGPU_RING_TYPE_SDMA, 47 AMDGPU_RING_TYPE_UVD, 48 AMDGPU_RING_TYPE_VCE, 49 AMDGPU_RING_TYPE_KIQ, 50 AMDGPU_RING_TYPE_UVD_ENC 51 }; 52 53 struct amdgpu_device; 54 struct amdgpu_ring; 55 struct amdgpu_ib; 56 struct amdgpu_cs_parser; 57 58 /* 59 * Fences. 60 */ 61 struct amdgpu_fence_driver { 62 uint64_t gpu_addr; 63 volatile uint32_t *cpu_addr; 64 /* sync_seq is protected by ring emission lock */ 65 uint32_t sync_seq; 66 atomic_t last_seq; 67 bool initialized; 68 struct amdgpu_irq_src *irq_src; 69 unsigned irq_type; 70 struct timer_list fallback_timer; 71 unsigned num_fences_mask; 72 spinlock_t lock; 73 struct dma_fence **fences; 74 }; 75 76 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 77 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 78 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 79 80 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 81 unsigned num_hw_submission); 82 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 83 struct amdgpu_irq_src *irq_src, 84 unsigned irq_type); 85 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 86 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 87 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence); 88 void amdgpu_fence_process(struct amdgpu_ring *ring); 89 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 90 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 91 92 /* 93 * Rings. 94 */ 95 96 /* provided by hw blocks that expose a ring buffer for commands */ 97 struct amdgpu_ring_funcs { 98 enum amdgpu_ring_type type; 99 uint32_t align_mask; 100 u32 nop; 101 bool support_64bit_ptrs; 102 unsigned vmhub; 103 104 /* ring read/write ptr handling */ 105 u64 (*get_rptr)(struct amdgpu_ring *ring); 106 u64 (*get_wptr)(struct amdgpu_ring *ring); 107 void (*set_wptr)(struct amdgpu_ring *ring); 108 /* validating and patching of IBs */ 109 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 110 /* constants to calculate how many DW are needed for an emit */ 111 unsigned emit_frame_size; 112 unsigned emit_ib_size; 113 /* command emit functions */ 114 void (*emit_ib)(struct amdgpu_ring *ring, 115 struct amdgpu_ib *ib, 116 unsigned vm_id, bool ctx_switch); 117 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 118 uint64_t seq, unsigned flags); 119 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 120 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 121 uint64_t pd_addr); 122 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 123 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 124 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 125 uint32_t gds_base, uint32_t gds_size, 126 uint32_t gws_base, uint32_t gws_size, 127 uint32_t oa_base, uint32_t oa_size); 128 /* testing functions */ 129 int (*test_ring)(struct amdgpu_ring *ring); 130 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 131 /* insert NOP packets */ 132 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 133 void (*insert_end)(struct amdgpu_ring *ring); 134 /* pad the indirect buffer to the necessary number of dw */ 135 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 136 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 137 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 138 /* note usage for clock and power gating */ 139 void (*begin_use)(struct amdgpu_ring *ring); 140 void (*end_use)(struct amdgpu_ring *ring); 141 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 142 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 143 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); 144 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 145 }; 146 147 struct amdgpu_ring { 148 struct amdgpu_device *adev; 149 const struct amdgpu_ring_funcs *funcs; 150 struct amdgpu_fence_driver fence_drv; 151 struct amd_gpu_scheduler sched; 152 153 struct amdgpu_bo *ring_obj; 154 volatile uint32_t *ring; 155 unsigned rptr_offs; 156 u64 wptr; 157 u64 wptr_old; 158 unsigned ring_size; 159 unsigned max_dw; 160 int count_dw; 161 uint64_t gpu_addr; 162 uint64_t ptr_mask; 163 uint32_t buf_mask; 164 bool ready; 165 u32 idx; 166 u32 me; 167 u32 pipe; 168 u32 queue; 169 struct amdgpu_bo *mqd_obj; 170 uint64_t mqd_gpu_addr; 171 void *mqd_ptr; 172 uint64_t eop_gpu_addr; 173 u32 doorbell_index; 174 bool use_doorbell; 175 unsigned wptr_offs; 176 unsigned fence_offs; 177 uint64_t current_ctx; 178 char name[16]; 179 unsigned cond_exe_offs; 180 u64 cond_exe_gpu_addr; 181 volatile u32 *cond_exe_cpu_addr; 182 unsigned vm_inv_eng; 183 #if defined(CONFIG_DEBUG_FS) 184 struct dentry *ent; 185 #endif 186 }; 187 188 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 189 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 190 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 191 void amdgpu_ring_commit(struct amdgpu_ring *ring); 192 void amdgpu_ring_undo(struct amdgpu_ring *ring); 193 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 194 unsigned ring_size, struct amdgpu_irq_src *irq_src, 195 unsigned irq_type); 196 void amdgpu_ring_fini(struct amdgpu_ring *ring); 197 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 198 { 199 int i = 0; 200 while (i <= ring->buf_mask) 201 ring->ring[i++] = ring->funcs->nop; 202 203 } 204 205 #endif 206