1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 31 /* max number of rings */ 32 #define AMDGPU_MAX_RINGS 21 33 #define AMDGPU_MAX_GFX_RINGS 1 34 #define AMDGPU_MAX_COMPUTE_RINGS 8 35 #define AMDGPU_MAX_VCE_RINGS 3 36 #define AMDGPU_MAX_UVD_ENC_RINGS 2 37 38 /* some special values for the owner field */ 39 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 40 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 41 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 42 43 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 44 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 45 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 46 47 enum amdgpu_ring_type { 48 AMDGPU_RING_TYPE_GFX, 49 AMDGPU_RING_TYPE_COMPUTE, 50 AMDGPU_RING_TYPE_SDMA, 51 AMDGPU_RING_TYPE_UVD, 52 AMDGPU_RING_TYPE_VCE, 53 AMDGPU_RING_TYPE_KIQ, 54 AMDGPU_RING_TYPE_UVD_ENC, 55 AMDGPU_RING_TYPE_VCN_DEC, 56 AMDGPU_RING_TYPE_VCN_ENC, 57 AMDGPU_RING_TYPE_VCN_JPEG 58 }; 59 60 struct amdgpu_device; 61 struct amdgpu_ring; 62 struct amdgpu_ib; 63 struct amdgpu_cs_parser; 64 struct amdgpu_job; 65 66 /* 67 * Fences. 68 */ 69 struct amdgpu_fence_driver { 70 uint64_t gpu_addr; 71 volatile uint32_t *cpu_addr; 72 /* sync_seq is protected by ring emission lock */ 73 uint32_t sync_seq; 74 atomic_t last_seq; 75 bool initialized; 76 struct amdgpu_irq_src *irq_src; 77 unsigned irq_type; 78 struct timer_list fallback_timer; 79 unsigned num_fences_mask; 80 spinlock_t lock; 81 struct dma_fence **fences; 82 }; 83 84 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 85 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 86 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 87 88 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 89 unsigned num_hw_submission); 90 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 91 struct amdgpu_irq_src *irq_src, 92 unsigned irq_type); 93 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 94 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 95 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, 96 unsigned flags); 97 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); 98 void amdgpu_fence_process(struct amdgpu_ring *ring); 99 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 100 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 101 uint32_t wait_seq, 102 signed long timeout); 103 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 104 105 /* 106 * Rings. 107 */ 108 109 /* provided by hw blocks that expose a ring buffer for commands */ 110 struct amdgpu_ring_funcs { 111 enum amdgpu_ring_type type; 112 uint32_t align_mask; 113 u32 nop; 114 bool support_64bit_ptrs; 115 unsigned vmhub; 116 unsigned extra_dw; 117 118 /* ring read/write ptr handling */ 119 u64 (*get_rptr)(struct amdgpu_ring *ring); 120 u64 (*get_wptr)(struct amdgpu_ring *ring); 121 void (*set_wptr)(struct amdgpu_ring *ring); 122 /* validating and patching of IBs */ 123 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 124 /* constants to calculate how many DW are needed for an emit */ 125 unsigned emit_frame_size; 126 unsigned emit_ib_size; 127 /* command emit functions */ 128 void (*emit_ib)(struct amdgpu_ring *ring, 129 struct amdgpu_ib *ib, 130 unsigned vmid, bool ctx_switch); 131 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 132 uint64_t seq, unsigned flags); 133 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 134 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 135 uint64_t pd_addr); 136 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 137 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 138 uint32_t gds_base, uint32_t gds_size, 139 uint32_t gws_base, uint32_t gws_size, 140 uint32_t oa_base, uint32_t oa_size); 141 /* testing functions */ 142 int (*test_ring)(struct amdgpu_ring *ring); 143 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 144 /* insert NOP packets */ 145 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 146 void (*insert_start)(struct amdgpu_ring *ring); 147 void (*insert_end)(struct amdgpu_ring *ring); 148 /* pad the indirect buffer to the necessary number of dw */ 149 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 150 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 151 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 152 /* note usage for clock and power gating */ 153 void (*begin_use)(struct amdgpu_ring *ring); 154 void (*end_use)(struct amdgpu_ring *ring); 155 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 156 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 157 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); 158 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 159 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 160 uint32_t val, uint32_t mask); 161 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 162 uint32_t reg0, uint32_t reg1, 163 uint32_t ref, uint32_t mask); 164 void (*emit_tmz)(struct amdgpu_ring *ring, bool start); 165 /* priority functions */ 166 void (*set_priority) (struct amdgpu_ring *ring, 167 enum drm_sched_priority priority); 168 }; 169 170 struct amdgpu_ring { 171 struct amdgpu_device *adev; 172 const struct amdgpu_ring_funcs *funcs; 173 struct amdgpu_fence_driver fence_drv; 174 struct drm_gpu_scheduler sched; 175 struct list_head lru_list; 176 177 struct amdgpu_bo *ring_obj; 178 volatile uint32_t *ring; 179 unsigned rptr_offs; 180 u64 wptr; 181 u64 wptr_old; 182 unsigned ring_size; 183 unsigned max_dw; 184 int count_dw; 185 uint64_t gpu_addr; 186 uint64_t ptr_mask; 187 uint32_t buf_mask; 188 bool ready; 189 u32 idx; 190 u32 me; 191 u32 pipe; 192 u32 queue; 193 struct amdgpu_bo *mqd_obj; 194 uint64_t mqd_gpu_addr; 195 void *mqd_ptr; 196 uint64_t eop_gpu_addr; 197 u32 doorbell_index; 198 bool use_doorbell; 199 bool use_pollmem; 200 unsigned wptr_offs; 201 unsigned fence_offs; 202 uint64_t current_ctx; 203 char name[16]; 204 unsigned cond_exe_offs; 205 u64 cond_exe_gpu_addr; 206 volatile u32 *cond_exe_cpu_addr; 207 unsigned vm_inv_eng; 208 struct dma_fence *vmid_wait; 209 bool has_compute_vm_bug; 210 211 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; 212 struct mutex priority_mutex; 213 /* protected by priority_mutex */ 214 int priority; 215 216 #if defined(CONFIG_DEBUG_FS) 217 struct dentry *ent; 218 #endif 219 }; 220 221 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 222 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 223 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 224 void amdgpu_ring_commit(struct amdgpu_ring *ring); 225 void amdgpu_ring_undo(struct amdgpu_ring *ring); 226 void amdgpu_ring_priority_get(struct amdgpu_ring *ring, 227 enum drm_sched_priority priority); 228 void amdgpu_ring_priority_put(struct amdgpu_ring *ring, 229 enum drm_sched_priority priority); 230 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 231 unsigned ring_size, struct amdgpu_irq_src *irq_src, 232 unsigned irq_type); 233 void amdgpu_ring_fini(struct amdgpu_ring *ring); 234 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, 235 int *blacklist, int num_blacklist, 236 bool lru_pipe_order, struct amdgpu_ring **ring); 237 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring); 238 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 239 uint32_t reg0, uint32_t val0, 240 uint32_t reg1, uint32_t val1); 241 242 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 243 { 244 int i = 0; 245 while (i <= ring->buf_mask) 246 ring->ring[i++] = ring->funcs->nop; 247 248 } 249 250 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 251 { 252 if (ring->count_dw <= 0) 253 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 254 ring->ring[ring->wptr++ & ring->buf_mask] = v; 255 ring->wptr &= ring->ptr_mask; 256 ring->count_dw--; 257 } 258 259 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 260 void *src, int count_dw) 261 { 262 unsigned occupied, chunk1, chunk2; 263 void *dst; 264 265 if (unlikely(ring->count_dw < count_dw)) 266 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 267 268 occupied = ring->wptr & ring->buf_mask; 269 dst = (void *)&ring->ring[occupied]; 270 chunk1 = ring->buf_mask + 1 - occupied; 271 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 272 chunk2 = count_dw - chunk1; 273 chunk1 <<= 2; 274 chunk2 <<= 2; 275 276 if (chunk1) 277 memcpy(dst, src, chunk1); 278 279 if (chunk2) { 280 src += chunk1; 281 dst = (void *)ring->ring; 282 memcpy(dst, src, chunk2); 283 } 284 285 ring->wptr += count_dw; 286 ring->wptr &= ring->ptr_mask; 287 ring->count_dw -= count_dw; 288 } 289 290 #endif 291