1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 31 /* max number of rings */ 32 #define AMDGPU_MAX_RINGS 28 33 #define AMDGPU_MAX_HWIP_RINGS 8 34 #define AMDGPU_MAX_GFX_RINGS 2 35 #define AMDGPU_MAX_COMPUTE_RINGS 8 36 #define AMDGPU_MAX_VCE_RINGS 3 37 #define AMDGPU_MAX_UVD_ENC_RINGS 2 38 39 #define AMDGPU_RING_PRIO_DEFAULT 1 40 #define AMDGPU_RING_PRIO_MAX AMDGPU_GFX_PIPE_PRIO_MAX 41 42 /* some special values for the owner field */ 43 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 44 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 45 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 46 47 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 48 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 49 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 50 51 /* fence flag bit to indicate the face is embedded in job*/ 52 #define AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT (DMA_FENCE_FLAG_USER_BITS + 1) 53 54 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 55 56 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 57 58 enum amdgpu_ring_type { 59 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 60 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 61 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 62 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 63 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 64 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 65 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 66 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 67 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 68 AMDGPU_RING_TYPE_KIQ, 69 AMDGPU_RING_TYPE_MES 70 }; 71 72 enum amdgpu_ib_pool_type { 73 /* Normal submissions to the top of the pipeline. */ 74 AMDGPU_IB_POOL_DELAYED, 75 /* Immediate submissions to the bottom of the pipeline. */ 76 AMDGPU_IB_POOL_IMMEDIATE, 77 /* Direct submission to the ring buffer during init and reset. */ 78 AMDGPU_IB_POOL_DIRECT, 79 80 AMDGPU_IB_POOL_MAX 81 }; 82 83 struct amdgpu_device; 84 struct amdgpu_ring; 85 struct amdgpu_ib; 86 struct amdgpu_cs_parser; 87 struct amdgpu_job; 88 89 struct amdgpu_sched { 90 u32 num_scheds; 91 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 92 }; 93 94 /* 95 * Fences. 96 */ 97 struct amdgpu_fence_driver { 98 uint64_t gpu_addr; 99 volatile uint32_t *cpu_addr; 100 /* sync_seq is protected by ring emission lock */ 101 uint32_t sync_seq; 102 atomic_t last_seq; 103 bool initialized; 104 struct amdgpu_irq_src *irq_src; 105 unsigned irq_type; 106 struct timer_list fallback_timer; 107 unsigned num_fences_mask; 108 spinlock_t lock; 109 struct dma_fence **fences; 110 }; 111 112 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 113 114 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 115 unsigned num_hw_submission, 116 atomic_t *sched_score); 117 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 118 struct amdgpu_irq_src *irq_src, 119 unsigned irq_type); 120 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 121 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 122 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 123 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 124 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job, 125 unsigned flags); 126 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 127 uint32_t timeout); 128 bool amdgpu_fence_process(struct amdgpu_ring *ring); 129 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 130 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 131 uint32_t wait_seq, 132 signed long timeout); 133 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 134 135 /* 136 * Rings. 137 */ 138 139 /* provided by hw blocks that expose a ring buffer for commands */ 140 struct amdgpu_ring_funcs { 141 enum amdgpu_ring_type type; 142 uint32_t align_mask; 143 u32 nop; 144 bool support_64bit_ptrs; 145 bool no_user_fence; 146 unsigned vmhub; 147 unsigned extra_dw; 148 149 /* ring read/write ptr handling */ 150 u64 (*get_rptr)(struct amdgpu_ring *ring); 151 u64 (*get_wptr)(struct amdgpu_ring *ring); 152 void (*set_wptr)(struct amdgpu_ring *ring); 153 /* validating and patching of IBs */ 154 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 155 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 156 /* constants to calculate how many DW are needed for an emit */ 157 unsigned emit_frame_size; 158 unsigned emit_ib_size; 159 /* command emit functions */ 160 void (*emit_ib)(struct amdgpu_ring *ring, 161 struct amdgpu_job *job, 162 struct amdgpu_ib *ib, 163 uint32_t flags); 164 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 165 uint64_t seq, unsigned flags); 166 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 167 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 168 uint64_t pd_addr); 169 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 170 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 171 uint32_t gds_base, uint32_t gds_size, 172 uint32_t gws_base, uint32_t gws_size, 173 uint32_t oa_base, uint32_t oa_size); 174 /* testing functions */ 175 int (*test_ring)(struct amdgpu_ring *ring); 176 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 177 /* insert NOP packets */ 178 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 179 void (*insert_start)(struct amdgpu_ring *ring); 180 void (*insert_end)(struct amdgpu_ring *ring); 181 /* pad the indirect buffer to the necessary number of dw */ 182 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 183 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 184 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 185 /* note usage for clock and power gating */ 186 void (*begin_use)(struct amdgpu_ring *ring); 187 void (*end_use)(struct amdgpu_ring *ring); 188 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 189 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 190 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 191 uint32_t reg_val_offs); 192 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 193 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 194 uint32_t val, uint32_t mask); 195 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 196 uint32_t reg0, uint32_t reg1, 197 uint32_t ref, uint32_t mask); 198 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 199 bool secure); 200 /* Try to soft recover the ring to make the fence signal */ 201 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 202 int (*preempt_ib)(struct amdgpu_ring *ring); 203 void (*emit_mem_sync)(struct amdgpu_ring *ring); 204 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 205 }; 206 207 struct amdgpu_ring { 208 struct amdgpu_device *adev; 209 const struct amdgpu_ring_funcs *funcs; 210 struct amdgpu_fence_driver fence_drv; 211 struct drm_gpu_scheduler sched; 212 213 struct amdgpu_bo *ring_obj; 214 volatile uint32_t *ring; 215 unsigned rptr_offs; 216 u64 wptr; 217 u64 wptr_old; 218 unsigned ring_size; 219 unsigned max_dw; 220 int count_dw; 221 uint64_t gpu_addr; 222 uint64_t ptr_mask; 223 uint32_t buf_mask; 224 u32 idx; 225 u32 me; 226 u32 pipe; 227 u32 queue; 228 struct amdgpu_bo *mqd_obj; 229 uint64_t mqd_gpu_addr; 230 void *mqd_ptr; 231 uint64_t eop_gpu_addr; 232 u32 doorbell_index; 233 bool use_doorbell; 234 bool use_pollmem; 235 unsigned wptr_offs; 236 unsigned fence_offs; 237 uint64_t current_ctx; 238 char name[16]; 239 u32 trail_seq; 240 unsigned trail_fence_offs; 241 u64 trail_fence_gpu_addr; 242 volatile u32 *trail_fence_cpu_addr; 243 unsigned cond_exe_offs; 244 u64 cond_exe_gpu_addr; 245 volatile u32 *cond_exe_cpu_addr; 246 unsigned vm_inv_eng; 247 struct dma_fence *vmid_wait; 248 bool has_compute_vm_bug; 249 bool no_scheduler; 250 int hw_prio; 251 252 #if defined(CONFIG_DEBUG_FS) 253 struct dentry *ent; 254 #endif 255 }; 256 257 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 258 #define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib))) 259 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 260 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 261 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 262 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 263 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 264 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 265 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 266 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 267 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 268 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 269 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 270 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 271 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 272 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 273 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 274 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 275 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 276 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 277 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 278 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 279 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 280 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 281 282 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 283 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 284 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 285 void amdgpu_ring_commit(struct amdgpu_ring *ring); 286 void amdgpu_ring_undo(struct amdgpu_ring *ring); 287 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 288 unsigned int ring_size, struct amdgpu_irq_src *irq_src, 289 unsigned int irq_type, unsigned int prio, 290 atomic_t *sched_score); 291 void amdgpu_ring_fini(struct amdgpu_ring *ring); 292 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 293 uint32_t reg0, uint32_t val0, 294 uint32_t reg1, uint32_t val1); 295 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 296 struct dma_fence *fence); 297 298 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 299 bool cond_exec) 300 { 301 *ring->cond_exe_cpu_addr = cond_exec; 302 } 303 304 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 305 { 306 int i = 0; 307 while (i <= ring->buf_mask) 308 ring->ring[i++] = ring->funcs->nop; 309 310 } 311 312 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 313 { 314 if (ring->count_dw <= 0) 315 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 316 ring->ring[ring->wptr++ & ring->buf_mask] = v; 317 ring->wptr &= ring->ptr_mask; 318 ring->count_dw--; 319 } 320 321 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 322 void *src, int count_dw) 323 { 324 unsigned occupied, chunk1, chunk2; 325 void *dst; 326 327 if (unlikely(ring->count_dw < count_dw)) 328 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 329 330 occupied = ring->wptr & ring->buf_mask; 331 dst = (void *)&ring->ring[occupied]; 332 chunk1 = ring->buf_mask + 1 - occupied; 333 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 334 chunk2 = count_dw - chunk1; 335 chunk1 <<= 2; 336 chunk2 <<= 2; 337 338 if (chunk1) 339 memcpy(dst, src, chunk1); 340 341 if (chunk2) { 342 src += chunk1; 343 dst = (void *)ring->ring; 344 memcpy(dst, src, chunk2); 345 } 346 347 ring->wptr += count_dw; 348 ring->wptr &= ring->ptr_mask; 349 ring->count_dw -= count_dw; 350 } 351 352 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 353 354 int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 355 struct amdgpu_ring *ring); 356 void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring); 357 358 #endif 359