1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 31 /* max number of rings */ 32 #define AMDGPU_MAX_RINGS 28 33 #define AMDGPU_MAX_HWIP_RINGS 8 34 #define AMDGPU_MAX_GFX_RINGS 2 35 #define AMDGPU_MAX_COMPUTE_RINGS 8 36 #define AMDGPU_MAX_VCE_RINGS 3 37 #define AMDGPU_MAX_UVD_ENC_RINGS 2 38 39 #define AMDGPU_RING_PRIO_DEFAULT 1 40 #define AMDGPU_RING_PRIO_MAX AMDGPU_GFX_PIPE_PRIO_MAX 41 42 /* some special values for the owner field */ 43 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 44 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 45 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 46 47 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 48 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 49 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 50 51 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 52 53 enum amdgpu_ring_type { 54 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 55 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 56 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 57 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 58 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 59 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 60 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 61 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 62 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 63 AMDGPU_RING_TYPE_KIQ 64 }; 65 66 struct amdgpu_device; 67 struct amdgpu_ring; 68 struct amdgpu_ib; 69 struct amdgpu_cs_parser; 70 struct amdgpu_job; 71 72 struct amdgpu_sched { 73 u32 num_scheds; 74 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 75 }; 76 77 /* 78 * Fences. 79 */ 80 struct amdgpu_fence_driver { 81 uint64_t gpu_addr; 82 volatile uint32_t *cpu_addr; 83 /* sync_seq is protected by ring emission lock */ 84 uint32_t sync_seq; 85 atomic_t last_seq; 86 bool initialized; 87 struct amdgpu_irq_src *irq_src; 88 unsigned irq_type; 89 struct timer_list fallback_timer; 90 unsigned num_fences_mask; 91 spinlock_t lock; 92 struct dma_fence **fences; 93 }; 94 95 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 96 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 97 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 98 99 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 100 unsigned num_hw_submission); 101 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 102 struct amdgpu_irq_src *irq_src, 103 unsigned irq_type); 104 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 105 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 106 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, 107 unsigned flags); 108 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); 109 bool amdgpu_fence_process(struct amdgpu_ring *ring); 110 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 111 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 112 uint32_t wait_seq, 113 signed long timeout); 114 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 115 116 /* 117 * Rings. 118 */ 119 120 /* provided by hw blocks that expose a ring buffer for commands */ 121 struct amdgpu_ring_funcs { 122 enum amdgpu_ring_type type; 123 uint32_t align_mask; 124 u32 nop; 125 bool support_64bit_ptrs; 126 bool no_user_fence; 127 unsigned vmhub; 128 unsigned extra_dw; 129 130 /* ring read/write ptr handling */ 131 u64 (*get_rptr)(struct amdgpu_ring *ring); 132 u64 (*get_wptr)(struct amdgpu_ring *ring); 133 void (*set_wptr)(struct amdgpu_ring *ring); 134 /* validating and patching of IBs */ 135 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 136 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 137 /* constants to calculate how many DW are needed for an emit */ 138 unsigned emit_frame_size; 139 unsigned emit_ib_size; 140 /* command emit functions */ 141 void (*emit_ib)(struct amdgpu_ring *ring, 142 struct amdgpu_job *job, 143 struct amdgpu_ib *ib, 144 uint32_t flags); 145 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 146 uint64_t seq, unsigned flags); 147 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 148 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 149 uint64_t pd_addr); 150 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 151 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 152 uint32_t gds_base, uint32_t gds_size, 153 uint32_t gws_base, uint32_t gws_size, 154 uint32_t oa_base, uint32_t oa_size); 155 /* testing functions */ 156 int (*test_ring)(struct amdgpu_ring *ring); 157 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 158 /* insert NOP packets */ 159 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 160 void (*insert_start)(struct amdgpu_ring *ring); 161 void (*insert_end)(struct amdgpu_ring *ring); 162 /* pad the indirect buffer to the necessary number of dw */ 163 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 164 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 165 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 166 /* note usage for clock and power gating */ 167 void (*begin_use)(struct amdgpu_ring *ring); 168 void (*end_use)(struct amdgpu_ring *ring); 169 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 170 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 171 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); 172 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 173 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 174 uint32_t val, uint32_t mask); 175 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 176 uint32_t reg0, uint32_t reg1, 177 uint32_t ref, uint32_t mask); 178 void (*emit_tmz)(struct amdgpu_ring *ring, bool start); 179 /* Try to soft recover the ring to make the fence signal */ 180 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 181 int (*preempt_ib)(struct amdgpu_ring *ring); 182 }; 183 184 struct amdgpu_ring { 185 struct amdgpu_device *adev; 186 const struct amdgpu_ring_funcs *funcs; 187 struct amdgpu_fence_driver fence_drv; 188 struct drm_gpu_scheduler sched; 189 190 struct amdgpu_bo *ring_obj; 191 volatile uint32_t *ring; 192 unsigned rptr_offs; 193 u64 wptr; 194 u64 wptr_old; 195 unsigned ring_size; 196 unsigned max_dw; 197 int count_dw; 198 uint64_t gpu_addr; 199 uint64_t ptr_mask; 200 uint32_t buf_mask; 201 u32 idx; 202 u32 me; 203 u32 pipe; 204 u32 queue; 205 struct amdgpu_bo *mqd_obj; 206 uint64_t mqd_gpu_addr; 207 void *mqd_ptr; 208 uint64_t eop_gpu_addr; 209 u32 doorbell_index; 210 bool use_doorbell; 211 bool use_pollmem; 212 unsigned wptr_offs; 213 unsigned fence_offs; 214 uint64_t current_ctx; 215 char name[16]; 216 u32 trail_seq; 217 unsigned trail_fence_offs; 218 u64 trail_fence_gpu_addr; 219 volatile u32 *trail_fence_cpu_addr; 220 unsigned cond_exe_offs; 221 u64 cond_exe_gpu_addr; 222 volatile u32 *cond_exe_cpu_addr; 223 unsigned vm_inv_eng; 224 struct dma_fence *vmid_wait; 225 bool has_compute_vm_bug; 226 bool no_scheduler; 227 228 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; 229 struct mutex priority_mutex; 230 /* protected by priority_mutex */ 231 int priority; 232 233 #if defined(CONFIG_DEBUG_FS) 234 struct dentry *ent; 235 #endif 236 }; 237 238 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 239 #define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib))) 240 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 241 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 242 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 243 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 244 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 245 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 246 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 247 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 248 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 249 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 250 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 251 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 252 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 253 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 254 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 255 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 256 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 257 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 258 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 259 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 260 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 261 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 262 263 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 264 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 265 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 266 void amdgpu_ring_commit(struct amdgpu_ring *ring); 267 void amdgpu_ring_undo(struct amdgpu_ring *ring); 268 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 269 unsigned int ring_size, struct amdgpu_irq_src *irq_src, 270 unsigned int irq_type, unsigned int prio); 271 void amdgpu_ring_fini(struct amdgpu_ring *ring); 272 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 273 uint32_t reg0, uint32_t val0, 274 uint32_t reg1, uint32_t val1); 275 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 276 struct dma_fence *fence); 277 278 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 279 bool cond_exec) 280 { 281 *ring->cond_exe_cpu_addr = cond_exec; 282 } 283 284 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 285 { 286 int i = 0; 287 while (i <= ring->buf_mask) 288 ring->ring[i++] = ring->funcs->nop; 289 290 } 291 292 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 293 { 294 if (ring->count_dw <= 0) 295 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 296 ring->ring[ring->wptr++ & ring->buf_mask] = v; 297 ring->wptr &= ring->ptr_mask; 298 ring->count_dw--; 299 } 300 301 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 302 void *src, int count_dw) 303 { 304 unsigned occupied, chunk1, chunk2; 305 void *dst; 306 307 if (unlikely(ring->count_dw < count_dw)) 308 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 309 310 occupied = ring->wptr & ring->buf_mask; 311 dst = (void *)&ring->ring[occupied]; 312 chunk1 = ring->buf_mask + 1 - occupied; 313 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 314 chunk2 = count_dw - chunk1; 315 chunk1 <<= 2; 316 chunk2 <<= 2; 317 318 if (chunk1) 319 memcpy(dst, src, chunk1); 320 321 if (chunk2) { 322 src += chunk1; 323 dst = (void *)ring->ring; 324 memcpy(dst, src, chunk2); 325 } 326 327 ring->wptr += count_dw; 328 ring->wptr &= ring->ptr_mask; 329 ring->count_dw -= count_dw; 330 } 331 332 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 333 334 int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 335 struct amdgpu_ring *ring); 336 void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring); 337 338 #endif 339