1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/amdgpu_drm.h>
34 #include "amdgpu.h"
35 #include "atom.h"
36 
37 /*
38  * Rings
39  * Most engines on the GPU are fed via ring buffers.  Ring
40  * buffers are areas of GPU accessible memory that the host
41  * writes commands into and the GPU reads commands out of.
42  * There is a rptr (read pointer) that determines where the
43  * GPU is currently reading, and a wptr (write pointer)
44  * which determines where the host has written.  When the
45  * pointers are equal, the ring is idle.  When the host
46  * writes commands to the ring buffer, it increments the
47  * wptr.  The GPU then starts fetching commands and executes
48  * them until the pointers are equal again.
49  */
50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
51 				    struct amdgpu_ring *ring);
52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
53 
54 /**
55  * amdgpu_ring_alloc - allocate space on the ring buffer
56  *
57  * @adev: amdgpu_device pointer
58  * @ring: amdgpu_ring structure holding ring information
59  * @ndw: number of dwords to allocate in the ring buffer
60  *
61  * Allocate @ndw dwords in the ring buffer (all asics).
62  * Returns 0 on success, error on failure.
63  */
64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
65 {
66 	/* Align requested size with padding so unlock_commit can
67 	 * pad safely */
68 	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
69 
70 	/* Make sure we aren't trying to allocate more space
71 	 * than the maximum for one submission
72 	 */
73 	if (WARN_ON_ONCE(ndw > ring->max_dw))
74 		return -ENOMEM;
75 
76 	ring->count_dw = ndw;
77 	ring->wptr_old = ring->wptr;
78 
79 	if (ring->funcs->begin_use)
80 		ring->funcs->begin_use(ring);
81 
82 	return 0;
83 }
84 
85 /** amdgpu_ring_insert_nop - insert NOP packets
86  *
87  * @ring: amdgpu_ring structure holding ring information
88  * @count: the number of NOP packets to insert
89  *
90  * This is the generic insert_nop function for rings except SDMA
91  */
92 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
93 {
94 	int i;
95 
96 	for (i = 0; i < count; i++)
97 		amdgpu_ring_write(ring, ring->funcs->nop);
98 }
99 
100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
101  *
102  * @ring: amdgpu_ring structure holding ring information
103  * @ib: IB to add NOP packets to
104  *
105  * This is the generic pad_ib function for rings except SDMA
106  */
107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
108 {
109 	while (ib->length_dw & ring->funcs->align_mask)
110 		ib->ptr[ib->length_dw++] = ring->funcs->nop;
111 }
112 
113 /**
114  * amdgpu_ring_commit - tell the GPU to execute the new
115  * commands on the ring buffer
116  *
117  * @adev: amdgpu_device pointer
118  * @ring: amdgpu_ring structure holding ring information
119  *
120  * Update the wptr (write pointer) to tell the GPU to
121  * execute new commands on the ring buffer (all asics).
122  */
123 void amdgpu_ring_commit(struct amdgpu_ring *ring)
124 {
125 	uint32_t count;
126 
127 	/* We pad to match fetch size */
128 	count = ring->funcs->align_mask + 1 -
129 		(ring->wptr & ring->funcs->align_mask);
130 	count %= ring->funcs->align_mask + 1;
131 	ring->funcs->insert_nop(ring, count);
132 
133 	mb();
134 	amdgpu_ring_set_wptr(ring);
135 
136 	if (ring->funcs->end_use)
137 		ring->funcs->end_use(ring);
138 }
139 
140 /**
141  * amdgpu_ring_undo - reset the wptr
142  *
143  * @ring: amdgpu_ring structure holding ring information
144  *
145  * Reset the driver's copy of the wptr (all asics).
146  */
147 void amdgpu_ring_undo(struct amdgpu_ring *ring)
148 {
149 	ring->wptr = ring->wptr_old;
150 
151 	if (ring->funcs->end_use)
152 		ring->funcs->end_use(ring);
153 }
154 
155 /**
156  * amdgpu_ring_init - init driver ring struct.
157  *
158  * @adev: amdgpu_device pointer
159  * @ring: amdgpu_ring structure holding ring information
160  * @max_ndw: maximum number of dw for ring alloc
161  * @nop: nop packet for this ring
162  *
163  * Initialize the driver information for the selected ring (all asics).
164  * Returns 0 on success, error on failure.
165  */
166 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
167 		     unsigned max_dw, struct amdgpu_irq_src *irq_src,
168 		     unsigned irq_type)
169 {
170 	int r;
171 
172 	if (ring->adev == NULL) {
173 		if (adev->num_rings >= AMDGPU_MAX_RINGS)
174 			return -EINVAL;
175 
176 		ring->adev = adev;
177 		ring->idx = adev->num_rings++;
178 		adev->rings[ring->idx] = ring;
179 		r = amdgpu_fence_driver_init_ring(ring,
180 			amdgpu_sched_hw_submission);
181 		if (r)
182 			return r;
183 	}
184 
185 	if (ring->funcs->support_64bit_ptrs) {
186 		r = amdgpu_wb_get_64bit(adev, &ring->rptr_offs);
187 		if (r) {
188 			dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
189 			return r;
190 		}
191 
192 		r = amdgpu_wb_get_64bit(adev, &ring->wptr_offs);
193 		if (r) {
194 			dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
195 			return r;
196 		}
197 
198 	} else {
199 		r = amdgpu_wb_get(adev, &ring->rptr_offs);
200 		if (r) {
201 			dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
202 			return r;
203 		}
204 
205 		r = amdgpu_wb_get(adev, &ring->wptr_offs);
206 		if (r) {
207 			dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
208 			return r;
209 		}
210 
211 	}
212 
213 	r = amdgpu_wb_get(adev, &ring->fence_offs);
214 	if (r) {
215 		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
216 		return r;
217 	}
218 
219 	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
220 	if (r) {
221 		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
222 		return r;
223 	}
224 	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
225 	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
226 	/* always set cond_exec_polling to CONTINUE */
227 	*ring->cond_exe_cpu_addr = 1;
228 
229 	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
230 	if (r) {
231 		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
232 		return r;
233 	}
234 
235 	ring->ring_size = roundup_pow_of_two(max_dw * 4 *
236 					     amdgpu_sched_hw_submission);
237 
238 	ring->buf_mask = (ring->ring_size / 4) - 1;
239 	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
240 		0xffffffffffffffff : ring->buf_mask;
241 	/* Allocate ring buffer */
242 	if (ring->ring_obj == NULL) {
243 		r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
244 					    AMDGPU_GEM_DOMAIN_GTT,
245 					    &ring->ring_obj,
246 					    &ring->gpu_addr,
247 					    (void **)&ring->ring);
248 		if (r) {
249 			dev_err(adev->dev, "(%d) ring create failed\n", r);
250 			return r;
251 		}
252 		amdgpu_ring_clear_ring(ring);
253 	}
254 
255 	ring->max_dw = max_dw;
256 
257 	if (amdgpu_debugfs_ring_init(adev, ring)) {
258 		DRM_ERROR("Failed to register debugfs file for rings !\n");
259 	}
260 	return 0;
261 }
262 
263 /**
264  * amdgpu_ring_fini - tear down the driver ring struct.
265  *
266  * @adev: amdgpu_device pointer
267  * @ring: amdgpu_ring structure holding ring information
268  *
269  * Tear down the driver information for the selected ring (all asics).
270  */
271 void amdgpu_ring_fini(struct amdgpu_ring *ring)
272 {
273 	ring->ready = false;
274 
275 	if (ring->funcs->support_64bit_ptrs) {
276 		amdgpu_wb_free_64bit(ring->adev, ring->cond_exe_offs);
277 		amdgpu_wb_free_64bit(ring->adev, ring->fence_offs);
278 		amdgpu_wb_free_64bit(ring->adev, ring->rptr_offs);
279 		amdgpu_wb_free_64bit(ring->adev, ring->wptr_offs);
280 	} else {
281 		amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
282 		amdgpu_wb_free(ring->adev, ring->fence_offs);
283 		amdgpu_wb_free(ring->adev, ring->rptr_offs);
284 		amdgpu_wb_free(ring->adev, ring->wptr_offs);
285 	}
286 
287 
288 	amdgpu_bo_free_kernel(&ring->ring_obj,
289 			      &ring->gpu_addr,
290 			      (void **)&ring->ring);
291 
292 	amdgpu_debugfs_ring_fini(ring);
293 
294 	ring->adev->rings[ring->idx] = NULL;
295 }
296 
297 /*
298  * Debugfs info
299  */
300 #if defined(CONFIG_DEBUG_FS)
301 
302 /* Layout of file is 12 bytes consisting of
303  * - rptr
304  * - wptr
305  * - driver's copy of wptr
306  *
307  * followed by n-words of ring data
308  */
309 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
310 					size_t size, loff_t *pos)
311 {
312 	struct amdgpu_ring *ring = file_inode(f)->i_private;
313 	int r, i;
314 	uint32_t value, result, early[3];
315 
316 	if (*pos & 3 || size & 3)
317 		return -EINVAL;
318 
319 	result = 0;
320 
321 	if (*pos < 12) {
322 		early[0] = amdgpu_ring_get_rptr(ring);
323 		early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
324 		early[2] = ring->wptr & ring->buf_mask;
325 		for (i = *pos / 4; i < 3 && size; i++) {
326 			r = put_user(early[i], (uint32_t *)buf);
327 			if (r)
328 				return r;
329 			buf += 4;
330 			result += 4;
331 			size -= 4;
332 			*pos += 4;
333 		}
334 	}
335 
336 	while (size) {
337 		if (*pos >= (ring->ring_size + 12))
338 			return result;
339 
340 		value = ring->ring[(*pos - 12)/4];
341 		r = put_user(value, (uint32_t*)buf);
342 		if (r)
343 			return r;
344 		buf += 4;
345 		result += 4;
346 		size -= 4;
347 		*pos += 4;
348 	}
349 
350 	return result;
351 }
352 
353 static const struct file_operations amdgpu_debugfs_ring_fops = {
354 	.owner = THIS_MODULE,
355 	.read = amdgpu_debugfs_ring_read,
356 	.llseek = default_llseek
357 };
358 
359 #endif
360 
361 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
362 				    struct amdgpu_ring *ring)
363 {
364 #if defined(CONFIG_DEBUG_FS)
365 	struct drm_minor *minor = adev->ddev->primary;
366 	struct dentry *ent, *root = minor->debugfs_root;
367 	char name[32];
368 
369 	sprintf(name, "amdgpu_ring_%s", ring->name);
370 
371 	ent = debugfs_create_file(name,
372 				  S_IFREG | S_IRUGO, root,
373 				  ring, &amdgpu_debugfs_ring_fops);
374 	if (!ent)
375 		return -ENOMEM;
376 
377 	i_size_write(ent->d_inode, ring->ring_size + 12);
378 	ring->ent = ent;
379 #endif
380 	return 0;
381 }
382 
383 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
384 {
385 #if defined(CONFIG_DEBUG_FS)
386 	debugfs_remove(ring->ent);
387 #endif
388 }
389