1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/amdgpu_drm.h>
34 #include "amdgpu.h"
35 #include "atom.h"
36 
37 /*
38  * Rings
39  * Most engines on the GPU are fed via ring buffers.  Ring
40  * buffers are areas of GPU accessible memory that the host
41  * writes commands into and the GPU reads commands out of.
42  * There is a rptr (read pointer) that determines where the
43  * GPU is currently reading, and a wptr (write pointer)
44  * which determines where the host has written.  When the
45  * pointers are equal, the ring is idle.  When the host
46  * writes commands to the ring buffer, it increments the
47  * wptr.  The GPU then starts fetching commands and executes
48  * them until the pointers are equal again.
49  */
50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
51 				    struct amdgpu_ring *ring);
52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
53 
54 /**
55  * amdgpu_ring_alloc - allocate space on the ring buffer
56  *
57  * @adev: amdgpu_device pointer
58  * @ring: amdgpu_ring structure holding ring information
59  * @ndw: number of dwords to allocate in the ring buffer
60  *
61  * Allocate @ndw dwords in the ring buffer (all asics).
62  * Returns 0 on success, error on failure.
63  */
64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
65 {
66 	/* Align requested size with padding so unlock_commit can
67 	 * pad safely */
68 	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
69 
70 	/* Make sure we aren't trying to allocate more space
71 	 * than the maximum for one submission
72 	 */
73 	if (WARN_ON_ONCE(ndw > ring->max_dw))
74 		return -ENOMEM;
75 
76 	ring->count_dw = ndw;
77 	ring->wptr_old = ring->wptr;
78 
79 	if (ring->funcs->begin_use)
80 		ring->funcs->begin_use(ring);
81 
82 	return 0;
83 }
84 
85 /** amdgpu_ring_insert_nop - insert NOP packets
86  *
87  * @ring: amdgpu_ring structure holding ring information
88  * @count: the number of NOP packets to insert
89  *
90  * This is the generic insert_nop function for rings except SDMA
91  */
92 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
93 {
94 	int i;
95 
96 	for (i = 0; i < count; i++)
97 		amdgpu_ring_write(ring, ring->funcs->nop);
98 }
99 
100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
101  *
102  * @ring: amdgpu_ring structure holding ring information
103  * @ib: IB to add NOP packets to
104  *
105  * This is the generic pad_ib function for rings except SDMA
106  */
107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
108 {
109 	while (ib->length_dw & ring->funcs->align_mask)
110 		ib->ptr[ib->length_dw++] = ring->funcs->nop;
111 }
112 
113 /**
114  * amdgpu_ring_commit - tell the GPU to execute the new
115  * commands on the ring buffer
116  *
117  * @adev: amdgpu_device pointer
118  * @ring: amdgpu_ring structure holding ring information
119  *
120  * Update the wptr (write pointer) to tell the GPU to
121  * execute new commands on the ring buffer (all asics).
122  */
123 void amdgpu_ring_commit(struct amdgpu_ring *ring)
124 {
125 	uint32_t count;
126 
127 	/* We pad to match fetch size */
128 	count = ring->funcs->align_mask + 1 -
129 		(ring->wptr & ring->funcs->align_mask);
130 	count %= ring->funcs->align_mask + 1;
131 	ring->funcs->insert_nop(ring, count);
132 
133 	mb();
134 	amdgpu_ring_set_wptr(ring);
135 
136 	if (ring->funcs->end_use)
137 		ring->funcs->end_use(ring);
138 
139 	amdgpu_ring_lru_touch(ring->adev, ring);
140 }
141 
142 /**
143  * amdgpu_ring_undo - reset the wptr
144  *
145  * @ring: amdgpu_ring structure holding ring information
146  *
147  * Reset the driver's copy of the wptr (all asics).
148  */
149 void amdgpu_ring_undo(struct amdgpu_ring *ring)
150 {
151 	ring->wptr = ring->wptr_old;
152 
153 	if (ring->funcs->end_use)
154 		ring->funcs->end_use(ring);
155 }
156 
157 /**
158  * amdgpu_ring_init - init driver ring struct.
159  *
160  * @adev: amdgpu_device pointer
161  * @ring: amdgpu_ring structure holding ring information
162  * @max_ndw: maximum number of dw for ring alloc
163  * @nop: nop packet for this ring
164  *
165  * Initialize the driver information for the selected ring (all asics).
166  * Returns 0 on success, error on failure.
167  */
168 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
169 		     unsigned max_dw, struct amdgpu_irq_src *irq_src,
170 		     unsigned irq_type)
171 {
172 	int r;
173 	int sched_hw_submission = amdgpu_sched_hw_submission;
174 
175 	/* Set the hw submission limit higher for KIQ because
176 	 * it's used for a number of gfx/compute tasks by both
177 	 * KFD and KGD which may have outstanding fences and
178 	 * it doesn't really use the gpu scheduler anyway;
179 	 * KIQ tasks get submitted directly to the ring.
180 	 */
181 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
182 		sched_hw_submission = max(sched_hw_submission, 256);
183 
184 	if (ring->adev == NULL) {
185 		if (adev->num_rings >= AMDGPU_MAX_RINGS)
186 			return -EINVAL;
187 
188 		ring->adev = adev;
189 		ring->idx = adev->num_rings++;
190 		adev->rings[ring->idx] = ring;
191 		r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
192 		if (r)
193 			return r;
194 	}
195 
196 	r = amdgpu_wb_get(adev, &ring->rptr_offs);
197 	if (r) {
198 		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
199 		return r;
200 	}
201 
202 	r = amdgpu_wb_get(adev, &ring->wptr_offs);
203 	if (r) {
204 		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
205 		return r;
206 	}
207 
208 	r = amdgpu_wb_get(adev, &ring->fence_offs);
209 	if (r) {
210 		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
211 		return r;
212 	}
213 
214 	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
215 	if (r) {
216 		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
217 		return r;
218 	}
219 	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
220 	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
221 	/* always set cond_exec_polling to CONTINUE */
222 	*ring->cond_exe_cpu_addr = 1;
223 
224 	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
225 	if (r) {
226 		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
227 		return r;
228 	}
229 
230 	ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
231 
232 	ring->buf_mask = (ring->ring_size / 4) - 1;
233 	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
234 		0xffffffffffffffff : ring->buf_mask;
235 	/* Allocate ring buffer */
236 	if (ring->ring_obj == NULL) {
237 		r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
238 					    AMDGPU_GEM_DOMAIN_GTT,
239 					    &ring->ring_obj,
240 					    &ring->gpu_addr,
241 					    (void **)&ring->ring);
242 		if (r) {
243 			dev_err(adev->dev, "(%d) ring create failed\n", r);
244 			return r;
245 		}
246 		amdgpu_ring_clear_ring(ring);
247 	}
248 
249 	ring->max_dw = max_dw;
250 	INIT_LIST_HEAD(&ring->lru_list);
251 	amdgpu_ring_lru_touch(adev, ring);
252 
253 	if (amdgpu_debugfs_ring_init(adev, ring)) {
254 		DRM_ERROR("Failed to register debugfs file for rings !\n");
255 	}
256 
257 	return 0;
258 }
259 
260 /**
261  * amdgpu_ring_fini - tear down the driver ring struct.
262  *
263  * @adev: amdgpu_device pointer
264  * @ring: amdgpu_ring structure holding ring information
265  *
266  * Tear down the driver information for the selected ring (all asics).
267  */
268 void amdgpu_ring_fini(struct amdgpu_ring *ring)
269 {
270 	ring->ready = false;
271 
272 	/* Not to finish a ring which is not initialized */
273 	if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
274 		return;
275 
276 	amdgpu_wb_free(ring->adev, ring->rptr_offs);
277 	amdgpu_wb_free(ring->adev, ring->wptr_offs);
278 
279 	amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
280 	amdgpu_wb_free(ring->adev, ring->fence_offs);
281 
282 	amdgpu_bo_free_kernel(&ring->ring_obj,
283 			      &ring->gpu_addr,
284 			      (void **)&ring->ring);
285 
286 	amdgpu_debugfs_ring_fini(ring);
287 
288 	ring->adev->rings[ring->idx] = NULL;
289 }
290 
291 static void amdgpu_ring_lru_touch_locked(struct amdgpu_device *adev,
292 					 struct amdgpu_ring *ring)
293 {
294 	/* list_move_tail handles the case where ring isn't part of the list */
295 	list_move_tail(&ring->lru_list, &adev->ring_lru_list);
296 }
297 
298 static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring,
299 				       int *blacklist, int num_blacklist)
300 {
301 	int i;
302 
303 	for (i = 0; i < num_blacklist; i++) {
304 		if (ring->idx == blacklist[i])
305 			return true;
306 	}
307 
308 	return false;
309 }
310 
311 /**
312  * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block
313  *
314  * @adev: amdgpu_device pointer
315  * @type: amdgpu_ring_type enum
316  * @blacklist: blacklisted ring ids array
317  * @num_blacklist: number of entries in @blacklist
318  * @ring: output ring
319  *
320  * Retrieve the amdgpu_ring structure for the least recently used ring of
321  * a specific IP block (all asics).
322  * Returns 0 on success, error on failure.
323  */
324 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
325 			int num_blacklist, struct amdgpu_ring **ring)
326 {
327 	struct amdgpu_ring *entry;
328 
329 	/* List is sorted in LRU order, find first entry corresponding
330 	 * to the desired HW IP */
331 	*ring = NULL;
332 	spin_lock(&adev->ring_lru_list_lock);
333 	list_for_each_entry(entry, &adev->ring_lru_list, lru_list) {
334 		if (entry->funcs->type != type)
335 			continue;
336 
337 		if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
338 			continue;
339 
340 		*ring = entry;
341 		amdgpu_ring_lru_touch_locked(adev, *ring);
342 		break;
343 	}
344 	spin_unlock(&adev->ring_lru_list_lock);
345 
346 	if (!*ring) {
347 		DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type);
348 		return -EINVAL;
349 	}
350 
351 	return 0;
352 }
353 
354 /**
355  * amdgpu_ring_lru_touch - mark a ring as recently being used
356  *
357  * @adev: amdgpu_device pointer
358  * @ring: ring to touch
359  *
360  * Move @ring to the tail of the lru list
361  */
362 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring)
363 {
364 	spin_lock(&adev->ring_lru_list_lock);
365 	amdgpu_ring_lru_touch_locked(adev, ring);
366 	spin_unlock(&adev->ring_lru_list_lock);
367 }
368 
369 /*
370  * Debugfs info
371  */
372 #if defined(CONFIG_DEBUG_FS)
373 
374 /* Layout of file is 12 bytes consisting of
375  * - rptr
376  * - wptr
377  * - driver's copy of wptr
378  *
379  * followed by n-words of ring data
380  */
381 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
382 					size_t size, loff_t *pos)
383 {
384 	struct amdgpu_ring *ring = file_inode(f)->i_private;
385 	int r, i;
386 	uint32_t value, result, early[3];
387 
388 	if (*pos & 3 || size & 3)
389 		return -EINVAL;
390 
391 	result = 0;
392 
393 	if (*pos < 12) {
394 		early[0] = amdgpu_ring_get_rptr(ring);
395 		early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
396 		early[2] = ring->wptr & ring->buf_mask;
397 		for (i = *pos / 4; i < 3 && size; i++) {
398 			r = put_user(early[i], (uint32_t *)buf);
399 			if (r)
400 				return r;
401 			buf += 4;
402 			result += 4;
403 			size -= 4;
404 			*pos += 4;
405 		}
406 	}
407 
408 	while (size) {
409 		if (*pos >= (ring->ring_size + 12))
410 			return result;
411 
412 		value = ring->ring[(*pos - 12)/4];
413 		r = put_user(value, (uint32_t*)buf);
414 		if (r)
415 			return r;
416 		buf += 4;
417 		result += 4;
418 		size -= 4;
419 		*pos += 4;
420 	}
421 
422 	return result;
423 }
424 
425 static const struct file_operations amdgpu_debugfs_ring_fops = {
426 	.owner = THIS_MODULE,
427 	.read = amdgpu_debugfs_ring_read,
428 	.llseek = default_llseek
429 };
430 
431 #endif
432 
433 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
434 				    struct amdgpu_ring *ring)
435 {
436 #if defined(CONFIG_DEBUG_FS)
437 	struct drm_minor *minor = adev->ddev->primary;
438 	struct dentry *ent, *root = minor->debugfs_root;
439 	char name[32];
440 
441 	sprintf(name, "amdgpu_ring_%s", ring->name);
442 
443 	ent = debugfs_create_file(name,
444 				  S_IFREG | S_IRUGO, root,
445 				  ring, &amdgpu_debugfs_ring_fops);
446 	if (!ent)
447 		return -ENOMEM;
448 
449 	i_size_write(ent->d_inode, ring->ring_size + 12);
450 	ring->ent = ent;
451 #endif
452 	return 0;
453 }
454 
455 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
456 {
457 #if defined(CONFIG_DEBUG_FS)
458 	debugfs_remove(ring->ent);
459 #endif
460 }
461