1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/debugfs.h>
33 
34 #include <drm/amdgpu_drm.h>
35 #include "amdgpu.h"
36 #include "atom.h"
37 
38 /*
39  * Rings
40  * Most engines on the GPU are fed via ring buffers.  Ring
41  * buffers are areas of GPU accessible memory that the host
42  * writes commands into and the GPU reads commands out of.
43  * There is a rptr (read pointer) that determines where the
44  * GPU is currently reading, and a wptr (write pointer)
45  * which determines where the host has written.  When the
46  * pointers are equal, the ring is idle.  When the host
47  * writes commands to the ring buffer, it increments the
48  * wptr.  The GPU then starts fetching commands and executes
49  * them until the pointers are equal again.
50  */
51 
52 /**
53  * amdgpu_ring_alloc - allocate space on the ring buffer
54  *
55  * @adev: amdgpu_device pointer
56  * @ring: amdgpu_ring structure holding ring information
57  * @ndw: number of dwords to allocate in the ring buffer
58  *
59  * Allocate @ndw dwords in the ring buffer (all asics).
60  * Returns 0 on success, error on failure.
61  */
62 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
63 {
64 	/* Align requested size with padding so unlock_commit can
65 	 * pad safely */
66 	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
67 
68 	/* Make sure we aren't trying to allocate more space
69 	 * than the maximum for one submission
70 	 */
71 	if (WARN_ON_ONCE(ndw > ring->max_dw))
72 		return -ENOMEM;
73 
74 	ring->count_dw = ndw;
75 	ring->wptr_old = ring->wptr;
76 
77 	if (ring->funcs->begin_use)
78 		ring->funcs->begin_use(ring);
79 
80 	return 0;
81 }
82 
83 /** amdgpu_ring_insert_nop - insert NOP packets
84  *
85  * @ring: amdgpu_ring structure holding ring information
86  * @count: the number of NOP packets to insert
87  *
88  * This is the generic insert_nop function for rings except SDMA
89  */
90 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
91 {
92 	int i;
93 
94 	for (i = 0; i < count; i++)
95 		amdgpu_ring_write(ring, ring->funcs->nop);
96 }
97 
98 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
99  *
100  * @ring: amdgpu_ring structure holding ring information
101  * @ib: IB to add NOP packets to
102  *
103  * This is the generic pad_ib function for rings except SDMA
104  */
105 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
106 {
107 	while (ib->length_dw & ring->funcs->align_mask)
108 		ib->ptr[ib->length_dw++] = ring->funcs->nop;
109 }
110 
111 /**
112  * amdgpu_ring_commit - tell the GPU to execute the new
113  * commands on the ring buffer
114  *
115  * @adev: amdgpu_device pointer
116  * @ring: amdgpu_ring structure holding ring information
117  *
118  * Update the wptr (write pointer) to tell the GPU to
119  * execute new commands on the ring buffer (all asics).
120  */
121 void amdgpu_ring_commit(struct amdgpu_ring *ring)
122 {
123 	uint32_t count;
124 
125 	/* We pad to match fetch size */
126 	count = ring->funcs->align_mask + 1 -
127 		(ring->wptr & ring->funcs->align_mask);
128 	count %= ring->funcs->align_mask + 1;
129 	ring->funcs->insert_nop(ring, count);
130 
131 	mb();
132 	amdgpu_ring_set_wptr(ring);
133 
134 	if (ring->funcs->end_use)
135 		ring->funcs->end_use(ring);
136 }
137 
138 /**
139  * amdgpu_ring_undo - reset the wptr
140  *
141  * @ring: amdgpu_ring structure holding ring information
142  *
143  * Reset the driver's copy of the wptr (all asics).
144  */
145 void amdgpu_ring_undo(struct amdgpu_ring *ring)
146 {
147 	ring->wptr = ring->wptr_old;
148 
149 	if (ring->funcs->end_use)
150 		ring->funcs->end_use(ring);
151 }
152 
153 /**
154  * amdgpu_ring_init - init driver ring struct.
155  *
156  * @adev: amdgpu_device pointer
157  * @ring: amdgpu_ring structure holding ring information
158  * @max_ndw: maximum number of dw for ring alloc
159  * @nop: nop packet for this ring
160  *
161  * Initialize the driver information for the selected ring (all asics).
162  * Returns 0 on success, error on failure.
163  */
164 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
165 		     unsigned max_dw, struct amdgpu_irq_src *irq_src,
166 		     unsigned irq_type)
167 {
168 	int r, i;
169 	int sched_hw_submission = amdgpu_sched_hw_submission;
170 
171 	/* Set the hw submission limit higher for KIQ because
172 	 * it's used for a number of gfx/compute tasks by both
173 	 * KFD and KGD which may have outstanding fences and
174 	 * it doesn't really use the gpu scheduler anyway;
175 	 * KIQ tasks get submitted directly to the ring.
176 	 */
177 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
178 		sched_hw_submission = max(sched_hw_submission, 256);
179 	else if (ring == &adev->sdma.instance[0].page)
180 		sched_hw_submission = 256;
181 
182 	if (ring->adev == NULL) {
183 		if (adev->num_rings >= AMDGPU_MAX_RINGS)
184 			return -EINVAL;
185 
186 		ring->adev = adev;
187 		ring->idx = adev->num_rings++;
188 		adev->rings[ring->idx] = ring;
189 		r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
190 		if (r)
191 			return r;
192 	}
193 
194 	r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
195 	if (r) {
196 		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
197 		return r;
198 	}
199 
200 	r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
201 	if (r) {
202 		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
203 		return r;
204 	}
205 
206 	r = amdgpu_device_wb_get(adev, &ring->fence_offs);
207 	if (r) {
208 		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
209 		return r;
210 	}
211 
212 	r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
213 	if (r) {
214 		dev_err(adev->dev,
215 			"(%d) ring trail_fence_offs wb alloc failed\n", r);
216 		return r;
217 	}
218 	ring->trail_fence_gpu_addr =
219 		adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
220 	ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
221 
222 	r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
223 	if (r) {
224 		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
225 		return r;
226 	}
227 	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
228 	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
229 	/* always set cond_exec_polling to CONTINUE */
230 	*ring->cond_exe_cpu_addr = 1;
231 
232 	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
233 	if (r) {
234 		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
235 		return r;
236 	}
237 
238 	ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
239 
240 	ring->buf_mask = (ring->ring_size / 4) - 1;
241 	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
242 		0xffffffffffffffff : ring->buf_mask;
243 	/* Allocate ring buffer */
244 	if (ring->ring_obj == NULL) {
245 		r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
246 					    AMDGPU_GEM_DOMAIN_GTT,
247 					    &ring->ring_obj,
248 					    &ring->gpu_addr,
249 					    (void **)&ring->ring);
250 		if (r) {
251 			dev_err(adev->dev, "(%d) ring create failed\n", r);
252 			return r;
253 		}
254 		amdgpu_ring_clear_ring(ring);
255 	}
256 
257 	ring->max_dw = max_dw;
258 	ring->priority = DRM_SCHED_PRIORITY_NORMAL;
259 	mutex_init(&ring->priority_mutex);
260 
261 	for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
262 		atomic_set(&ring->num_jobs[i], 0);
263 
264 	return 0;
265 }
266 
267 /**
268  * amdgpu_ring_fini - tear down the driver ring struct.
269  *
270  * @adev: amdgpu_device pointer
271  * @ring: amdgpu_ring structure holding ring information
272  *
273  * Tear down the driver information for the selected ring (all asics).
274  */
275 void amdgpu_ring_fini(struct amdgpu_ring *ring)
276 {
277 
278 	/* Not to finish a ring which is not initialized */
279 	if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
280 		return;
281 
282 	ring->sched.ready = false;
283 
284 	amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
285 	amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
286 
287 	amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
288 	amdgpu_device_wb_free(ring->adev, ring->fence_offs);
289 
290 	amdgpu_bo_free_kernel(&ring->ring_obj,
291 			      &ring->gpu_addr,
292 			      (void **)&ring->ring);
293 
294 	dma_fence_put(ring->vmid_wait);
295 	ring->vmid_wait = NULL;
296 	ring->me = 0;
297 
298 	ring->adev->rings[ring->idx] = NULL;
299 }
300 
301 /**
302  * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
303  *
304  * @adev: amdgpu_device pointer
305  * @reg0: register to write
306  * @reg1: register to wait on
307  * @ref: reference value to write/wait on
308  * @mask: mask to wait on
309  *
310  * Helper for rings that don't support write and wait in a
311  * single oneshot packet.
312  */
313 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
314 						uint32_t reg0, uint32_t reg1,
315 						uint32_t ref, uint32_t mask)
316 {
317 	amdgpu_ring_emit_wreg(ring, reg0, ref);
318 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
319 }
320 
321 /**
322  * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
323  *
324  * @ring: ring to try the recovery on
325  * @vmid: VMID we try to get going again
326  * @fence: timedout fence
327  *
328  * Tries to get a ring proceeding again when it is stuck.
329  */
330 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
331 			       struct dma_fence *fence)
332 {
333 	ktime_t deadline = ktime_add_us(ktime_get(), 10000);
334 
335 	if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
336 		return false;
337 
338 	atomic_inc(&ring->adev->gpu_reset_counter);
339 	while (!dma_fence_is_signaled(fence) &&
340 	       ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
341 		ring->funcs->soft_recovery(ring, vmid);
342 
343 	return dma_fence_is_signaled(fence);
344 }
345 
346 /*
347  * Debugfs info
348  */
349 #if defined(CONFIG_DEBUG_FS)
350 
351 /* Layout of file is 12 bytes consisting of
352  * - rptr
353  * - wptr
354  * - driver's copy of wptr
355  *
356  * followed by n-words of ring data
357  */
358 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
359 					size_t size, loff_t *pos)
360 {
361 	struct amdgpu_ring *ring = file_inode(f)->i_private;
362 	int r, i;
363 	uint32_t value, result, early[3];
364 
365 	if (*pos & 3 || size & 3)
366 		return -EINVAL;
367 
368 	result = 0;
369 
370 	if (*pos < 12) {
371 		early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
372 		early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
373 		early[2] = ring->wptr & ring->buf_mask;
374 		for (i = *pos / 4; i < 3 && size; i++) {
375 			r = put_user(early[i], (uint32_t *)buf);
376 			if (r)
377 				return r;
378 			buf += 4;
379 			result += 4;
380 			size -= 4;
381 			*pos += 4;
382 		}
383 	}
384 
385 	while (size) {
386 		if (*pos >= (ring->ring_size + 12))
387 			return result;
388 
389 		value = ring->ring[(*pos - 12)/4];
390 		r = put_user(value, (uint32_t*)buf);
391 		if (r)
392 			return r;
393 		buf += 4;
394 		result += 4;
395 		size -= 4;
396 		*pos += 4;
397 	}
398 
399 	return result;
400 }
401 
402 static const struct file_operations amdgpu_debugfs_ring_fops = {
403 	.owner = THIS_MODULE,
404 	.read = amdgpu_debugfs_ring_read,
405 	.llseek = default_llseek
406 };
407 
408 #endif
409 
410 int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
411 			     struct amdgpu_ring *ring)
412 {
413 #if defined(CONFIG_DEBUG_FS)
414 	struct drm_minor *minor = adev->ddev->primary;
415 	struct dentry *ent, *root = minor->debugfs_root;
416 	char name[32];
417 
418 	sprintf(name, "amdgpu_ring_%s", ring->name);
419 
420 	ent = debugfs_create_file(name,
421 				  S_IFREG | S_IRUGO, root,
422 				  ring, &amdgpu_debugfs_ring_fops);
423 	if (!ent)
424 		return -ENOMEM;
425 
426 	i_size_write(ent->d_inode, ring->ring_size + 12);
427 	ring->ent = ent;
428 #endif
429 	return 0;
430 }
431 
432 /**
433  * amdgpu_ring_test_helper - tests ring and set sched readiness status
434  *
435  * @ring: ring to try the recovery on
436  *
437  * Tests ring and set sched readiness status
438  *
439  * Returns 0 on success, error on failure.
440  */
441 int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
442 {
443 	struct amdgpu_device *adev = ring->adev;
444 	int r;
445 
446 	r = amdgpu_ring_test_ring(ring);
447 	if (r)
448 		DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
449 			      ring->name, r);
450 	else
451 		DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
452 			      ring->name);
453 
454 	ring->sched.ready = !r;
455 	return r;
456 }
457