1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <linux/debugfs.h> 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include "amdgpu.h" 35 #include "atom.h" 36 37 /* 38 * Rings 39 * Most engines on the GPU are fed via ring buffers. Ring 40 * buffers are areas of GPU accessible memory that the host 41 * writes commands into and the GPU reads commands out of. 42 * There is a rptr (read pointer) that determines where the 43 * GPU is currently reading, and a wptr (write pointer) 44 * which determines where the host has written. When the 45 * pointers are equal, the ring is idle. When the host 46 * writes commands to the ring buffer, it increments the 47 * wptr. The GPU then starts fetching commands and executes 48 * them until the pointers are equal again. 49 */ 50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 51 struct amdgpu_ring *ring); 52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring); 53 54 /** 55 * amdgpu_ring_alloc - allocate space on the ring buffer 56 * 57 * @adev: amdgpu_device pointer 58 * @ring: amdgpu_ring structure holding ring information 59 * @ndw: number of dwords to allocate in the ring buffer 60 * 61 * Allocate @ndw dwords in the ring buffer (all asics). 62 * Returns 0 on success, error on failure. 63 */ 64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) 65 { 66 /* Align requested size with padding so unlock_commit can 67 * pad safely */ 68 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 69 70 /* Make sure we aren't trying to allocate more space 71 * than the maximum for one submission 72 */ 73 if (WARN_ON_ONCE(ndw > ring->max_dw)) 74 return -ENOMEM; 75 76 ring->count_dw = ndw; 77 ring->wptr_old = ring->wptr; 78 79 if (ring->funcs->begin_use) 80 ring->funcs->begin_use(ring); 81 82 return 0; 83 } 84 85 /** amdgpu_ring_insert_nop - insert NOP packets 86 * 87 * @ring: amdgpu_ring structure holding ring information 88 * @count: the number of NOP packets to insert 89 * 90 * This is the generic insert_nop function for rings except SDMA 91 */ 92 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 93 { 94 int i; 95 96 for (i = 0; i < count; i++) 97 amdgpu_ring_write(ring, ring->funcs->nop); 98 } 99 100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets 101 * 102 * @ring: amdgpu_ring structure holding ring information 103 * @ib: IB to add NOP packets to 104 * 105 * This is the generic pad_ib function for rings except SDMA 106 */ 107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 108 { 109 while (ib->length_dw & ring->funcs->align_mask) 110 ib->ptr[ib->length_dw++] = ring->funcs->nop; 111 } 112 113 /** 114 * amdgpu_ring_commit - tell the GPU to execute the new 115 * commands on the ring buffer 116 * 117 * @adev: amdgpu_device pointer 118 * @ring: amdgpu_ring structure holding ring information 119 * 120 * Update the wptr (write pointer) to tell the GPU to 121 * execute new commands on the ring buffer (all asics). 122 */ 123 void amdgpu_ring_commit(struct amdgpu_ring *ring) 124 { 125 uint32_t count; 126 127 /* We pad to match fetch size */ 128 count = ring->funcs->align_mask + 1 - 129 (ring->wptr & ring->funcs->align_mask); 130 count %= ring->funcs->align_mask + 1; 131 ring->funcs->insert_nop(ring, count); 132 133 mb(); 134 amdgpu_ring_set_wptr(ring); 135 136 if (ring->funcs->end_use) 137 ring->funcs->end_use(ring); 138 } 139 140 /** 141 * amdgpu_ring_undo - reset the wptr 142 * 143 * @ring: amdgpu_ring structure holding ring information 144 * 145 * Reset the driver's copy of the wptr (all asics). 146 */ 147 void amdgpu_ring_undo(struct amdgpu_ring *ring) 148 { 149 ring->wptr = ring->wptr_old; 150 151 if (ring->funcs->end_use) 152 ring->funcs->end_use(ring); 153 } 154 155 /** 156 * amdgpu_ring_init - init driver ring struct. 157 * 158 * @adev: amdgpu_device pointer 159 * @ring: amdgpu_ring structure holding ring information 160 * @max_ndw: maximum number of dw for ring alloc 161 * @nop: nop packet for this ring 162 * 163 * Initialize the driver information for the selected ring (all asics). 164 * Returns 0 on success, error on failure. 165 */ 166 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 167 unsigned max_dw, struct amdgpu_irq_src *irq_src, 168 unsigned irq_type) 169 { 170 int r; 171 172 if (ring->adev == NULL) { 173 if (adev->num_rings >= AMDGPU_MAX_RINGS) 174 return -EINVAL; 175 176 ring->adev = adev; 177 ring->idx = adev->num_rings++; 178 adev->rings[ring->idx] = ring; 179 r = amdgpu_fence_driver_init_ring(ring, 180 amdgpu_sched_hw_submission); 181 if (r) 182 return r; 183 } 184 185 r = amdgpu_wb_get(adev, &ring->rptr_offs); 186 if (r) { 187 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); 188 return r; 189 } 190 191 r = amdgpu_wb_get(adev, &ring->wptr_offs); 192 if (r) { 193 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); 194 return r; 195 } 196 197 r = amdgpu_wb_get(adev, &ring->fence_offs); 198 if (r) { 199 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); 200 return r; 201 } 202 203 r = amdgpu_wb_get(adev, &ring->cond_exe_offs); 204 if (r) { 205 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); 206 return r; 207 } 208 ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4); 209 ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs]; 210 /* always set cond_exec_polling to CONTINUE */ 211 *ring->cond_exe_cpu_addr = 1; 212 213 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); 214 if (r) { 215 dev_err(adev->dev, "failed initializing fences (%d).\n", r); 216 return r; 217 } 218 219 ring->ring_size = roundup_pow_of_two(max_dw * 4 * 220 amdgpu_sched_hw_submission); 221 222 /* Allocate ring buffer */ 223 if (ring->ring_obj == NULL) { 224 r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 225 AMDGPU_GEM_DOMAIN_GTT, 226 &ring->ring_obj, 227 &ring->gpu_addr, 228 (void **)&ring->ring); 229 if (r) { 230 dev_err(adev->dev, "(%d) ring create failed\n", r); 231 return r; 232 } 233 memset((void *)ring->ring, 0, ring->ring_size); 234 } 235 ring->ptr_mask = (ring->ring_size / 4) - 1; 236 ring->max_dw = max_dw; 237 238 if (amdgpu_debugfs_ring_init(adev, ring)) { 239 DRM_ERROR("Failed to register debugfs file for rings !\n"); 240 } 241 return 0; 242 } 243 244 /** 245 * amdgpu_ring_fini - tear down the driver ring struct. 246 * 247 * @adev: amdgpu_device pointer 248 * @ring: amdgpu_ring structure holding ring information 249 * 250 * Tear down the driver information for the selected ring (all asics). 251 */ 252 void amdgpu_ring_fini(struct amdgpu_ring *ring) 253 { 254 ring->ready = false; 255 256 amdgpu_wb_free(ring->adev, ring->cond_exe_offs); 257 amdgpu_wb_free(ring->adev, ring->fence_offs); 258 amdgpu_wb_free(ring->adev, ring->rptr_offs); 259 amdgpu_wb_free(ring->adev, ring->wptr_offs); 260 261 amdgpu_bo_free_kernel(&ring->ring_obj, 262 &ring->gpu_addr, 263 (void **)&ring->ring); 264 265 amdgpu_debugfs_ring_fini(ring); 266 267 ring->adev->rings[ring->idx] = NULL; 268 } 269 270 /* 271 * Debugfs info 272 */ 273 #if defined(CONFIG_DEBUG_FS) 274 275 /* Layout of file is 12 bytes consisting of 276 * - rptr 277 * - wptr 278 * - driver's copy of wptr 279 * 280 * followed by n-words of ring data 281 */ 282 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, 283 size_t size, loff_t *pos) 284 { 285 struct amdgpu_ring *ring = file_inode(f)->i_private; 286 int r, i; 287 uint32_t value, result, early[3]; 288 289 if (*pos & 3 || size & 3) 290 return -EINVAL; 291 292 result = 0; 293 294 if (*pos < 12) { 295 early[0] = amdgpu_ring_get_rptr(ring); 296 early[1] = amdgpu_ring_get_wptr(ring); 297 early[2] = ring->wptr; 298 for (i = *pos / 4; i < 3 && size; i++) { 299 r = put_user(early[i], (uint32_t *)buf); 300 if (r) 301 return r; 302 buf += 4; 303 result += 4; 304 size -= 4; 305 *pos += 4; 306 } 307 } 308 309 while (size) { 310 if (*pos >= (ring->ring_size + 12)) 311 return result; 312 313 value = ring->ring[(*pos - 12)/4]; 314 r = put_user(value, (uint32_t*)buf); 315 if (r) 316 return r; 317 buf += 4; 318 result += 4; 319 size -= 4; 320 *pos += 4; 321 } 322 323 return result; 324 } 325 326 static const struct file_operations amdgpu_debugfs_ring_fops = { 327 .owner = THIS_MODULE, 328 .read = amdgpu_debugfs_ring_read, 329 .llseek = default_llseek 330 }; 331 332 #endif 333 334 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 335 struct amdgpu_ring *ring) 336 { 337 #if defined(CONFIG_DEBUG_FS) 338 struct drm_minor *minor = adev->ddev->primary; 339 struct dentry *ent, *root = minor->debugfs_root; 340 char name[32]; 341 342 sprintf(name, "amdgpu_ring_%s", ring->name); 343 344 ent = debugfs_create_file(name, 345 S_IFREG | S_IRUGO, root, 346 ring, &amdgpu_debugfs_ring_fops); 347 if (!ent) 348 return -ENOMEM; 349 350 i_size_write(ent->d_inode, ring->ring_size + 12); 351 ring->ent = ent; 352 #endif 353 return 0; 354 } 355 356 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring) 357 { 358 #if defined(CONFIG_DEBUG_FS) 359 debugfs_remove(ring->ent); 360 #endif 361 } 362