1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 30 #define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0 31 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8 32 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342 0xA0 33 34 /* 35 * The 2 macros bellow represent the actual size in bytes that 36 * those entities occupy in the EEPROM memory. 37 * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 38 * uses uint64 to store 6b fields such as retired_page. 39 */ 40 #define EEPROM_TABLE_HEADER_SIZE 20 41 #define EEPROM_TABLE_RECORD_SIZE 24 42 43 #define EEPROM_ADDRESS_SIZE 0x2 44 45 /* Table hdr is 'AMDR' */ 46 #define EEPROM_TABLE_HDR_VAL 0x414d4452 47 #define EEPROM_TABLE_VER 0x00010000 48 49 /* Bad GPU tag ‘BADG’ */ 50 #define EEPROM_TABLE_HDR_BAD 0x42414447 51 52 /* Assume 2 Mbit size */ 53 #define EEPROM_SIZE_BYTES 256000 54 #define EEPROM_PAGE__SIZE_BYTES 256 55 #define EEPROM_HDR_START 0 56 #define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE) 57 #define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE) 58 #define EEPROM_ADDR_MSB_MASK GENMASK(17, 8) 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev 61 62 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 63 { 64 if ((adev->asic_type == CHIP_VEGA20) || 65 (adev->asic_type == CHIP_ARCTURUS)) 66 return true; 67 68 return false; 69 } 70 71 static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, 72 uint16_t *i2c_addr) 73 { 74 struct atom_context *atom_ctx = adev->mode_info.atom_context; 75 76 if (!i2c_addr || !atom_ctx) 77 return false; 78 79 if (strnstr(atom_ctx->vbios_version, 80 "D342", 81 sizeof(atom_ctx->vbios_version))) 82 *i2c_addr = EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342; 83 else 84 *i2c_addr = EEPROM_I2C_TARGET_ADDR_ARCTURUS; 85 86 return true; 87 } 88 89 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 90 uint16_t *i2c_addr) 91 { 92 if (!i2c_addr) 93 return false; 94 95 switch (adev->asic_type) { 96 case CHIP_VEGA20: 97 *i2c_addr = EEPROM_I2C_TARGET_ADDR_VEGA20; 98 break; 99 100 case CHIP_ARCTURUS: 101 return __get_eeprom_i2c_addr_arct(adev, i2c_addr); 102 103 default: 104 return false; 105 } 106 107 return true; 108 } 109 110 static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr, 111 unsigned char *buff) 112 { 113 uint32_t *pp = (uint32_t *) buff; 114 115 pp[0] = cpu_to_le32(hdr->header); 116 pp[1] = cpu_to_le32(hdr->version); 117 pp[2] = cpu_to_le32(hdr->first_rec_offset); 118 pp[3] = cpu_to_le32(hdr->tbl_size); 119 pp[4] = cpu_to_le32(hdr->checksum); 120 } 121 122 static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr, 123 unsigned char *buff) 124 { 125 uint32_t *pp = (uint32_t *)buff; 126 127 hdr->header = le32_to_cpu(pp[0]); 128 hdr->version = le32_to_cpu(pp[1]); 129 hdr->first_rec_offset = le32_to_cpu(pp[2]); 130 hdr->tbl_size = le32_to_cpu(pp[3]); 131 hdr->checksum = le32_to_cpu(pp[4]); 132 } 133 134 static int __update_table_header(struct amdgpu_ras_eeprom_control *control, 135 unsigned char *buff) 136 { 137 int ret = 0; 138 struct amdgpu_device *adev = to_amdgpu_device(control); 139 struct i2c_msg msg = { 140 .addr = 0, 141 .flags = 0, 142 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, 143 .buf = buff, 144 }; 145 146 147 *(uint16_t *)buff = EEPROM_HDR_START; 148 __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE); 149 150 msg.addr = control->i2c_address; 151 152 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1); 153 if (ret < 1) 154 DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret); 155 156 return ret; 157 } 158 159 static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control) 160 { 161 int i; 162 uint32_t tbl_sum = 0; 163 164 /* Header checksum, skip checksum field in the calculation */ 165 for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++) 166 tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i); 167 168 return tbl_sum; 169 } 170 171 static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records, 172 int num) 173 { 174 int i, j; 175 uint32_t tbl_sum = 0; 176 177 /* Records checksum */ 178 for (i = 0; i < num; i++) { 179 struct eeprom_table_record *record = &records[i]; 180 181 for (j = 0; j < sizeof(*record); j++) { 182 tbl_sum += *(((unsigned char *)record) + j); 183 } 184 } 185 186 return tbl_sum; 187 } 188 189 static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control, 190 struct eeprom_table_record *records, int num) 191 { 192 return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num); 193 } 194 195 /* Checksum = 256 -((sum of all table entries) mod 256) */ 196 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control, 197 struct eeprom_table_record *records, int num, 198 uint32_t old_hdr_byte_sum) 199 { 200 /* 201 * This will update the table sum with new records. 202 * 203 * TODO: What happens when the EEPROM table is to be wrapped around 204 * and old records from start will get overridden. 205 */ 206 207 /* need to recalculate updated header byte sum */ 208 control->tbl_byte_sum -= old_hdr_byte_sum; 209 control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num); 210 211 control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256); 212 } 213 214 /* table sum mod 256 + checksum must equals 256 */ 215 static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control, 216 struct eeprom_table_record *records, int num) 217 { 218 control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num); 219 220 if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) { 221 DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum); 222 return false; 223 } 224 225 return true; 226 } 227 228 static int amdgpu_ras_eeprom_correct_header_tag( 229 struct amdgpu_ras_eeprom_control *control, 230 uint32_t header) 231 { 232 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE]; 233 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 234 int ret = 0; 235 236 memset(buff, 0, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE); 237 238 mutex_lock(&control->tbl_mutex); 239 hdr->header = header; 240 ret = __update_table_header(control, buff); 241 mutex_unlock(&control->tbl_mutex); 242 243 return ret; 244 } 245 246 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 247 { 248 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 }; 249 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 250 int ret = 0; 251 252 mutex_lock(&control->tbl_mutex); 253 254 hdr->header = EEPROM_TABLE_HDR_VAL; 255 hdr->version = EEPROM_TABLE_VER; 256 hdr->first_rec_offset = EEPROM_RECORD_START; 257 hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE; 258 259 control->tbl_byte_sum = 0; 260 __update_tbl_checksum(control, NULL, 0, 0); 261 control->next_addr = EEPROM_RECORD_START; 262 263 ret = __update_table_header(control, buff); 264 265 mutex_unlock(&control->tbl_mutex); 266 267 return ret; 268 269 } 270 271 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 272 bool *exceed_err_limit) 273 { 274 int ret = 0; 275 struct amdgpu_device *adev = to_amdgpu_device(control); 276 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 }; 277 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 278 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 279 struct i2c_msg msg = { 280 .addr = 0, 281 .flags = I2C_M_RD, 282 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, 283 .buf = buff, 284 }; 285 286 *exceed_err_limit = false; 287 288 if (!__is_ras_eeprom_supported(adev)) 289 return 0; 290 291 /* Verify i2c adapter is initialized */ 292 if (!adev->pm.smu_i2c.algo) 293 return -ENOENT; 294 295 if (!__get_eeprom_i2c_addr(adev, &control->i2c_address)) 296 return -EINVAL; 297 298 mutex_init(&control->tbl_mutex); 299 300 msg.addr = control->i2c_address; 301 /* Read/Create table header from EEPROM address 0 */ 302 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1); 303 if (ret < 1) { 304 DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret); 305 return ret; 306 } 307 308 __decode_table_header_from_buff(hdr, &buff[2]); 309 310 if (hdr->header == EEPROM_TABLE_HDR_VAL) { 311 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) / 312 EEPROM_TABLE_RECORD_SIZE; 313 control->tbl_byte_sum = __calc_hdr_byte_sum(control); 314 control->next_addr = EEPROM_RECORD_START; 315 316 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 317 control->num_recs); 318 319 } else if ((hdr->header == EEPROM_TABLE_HDR_BAD) && 320 (amdgpu_bad_page_threshold != 0)) { 321 if (ras->bad_page_cnt_threshold > control->num_recs) { 322 dev_info(adev->dev, "Using one valid bigger bad page " 323 "threshold and correcting eeprom header tag.\n"); 324 ret = amdgpu_ras_eeprom_correct_header_tag(control, 325 EEPROM_TABLE_HDR_VAL); 326 } else { 327 *exceed_err_limit = true; 328 dev_err(adev->dev, "Exceeding the bad_page_threshold parameter, " 329 "disabling the GPU.\n"); 330 } 331 } else { 332 DRM_INFO("Creating new EEPROM table"); 333 334 ret = amdgpu_ras_eeprom_reset_table(control); 335 } 336 337 return ret == 1 ? 0 : -EIO; 338 } 339 340 static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control, 341 struct eeprom_table_record *record, 342 unsigned char *buff) 343 { 344 __le64 tmp = 0; 345 int i = 0; 346 347 /* Next are all record fields according to EEPROM page spec in LE foramt */ 348 buff[i++] = record->err_type; 349 350 buff[i++] = record->bank; 351 352 tmp = cpu_to_le64(record->ts); 353 memcpy(buff + i, &tmp, 8); 354 i += 8; 355 356 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 357 memcpy(buff + i, &tmp, 6); 358 i += 6; 359 360 buff[i++] = record->mem_channel; 361 buff[i++] = record->mcumc_id; 362 363 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 364 memcpy(buff + i, &tmp, 6); 365 } 366 367 static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control, 368 struct eeprom_table_record *record, 369 unsigned char *buff) 370 { 371 __le64 tmp = 0; 372 int i = 0; 373 374 /* Next are all record fields according to EEPROM page spec in LE foramt */ 375 record->err_type = buff[i++]; 376 377 record->bank = buff[i++]; 378 379 memcpy(&tmp, buff + i, 8); 380 record->ts = le64_to_cpu(tmp); 381 i += 8; 382 383 memcpy(&tmp, buff + i, 6); 384 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 385 i += 6; 386 387 record->mem_channel = buff[i++]; 388 record->mcumc_id = buff[i++]; 389 390 memcpy(&tmp, buff + i, 6); 391 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 392 } 393 394 /* 395 * When reaching end of EEPROM memory jump back to 0 record address 396 * When next record access will go beyond EEPROM page boundary modify bits A17/A8 397 * in I2C selector to go to next page 398 */ 399 static uint32_t __correct_eeprom_dest_address(uint32_t curr_address) 400 { 401 uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE; 402 403 /* When all EEPROM memory used jump back to 0 address */ 404 if (next_address > EEPROM_SIZE_BYTES) { 405 DRM_INFO("Reached end of EEPROM memory, jumping to 0 " 406 "and overriding old record"); 407 return EEPROM_RECORD_START; 408 } 409 410 /* 411 * To check if we overflow page boundary compare next address with 412 * current and see if bits 17/8 of the EEPROM address will change 413 * If they do start from the next 256b page 414 * 415 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2 416 */ 417 if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) { 418 DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx", 419 (next_address & EEPROM_ADDR_MSB_MASK)); 420 421 return (next_address & EEPROM_ADDR_MSB_MASK); 422 } 423 424 return curr_address; 425 } 426 427 int amdgpu_ras_eeprom_check_err_threshold( 428 struct amdgpu_ras_eeprom_control *control, 429 bool *exceed_err_limit) 430 { 431 struct amdgpu_device *adev = to_amdgpu_device(control); 432 unsigned char buff[EEPROM_ADDRESS_SIZE + 433 EEPROM_TABLE_HEADER_SIZE] = { 0 }; 434 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 435 struct i2c_msg msg = { 436 .addr = control->i2c_address, 437 .flags = I2C_M_RD, 438 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, 439 .buf = buff, 440 }; 441 int ret; 442 443 *exceed_err_limit = false; 444 445 if (!__is_ras_eeprom_supported(adev)) 446 return 0; 447 448 /* read EEPROM table header */ 449 mutex_lock(&control->tbl_mutex); 450 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1); 451 if (ret < 1) { 452 dev_err(adev->dev, "Failed to read EEPROM table header.\n"); 453 goto err; 454 } 455 456 __decode_table_header_from_buff(hdr, &buff[2]); 457 458 if (hdr->header == EEPROM_TABLE_HDR_BAD) { 459 dev_warn(adev->dev, "This GPU is in BAD status."); 460 dev_warn(adev->dev, "Please retire it or setting one bigger " 461 "threshold value when reloading driver.\n"); 462 *exceed_err_limit = true; 463 } 464 465 err: 466 mutex_unlock(&control->tbl_mutex); 467 return 0; 468 } 469 470 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, 471 struct eeprom_table_record *records, 472 bool write, 473 int num) 474 { 475 int i, ret = 0; 476 struct i2c_msg *msgs, *msg; 477 unsigned char *buffs, *buff; 478 bool sched_ras_recovery = false; 479 struct eeprom_table_record *record; 480 struct amdgpu_device *adev = to_amdgpu_device(control); 481 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 482 483 if (!__is_ras_eeprom_supported(adev)) 484 return 0; 485 486 buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE, 487 GFP_KERNEL); 488 if (!buffs) 489 return -ENOMEM; 490 491 mutex_lock(&control->tbl_mutex); 492 493 msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL); 494 if (!msgs) { 495 ret = -ENOMEM; 496 goto free_buff; 497 } 498 499 /* 500 * If saved bad pages number exceeds the bad page threshold for 501 * the whole VRAM, update table header to mark the BAD GPU tag 502 * and schedule one ras recovery after eeprom write is done, 503 * this can avoid the missing for latest records. 504 * 505 * This new header will be picked up and checked in the bootup 506 * by ras recovery, which may break bootup process to notify 507 * user this GPU is in bad state and to retire such GPU for 508 * further check. 509 */ 510 if (write && (amdgpu_bad_page_threshold != 0) && 511 ((control->num_recs + num) >= ras->bad_page_cnt_threshold)) { 512 dev_warn(adev->dev, 513 "Saved bad pages(%d) reaches threshold value(%d).\n", 514 control->num_recs + num, ras->bad_page_cnt_threshold); 515 control->tbl_hdr.header = EEPROM_TABLE_HDR_BAD; 516 sched_ras_recovery = true; 517 } 518 519 /* In case of overflow just start from beginning to not lose newest records */ 520 if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES)) 521 control->next_addr = EEPROM_RECORD_START; 522 523 /* 524 * TODO Currently makes EEPROM writes for each record, this creates 525 * internal fragmentation. Optimized the code to do full page write of 526 * 256b 527 */ 528 for (i = 0; i < num; i++) { 529 buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)]; 530 record = &records[i]; 531 msg = &msgs[i]; 532 533 control->next_addr = __correct_eeprom_dest_address(control->next_addr); 534 535 /* 536 * Update bits 16,17 of EEPROM address in I2C address by setting them 537 * to bits 1,2 of Device address byte 538 */ 539 msg->addr = control->i2c_address | 540 ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15); 541 msg->flags = write ? 0 : I2C_M_RD; 542 msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE; 543 msg->buf = buff; 544 545 /* Insert the EEPROM dest addess, bits 0-15 */ 546 buff[0] = ((control->next_addr >> 8) & 0xff); 547 buff[1] = (control->next_addr & 0xff); 548 549 /* EEPROM table content is stored in LE format */ 550 if (write) 551 __encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE); 552 553 /* 554 * The destination EEPROM address might need to be corrected to account 555 * for page or entire memory wrapping 556 */ 557 control->next_addr += EEPROM_TABLE_RECORD_SIZE; 558 } 559 560 ret = i2c_transfer(&adev->pm.smu_i2c, msgs, num); 561 if (ret < 1) { 562 DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret); 563 564 /* TODO Restore prev next EEPROM address ? */ 565 goto free_msgs; 566 } 567 568 569 if (!write) { 570 for (i = 0; i < num; i++) { 571 buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)]; 572 record = &records[i]; 573 574 __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE); 575 } 576 } 577 578 if (write) { 579 uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control); 580 581 /* 582 * Update table header with size and CRC and account for table 583 * wrap around where the assumption is that we treat it as empty 584 * table 585 * 586 * TODO - Check the assumption is correct 587 */ 588 control->num_recs += num; 589 control->num_recs %= EEPROM_MAX_RECORD_NUM; 590 control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num; 591 if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES) 592 control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE + 593 control->num_recs * EEPROM_TABLE_RECORD_SIZE; 594 595 __update_tbl_checksum(control, records, num, old_hdr_byte_sum); 596 597 __update_table_header(control, buffs); 598 599 if (sched_ras_recovery) { 600 /* 601 * Before scheduling ras recovery, assert the related 602 * flag first, which shall bypass common bad page 603 * reservation execution in amdgpu_ras_reset_gpu. 604 */ 605 amdgpu_ras_get_context(adev)->flags |= 606 AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV; 607 608 dev_warn(adev->dev, "Conduct ras recovery due to bad " 609 "page threshold reached.\n"); 610 amdgpu_ras_reset_gpu(adev); 611 } 612 } else if (!__validate_tbl_checksum(control, records, num)) { 613 DRM_WARN("EEPROM Table checksum mismatch!"); 614 /* TODO Uncomment when EEPROM read/write is relliable */ 615 /* ret = -EIO; */ 616 } 617 618 free_msgs: 619 kfree(msgs); 620 621 free_buff: 622 kfree(buffs); 623 624 mutex_unlock(&control->tbl_mutex); 625 626 return ret == num ? 0 : -EIO; 627 } 628 629 inline uint32_t amdgpu_ras_eeprom_get_record_max_length(void) 630 { 631 return EEPROM_MAX_RECORD_NUM; 632 } 633 634 /* Used for testing if bugs encountered */ 635 #if 0 636 void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control) 637 { 638 int i; 639 struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL); 640 641 if (!recs) 642 return; 643 644 for (i = 0; i < 1 ; i++) { 645 recs[i].address = 0xdeadbeef; 646 recs[i].retired_page = i; 647 } 648 649 if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) { 650 651 memset(recs, 0, sizeof(*recs) * 1); 652 653 control->next_addr = EEPROM_RECORD_START; 654 655 if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) { 656 for (i = 0; i < 1; i++) 657 DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu", 658 recs[i].address, recs[i].retired_page); 659 } else 660 DRM_ERROR("Failed in reading from table"); 661 662 } else 663 DRM_ERROR("Failed in writing to table"); 664 } 665 #endif 666