1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 #define RAS_TABLE_VER 0x00010000 72 73 /* Bad GPU tag ‘BADG’ */ 74 #define RAS_TABLE_HDR_BAD 0x42414447 75 76 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 77 #define RAS_TBL_SIZE_BYTES (256 * 1024) 78 #define RAS_TABLE_START 0 79 #define RAS_HDR_START RAS_TABLE_START 80 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 81 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 82 / RAS_TABLE_RECORD_SIZE) 83 84 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 85 * offset off of RAS_TABLE_START. That is, this is something you can 86 * add to control->i2c_address, and then tell I2C layer to read 87 * from/write to there. _N is the so called absolute index, 88 * because it starts right after the table header. 89 */ 90 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 91 (_N) * RAS_TABLE_RECORD_SIZE) 92 93 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 94 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 95 96 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 97 * of "fri", return the absolute record index off of the end of 98 * the table header. 99 */ 100 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 101 (_C)->ras_max_record_count) 102 103 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 104 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 105 106 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev 107 108 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 109 { 110 if (adev->asic_type == CHIP_IP_DISCOVERY) { 111 switch (adev->ip_versions[MP1_HWIP][0]) { 112 case IP_VERSION(13, 0, 0): 113 case IP_VERSION(13, 0, 10): 114 return true; 115 default: 116 return false; 117 } 118 } 119 120 return adev->asic_type == CHIP_VEGA20 || 121 adev->asic_type == CHIP_ARCTURUS || 122 adev->asic_type == CHIP_SIENNA_CICHLID || 123 adev->asic_type == CHIP_ALDEBARAN; 124 } 125 126 static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, 127 struct amdgpu_ras_eeprom_control *control) 128 { 129 struct atom_context *atom_ctx = adev->mode_info.atom_context; 130 131 if (!control || !atom_ctx) 132 return false; 133 134 if (strnstr(atom_ctx->vbios_version, 135 "D342", 136 sizeof(atom_ctx->vbios_version))) 137 control->i2c_address = EEPROM_I2C_MADDR_0; 138 else 139 control->i2c_address = EEPROM_I2C_MADDR_4; 140 141 return true; 142 } 143 144 static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, 145 struct amdgpu_ras_eeprom_control *control) 146 { 147 switch (adev->ip_versions[MP1_HWIP][0]) { 148 case IP_VERSION(13, 0, 0): 149 case IP_VERSION(13, 0, 10): 150 control->i2c_address = EEPROM_I2C_MADDR_4; 151 return true; 152 default: 153 return false; 154 } 155 } 156 157 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 158 struct amdgpu_ras_eeprom_control *control) 159 { 160 struct atom_context *atom_ctx = adev->mode_info.atom_context; 161 u8 i2c_addr; 162 163 if (!control) 164 return false; 165 166 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 167 /* The address given by VBIOS is an 8-bit, wire-format 168 * address, i.e. the most significant byte. 169 * 170 * Normalize it to a 19-bit EEPROM address. Remove the 171 * device type identifier and make it a 7-bit address; 172 * then make it a 19-bit EEPROM address. See top of 173 * amdgpu_eeprom.c. 174 */ 175 i2c_addr = (i2c_addr & 0x0F) >> 1; 176 control->i2c_address = ((u32) i2c_addr) << 16; 177 178 return true; 179 } 180 181 switch (adev->asic_type) { 182 case CHIP_VEGA20: 183 control->i2c_address = EEPROM_I2C_MADDR_0; 184 break; 185 186 case CHIP_ARCTURUS: 187 return __get_eeprom_i2c_addr_arct(adev, control); 188 189 case CHIP_SIENNA_CICHLID: 190 control->i2c_address = EEPROM_I2C_MADDR_0; 191 break; 192 193 case CHIP_ALDEBARAN: 194 if (strnstr(atom_ctx->vbios_version, "D673", 195 sizeof(atom_ctx->vbios_version))) 196 control->i2c_address = EEPROM_I2C_MADDR_4; 197 else 198 control->i2c_address = EEPROM_I2C_MADDR_0; 199 break; 200 201 case CHIP_IP_DISCOVERY: 202 return __get_eeprom_i2c_addr_ip_discovery(adev, control); 203 204 default: 205 return false; 206 } 207 208 switch (adev->ip_versions[MP1_HWIP][0]) { 209 case IP_VERSION(13, 0, 0): 210 control->i2c_address = EEPROM_I2C_MADDR_4; 211 break; 212 213 default: 214 break; 215 } 216 217 return true; 218 } 219 220 static void 221 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 222 unsigned char *buf) 223 { 224 u32 *pp = (uint32_t *)buf; 225 226 pp[0] = cpu_to_le32(hdr->header); 227 pp[1] = cpu_to_le32(hdr->version); 228 pp[2] = cpu_to_le32(hdr->first_rec_offset); 229 pp[3] = cpu_to_le32(hdr->tbl_size); 230 pp[4] = cpu_to_le32(hdr->checksum); 231 } 232 233 static void 234 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 235 unsigned char *buf) 236 { 237 u32 *pp = (uint32_t *)buf; 238 239 hdr->header = le32_to_cpu(pp[0]); 240 hdr->version = le32_to_cpu(pp[1]); 241 hdr->first_rec_offset = le32_to_cpu(pp[2]); 242 hdr->tbl_size = le32_to_cpu(pp[3]); 243 hdr->checksum = le32_to_cpu(pp[4]); 244 } 245 246 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 247 { 248 u8 buf[RAS_TABLE_HEADER_SIZE]; 249 struct amdgpu_device *adev = to_amdgpu_device(control); 250 int res; 251 252 memset(buf, 0, sizeof(buf)); 253 __encode_table_header_to_buf(&control->tbl_hdr, buf); 254 255 /* i2c may be unstable in gpu reset */ 256 down_read(&adev->reset_domain->sem); 257 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 258 control->i2c_address + 259 control->ras_header_offset, 260 buf, RAS_TABLE_HEADER_SIZE); 261 up_read(&adev->reset_domain->sem); 262 263 if (res < 0) { 264 DRM_ERROR("Failed to write EEPROM table header:%d", res); 265 } else if (res < RAS_TABLE_HEADER_SIZE) { 266 DRM_ERROR("Short write:%d out of %d\n", 267 res, RAS_TABLE_HEADER_SIZE); 268 res = -EIO; 269 } else { 270 res = 0; 271 } 272 273 return res; 274 } 275 276 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 277 { 278 int ii; 279 u8 *pp, csum; 280 size_t sz; 281 282 /* Header checksum, skip checksum field in the calculation */ 283 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 284 pp = (u8 *) &control->tbl_hdr; 285 csum = 0; 286 for (ii = 0; ii < sz; ii++, pp++) 287 csum += *pp; 288 289 return csum; 290 } 291 292 static int amdgpu_ras_eeprom_correct_header_tag( 293 struct amdgpu_ras_eeprom_control *control, 294 uint32_t header) 295 { 296 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 297 u8 *hh; 298 int res; 299 u8 csum; 300 301 csum = -hdr->checksum; 302 303 hh = (void *) &hdr->header; 304 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 305 hh = (void *) &header; 306 csum += hh[0] + hh[1] + hh[2] + hh[3]; 307 csum = -csum; 308 mutex_lock(&control->ras_tbl_mutex); 309 hdr->header = header; 310 hdr->checksum = csum; 311 res = __write_table_header(control); 312 mutex_unlock(&control->ras_tbl_mutex); 313 314 return res; 315 } 316 317 /** 318 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 319 * @control: pointer to control structure 320 * 321 * Reset the contents of the header of the RAS EEPROM table. 322 * Return 0 on success, -errno on error. 323 */ 324 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 325 { 326 struct amdgpu_device *adev = to_amdgpu_device(control); 327 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 328 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 329 u8 csum; 330 int res; 331 332 mutex_lock(&control->ras_tbl_mutex); 333 334 hdr->header = RAS_TABLE_HDR_VAL; 335 hdr->version = RAS_TABLE_VER; 336 hdr->first_rec_offset = RAS_RECORD_START; 337 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 338 339 csum = __calc_hdr_byte_sum(control); 340 csum = -csum; 341 hdr->checksum = csum; 342 res = __write_table_header(control); 343 344 control->ras_num_recs = 0; 345 control->ras_fri = 0; 346 347 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 348 349 control->bad_channel_bitmap = 0; 350 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 351 con->update_channel_flag = false; 352 353 amdgpu_ras_debugfs_set_ret_size(control); 354 355 mutex_unlock(&control->ras_tbl_mutex); 356 357 return res; 358 } 359 360 static void 361 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 362 struct eeprom_table_record *record, 363 unsigned char *buf) 364 { 365 __le64 tmp = 0; 366 int i = 0; 367 368 /* Next are all record fields according to EEPROM page spec in LE foramt */ 369 buf[i++] = record->err_type; 370 371 buf[i++] = record->bank; 372 373 tmp = cpu_to_le64(record->ts); 374 memcpy(buf + i, &tmp, 8); 375 i += 8; 376 377 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 378 memcpy(buf + i, &tmp, 6); 379 i += 6; 380 381 buf[i++] = record->mem_channel; 382 buf[i++] = record->mcumc_id; 383 384 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 385 memcpy(buf + i, &tmp, 6); 386 } 387 388 static void 389 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 390 struct eeprom_table_record *record, 391 unsigned char *buf) 392 { 393 __le64 tmp = 0; 394 int i = 0; 395 396 /* Next are all record fields according to EEPROM page spec in LE foramt */ 397 record->err_type = buf[i++]; 398 399 record->bank = buf[i++]; 400 401 memcpy(&tmp, buf + i, 8); 402 record->ts = le64_to_cpu(tmp); 403 i += 8; 404 405 memcpy(&tmp, buf + i, 6); 406 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 407 i += 6; 408 409 record->mem_channel = buf[i++]; 410 record->mcumc_id = buf[i++]; 411 412 memcpy(&tmp, buf + i, 6); 413 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 414 } 415 416 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 417 { 418 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 419 420 if (!__is_ras_eeprom_supported(adev) || 421 !amdgpu_bad_page_threshold) 422 return false; 423 424 /* skip check eeprom table for VEGA20 Gaming */ 425 if (!con) 426 return false; 427 else 428 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 429 return false; 430 431 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 432 if (amdgpu_bad_page_threshold == -1) { 433 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 434 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold); 435 dev_warn(adev->dev, 436 "But GPU can be operated due to bad_page_threshold = -1.\n"); 437 return false; 438 } else { 439 dev_warn(adev->dev, "This GPU is in BAD status."); 440 dev_warn(adev->dev, "Please retire it or set a larger " 441 "threshold value when reloading driver.\n"); 442 return true; 443 } 444 } 445 446 return false; 447 } 448 449 /** 450 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 451 * @control: pointer to control structure 452 * @buf: pointer to buffer containing data to write 453 * @fri: start writing at this index 454 * @num: number of records to write 455 * 456 * The caller must hold the table mutex in @control. 457 * Return 0 on success, -errno otherwise. 458 */ 459 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 460 u8 *buf, const u32 fri, const u32 num) 461 { 462 struct amdgpu_device *adev = to_amdgpu_device(control); 463 u32 buf_size; 464 int res; 465 466 /* i2c may be unstable in gpu reset */ 467 down_read(&adev->reset_domain->sem); 468 buf_size = num * RAS_TABLE_RECORD_SIZE; 469 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 470 control->i2c_address + 471 RAS_INDEX_TO_OFFSET(control, fri), 472 buf, buf_size); 473 up_read(&adev->reset_domain->sem); 474 if (res < 0) { 475 DRM_ERROR("Writing %d EEPROM table records error:%d", 476 num, res); 477 } else if (res < buf_size) { 478 /* Short write, return error. 479 */ 480 DRM_ERROR("Wrote %d records out of %d", 481 res / RAS_TABLE_RECORD_SIZE, num); 482 res = -EIO; 483 } else { 484 res = 0; 485 } 486 487 return res; 488 } 489 490 static int 491 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 492 struct eeprom_table_record *record, 493 const u32 num) 494 { 495 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 496 u32 a, b, i; 497 u8 *buf, *pp; 498 int res; 499 500 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 501 if (!buf) 502 return -ENOMEM; 503 504 /* Encode all of them in one go. 505 */ 506 pp = buf; 507 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 508 __encode_table_record_to_buf(control, &record[i], pp); 509 510 /* update bad channel bitmap */ 511 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 512 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 513 con->update_channel_flag = true; 514 } 515 } 516 517 /* a, first record index to write into. 518 * b, last record index to write into. 519 * a = first index to read (fri) + number of records in the table, 520 * b = a + @num - 1. 521 * Let N = control->ras_max_num_record_count, then we have, 522 * case 0: 0 <= a <= b < N, 523 * just append @num records starting at a; 524 * case 1: 0 <= a < N <= b, 525 * append (N - a) records starting at a, and 526 * append the remainder, b % N + 1, starting at 0. 527 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 528 * case 2a: 0 <= a <= b < N 529 * append num records starting at a; and fix fri if b overwrote it, 530 * and since a <= b, if b overwrote it then a must've also, 531 * and if b didn't overwrite it, then a didn't also. 532 * case 2b: 0 <= b < a < N 533 * write num records starting at a, which wraps around 0=N 534 * and overwrite fri unconditionally. Now from case 2a, 535 * this means that b eclipsed fri to overwrite it and wrap 536 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 537 * set fri = b + 1 (mod N). 538 * Now, since fri is updated in every case, except the trivial case 0, 539 * the number of records present in the table after writing, is, 540 * num_recs - 1 = b - fri (mod N), and we take the positive value, 541 * by adding an arbitrary multiple of N before taking the modulo N 542 * as shown below. 543 */ 544 a = control->ras_fri + control->ras_num_recs; 545 b = a + num - 1; 546 if (b < control->ras_max_record_count) { 547 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 548 } else if (a < control->ras_max_record_count) { 549 u32 g0, g1; 550 551 g0 = control->ras_max_record_count - a; 552 g1 = b % control->ras_max_record_count + 1; 553 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 554 if (res) 555 goto Out; 556 res = __amdgpu_ras_eeprom_write(control, 557 buf + g0 * RAS_TABLE_RECORD_SIZE, 558 0, g1); 559 if (res) 560 goto Out; 561 if (g1 > control->ras_fri) 562 control->ras_fri = g1 % control->ras_max_record_count; 563 } else { 564 a %= control->ras_max_record_count; 565 b %= control->ras_max_record_count; 566 567 if (a <= b) { 568 /* Note that, b - a + 1 = num. */ 569 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 570 if (res) 571 goto Out; 572 if (b >= control->ras_fri) 573 control->ras_fri = (b + 1) % control->ras_max_record_count; 574 } else { 575 u32 g0, g1; 576 577 /* b < a, which means, we write from 578 * a to the end of the table, and from 579 * the start of the table to b. 580 */ 581 g0 = control->ras_max_record_count - a; 582 g1 = b + 1; 583 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 584 if (res) 585 goto Out; 586 res = __amdgpu_ras_eeprom_write(control, 587 buf + g0 * RAS_TABLE_RECORD_SIZE, 588 0, g1); 589 if (res) 590 goto Out; 591 control->ras_fri = g1 % control->ras_max_record_count; 592 } 593 } 594 control->ras_num_recs = 1 + (control->ras_max_record_count + b 595 - control->ras_fri) 596 % control->ras_max_record_count; 597 Out: 598 kfree(buf); 599 return res; 600 } 601 602 static int 603 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 604 { 605 struct amdgpu_device *adev = to_amdgpu_device(control); 606 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 607 u8 *buf, *pp, csum; 608 u32 buf_size; 609 int res; 610 611 /* Modify the header if it exceeds. 612 */ 613 if (amdgpu_bad_page_threshold != 0 && 614 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 615 dev_warn(adev->dev, 616 "Saved bad pages %d reaches threshold value %d\n", 617 control->ras_num_recs, ras->bad_page_cnt_threshold); 618 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 619 } 620 621 control->tbl_hdr.version = RAS_TABLE_VER; 622 control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri); 623 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 624 control->tbl_hdr.checksum = 0; 625 626 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 627 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 628 if (!buf) { 629 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 630 control->tbl_hdr.tbl_size); 631 res = -ENOMEM; 632 goto Out; 633 } 634 635 down_read(&adev->reset_domain->sem); 636 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 637 control->i2c_address + 638 control->ras_record_offset, 639 buf, buf_size); 640 up_read(&adev->reset_domain->sem); 641 if (res < 0) { 642 DRM_ERROR("EEPROM failed reading records:%d\n", 643 res); 644 goto Out; 645 } else if (res < buf_size) { 646 DRM_ERROR("EEPROM read %d out of %d bytes\n", 647 res, buf_size); 648 res = -EIO; 649 goto Out; 650 } 651 652 /* Recalc the checksum. 653 */ 654 csum = 0; 655 for (pp = buf; pp < buf + buf_size; pp++) 656 csum += *pp; 657 658 csum += __calc_hdr_byte_sum(control); 659 /* avoid sign extension when assigning to "checksum" */ 660 csum = -csum; 661 control->tbl_hdr.checksum = csum; 662 res = __write_table_header(control); 663 Out: 664 kfree(buf); 665 return res; 666 } 667 668 /** 669 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 670 * @control: pointer to control structure 671 * @record: array of records to append 672 * @num: number of records in @record array 673 * 674 * Append @num records to the table, calculate the checksum and write 675 * the table back to EEPROM. The maximum number of records that 676 * can be appended is between 1 and control->ras_max_record_count, 677 * regardless of how many records are already stored in the table. 678 * 679 * Return 0 on success or if EEPROM is not supported, -errno on error. 680 */ 681 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 682 struct eeprom_table_record *record, 683 const u32 num) 684 { 685 struct amdgpu_device *adev = to_amdgpu_device(control); 686 int res; 687 688 if (!__is_ras_eeprom_supported(adev)) 689 return 0; 690 691 if (num == 0) { 692 DRM_ERROR("will not append 0 records\n"); 693 return -EINVAL; 694 } else if (num > control->ras_max_record_count) { 695 DRM_ERROR("cannot append %d records than the size of table %d\n", 696 num, control->ras_max_record_count); 697 return -EINVAL; 698 } 699 700 mutex_lock(&control->ras_tbl_mutex); 701 702 res = amdgpu_ras_eeprom_append_table(control, record, num); 703 if (!res) 704 res = amdgpu_ras_eeprom_update_header(control); 705 if (!res) 706 amdgpu_ras_debugfs_set_ret_size(control); 707 708 mutex_unlock(&control->ras_tbl_mutex); 709 return res; 710 } 711 712 /** 713 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 714 * @control: pointer to control structure 715 * @buf: pointer to buffer to read into 716 * @fri: first record index, start reading at this index, absolute index 717 * @num: number of records to read 718 * 719 * The caller must hold the table mutex in @control. 720 * Return 0 on success, -errno otherwise. 721 */ 722 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 723 u8 *buf, const u32 fri, const u32 num) 724 { 725 struct amdgpu_device *adev = to_amdgpu_device(control); 726 u32 buf_size; 727 int res; 728 729 /* i2c may be unstable in gpu reset */ 730 down_read(&adev->reset_domain->sem); 731 buf_size = num * RAS_TABLE_RECORD_SIZE; 732 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 733 control->i2c_address + 734 RAS_INDEX_TO_OFFSET(control, fri), 735 buf, buf_size); 736 up_read(&adev->reset_domain->sem); 737 if (res < 0) { 738 DRM_ERROR("Reading %d EEPROM table records error:%d", 739 num, res); 740 } else if (res < buf_size) { 741 /* Short read, return error. 742 */ 743 DRM_ERROR("Read %d records out of %d", 744 res / RAS_TABLE_RECORD_SIZE, num); 745 res = -EIO; 746 } else { 747 res = 0; 748 } 749 750 return res; 751 } 752 753 /** 754 * amdgpu_ras_eeprom_read -- read EEPROM 755 * @control: pointer to control structure 756 * @record: array of records to read into 757 * @num: number of records in @record 758 * 759 * Reads num records from the RAS table in EEPROM and 760 * writes the data into @record array. 761 * 762 * Returns 0 on success, -errno on error. 763 */ 764 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 765 struct eeprom_table_record *record, 766 const u32 num) 767 { 768 struct amdgpu_device *adev = to_amdgpu_device(control); 769 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 770 int i, res; 771 u8 *buf, *pp; 772 u32 g0, g1; 773 774 if (!__is_ras_eeprom_supported(adev)) 775 return 0; 776 777 if (num == 0) { 778 DRM_ERROR("will not read 0 records\n"); 779 return -EINVAL; 780 } else if (num > control->ras_num_recs) { 781 DRM_ERROR("too many records to read:%d available:%d\n", 782 num, control->ras_num_recs); 783 return -EINVAL; 784 } 785 786 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 787 if (!buf) 788 return -ENOMEM; 789 790 /* Determine how many records to read, from the first record 791 * index, fri, to the end of the table, and from the beginning 792 * of the table, such that the total number of records is 793 * @num, and we handle wrap around when fri > 0 and 794 * fri + num > RAS_MAX_RECORD_COUNT. 795 * 796 * First we compute the index of the last element 797 * which would be fetched from each region, 798 * g0 is in [fri, fri + num - 1], and 799 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 800 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 801 * the last element to fetch, we set g0 to _the number_ 802 * of elements to fetch, @num, since we know that the last 803 * indexed to be fetched does not exceed the table. 804 * 805 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 806 * we set g0 to the number of elements to read 807 * until the end of the table, and g1 to the number of 808 * elements to read from the beginning of the table. 809 */ 810 g0 = control->ras_fri + num - 1; 811 g1 = g0 % control->ras_max_record_count; 812 if (g0 < control->ras_max_record_count) { 813 g0 = num; 814 g1 = 0; 815 } else { 816 g0 = control->ras_max_record_count - control->ras_fri; 817 g1 += 1; 818 } 819 820 mutex_lock(&control->ras_tbl_mutex); 821 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 822 if (res) 823 goto Out; 824 if (g1) { 825 res = __amdgpu_ras_eeprom_read(control, 826 buf + g0 * RAS_TABLE_RECORD_SIZE, 827 0, g1); 828 if (res) 829 goto Out; 830 } 831 832 res = 0; 833 834 /* Read up everything? Then transform. 835 */ 836 pp = buf; 837 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 838 __decode_table_record_from_buf(control, &record[i], pp); 839 840 /* update bad channel bitmap */ 841 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 842 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 843 con->update_channel_flag = true; 844 } 845 } 846 Out: 847 kfree(buf); 848 mutex_unlock(&control->ras_tbl_mutex); 849 850 return res; 851 } 852 853 uint32_t amdgpu_ras_eeprom_max_record_count(void) 854 { 855 return RAS_MAX_RECORD_COUNT; 856 } 857 858 static ssize_t 859 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 860 size_t size, loff_t *pos) 861 { 862 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 863 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 864 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 865 u8 data[50]; 866 int res; 867 868 if (!size) 869 return size; 870 871 if (!ras || !control) { 872 res = snprintf(data, sizeof(data), "Not supported\n"); 873 } else { 874 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 875 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 876 } 877 878 if (*pos >= res) 879 return 0; 880 881 res -= *pos; 882 res = min_t(size_t, res, size); 883 884 if (copy_to_user(buf, &data[*pos], res)) 885 return -EFAULT; 886 887 *pos += res; 888 889 return res; 890 } 891 892 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 893 .owner = THIS_MODULE, 894 .read = amdgpu_ras_debugfs_eeprom_size_read, 895 .write = NULL, 896 .llseek = default_llseek, 897 }; 898 899 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 900 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 901 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 902 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 903 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 904 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 905 906 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 907 "ignore", 908 "re", 909 "ue", 910 }; 911 912 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 913 { 914 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 915 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 916 } 917 918 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 919 { 920 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 921 eeprom_control); 922 struct dentry *de = ras->de_ras_eeprom_table; 923 924 if (de) 925 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 926 } 927 928 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 929 size_t size, loff_t *pos) 930 { 931 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 932 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 933 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 934 const size_t orig_size = size; 935 int res = -EFAULT; 936 size_t data_len; 937 938 mutex_lock(&control->ras_tbl_mutex); 939 940 /* We want *pos - data_len > 0, which means there's 941 * bytes to be printed from data. 942 */ 943 data_len = strlen(tbl_hdr_str); 944 if (*pos < data_len) { 945 data_len -= *pos; 946 data_len = min_t(size_t, data_len, size); 947 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 948 goto Out; 949 buf += data_len; 950 size -= data_len; 951 *pos += data_len; 952 } 953 954 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 955 if (*pos < data_len && size > 0) { 956 u8 data[tbl_hdr_fmt_size + 1]; 957 loff_t lpos; 958 959 snprintf(data, sizeof(data), tbl_hdr_fmt, 960 control->tbl_hdr.header, 961 control->tbl_hdr.version, 962 control->tbl_hdr.first_rec_offset, 963 control->tbl_hdr.tbl_size, 964 control->tbl_hdr.checksum); 965 966 data_len -= *pos; 967 data_len = min_t(size_t, data_len, size); 968 lpos = *pos - strlen(tbl_hdr_str); 969 if (copy_to_user(buf, &data[lpos], data_len)) 970 goto Out; 971 buf += data_len; 972 size -= data_len; 973 *pos += data_len; 974 } 975 976 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 977 if (*pos < data_len && size > 0) { 978 loff_t lpos; 979 980 data_len -= *pos; 981 data_len = min_t(size_t, data_len, size); 982 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 983 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 984 goto Out; 985 buf += data_len; 986 size -= data_len; 987 *pos += data_len; 988 } 989 990 data_len = amdgpu_ras_debugfs_table_size(control); 991 if (*pos < data_len && size > 0) { 992 u8 dare[RAS_TABLE_RECORD_SIZE]; 993 u8 data[rec_hdr_fmt_size + 1]; 994 struct eeprom_table_record record; 995 int s, r; 996 997 /* Find the starting record index 998 */ 999 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1000 strlen(rec_hdr_str); 1001 s = s / rec_hdr_fmt_size; 1002 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1003 strlen(rec_hdr_str); 1004 r = r % rec_hdr_fmt_size; 1005 1006 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1007 u32 ai = RAS_RI_TO_AI(control, s); 1008 /* Read a single record 1009 */ 1010 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1011 if (res) 1012 goto Out; 1013 __decode_table_record_from_buf(control, &record, dare); 1014 snprintf(data, sizeof(data), rec_hdr_fmt, 1015 s, 1016 RAS_INDEX_TO_OFFSET(control, ai), 1017 record_err_type_str[record.err_type], 1018 record.bank, 1019 record.ts, 1020 record.offset, 1021 record.mem_channel, 1022 record.mcumc_id, 1023 record.retired_page); 1024 1025 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1026 if (copy_to_user(buf, &data[r], data_len)) { 1027 res = -EFAULT; 1028 goto Out; 1029 } 1030 buf += data_len; 1031 size -= data_len; 1032 *pos += data_len; 1033 r = 0; 1034 } 1035 } 1036 res = 0; 1037 Out: 1038 mutex_unlock(&control->ras_tbl_mutex); 1039 return res < 0 ? res : orig_size - size; 1040 } 1041 1042 static ssize_t 1043 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1044 size_t size, loff_t *pos) 1045 { 1046 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1047 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1048 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1049 u8 data[81]; 1050 int res; 1051 1052 if (!size) 1053 return size; 1054 1055 if (!ras || !control) { 1056 res = snprintf(data, sizeof(data), "Not supported\n"); 1057 if (*pos >= res) 1058 return 0; 1059 1060 res -= *pos; 1061 res = min_t(size_t, res, size); 1062 1063 if (copy_to_user(buf, &data[*pos], res)) 1064 return -EFAULT; 1065 1066 *pos += res; 1067 1068 return res; 1069 } else { 1070 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1071 } 1072 } 1073 1074 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1075 .owner = THIS_MODULE, 1076 .read = amdgpu_ras_debugfs_eeprom_table_read, 1077 .write = NULL, 1078 .llseek = default_llseek, 1079 }; 1080 1081 /** 1082 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1083 * @control: pointer to control structure 1084 * 1085 * Check the checksum of the stored in EEPROM RAS table. 1086 * 1087 * Return 0 if the checksum is correct, 1088 * positive if it is not correct, and 1089 * -errno on I/O error. 1090 */ 1091 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1092 { 1093 struct amdgpu_device *adev = to_amdgpu_device(control); 1094 int buf_size, res; 1095 u8 csum, *buf, *pp; 1096 1097 buf_size = RAS_TABLE_HEADER_SIZE + 1098 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1099 buf = kzalloc(buf_size, GFP_KERNEL); 1100 if (!buf) { 1101 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1102 return -ENOMEM; 1103 } 1104 1105 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1106 control->i2c_address + 1107 control->ras_header_offset, 1108 buf, buf_size); 1109 if (res < buf_size) { 1110 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1111 /* On partial reads, return -EIO. 1112 */ 1113 if (res >= 0) 1114 res = -EIO; 1115 goto Out; 1116 } 1117 1118 csum = 0; 1119 for (pp = buf; pp < buf + buf_size; pp++) 1120 csum += *pp; 1121 Out: 1122 kfree(buf); 1123 return res < 0 ? res : csum; 1124 } 1125 1126 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 1127 bool *exceed_err_limit) 1128 { 1129 struct amdgpu_device *adev = to_amdgpu_device(control); 1130 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1131 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1132 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1133 int res; 1134 1135 *exceed_err_limit = false; 1136 1137 if (!__is_ras_eeprom_supported(adev)) 1138 return 0; 1139 1140 /* Verify i2c adapter is initialized */ 1141 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1142 return -ENOENT; 1143 1144 if (!__get_eeprom_i2c_addr(adev, control)) 1145 return -EINVAL; 1146 1147 control->ras_header_offset = RAS_HDR_START; 1148 control->ras_record_offset = RAS_RECORD_START; 1149 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1150 mutex_init(&control->ras_tbl_mutex); 1151 1152 /* Read the table header from EEPROM address */ 1153 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1154 control->i2c_address + control->ras_header_offset, 1155 buf, RAS_TABLE_HEADER_SIZE); 1156 if (res < RAS_TABLE_HEADER_SIZE) { 1157 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1158 return res >= 0 ? -EIO : res; 1159 } 1160 1161 __decode_table_header_from_buf(hdr, buf); 1162 1163 control->ras_num_recs = RAS_NUM_RECS(hdr); 1164 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1165 1166 if (hdr->header == RAS_TABLE_HDR_VAL) { 1167 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1168 control->ras_num_recs); 1169 res = __verify_ras_table_checksum(control); 1170 if (res) 1171 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1172 res); 1173 1174 /* Warn if we are at 90% of the threshold or above 1175 */ 1176 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1177 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1178 control->ras_num_recs, 1179 ras->bad_page_cnt_threshold); 1180 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1181 amdgpu_bad_page_threshold != 0) { 1182 res = __verify_ras_table_checksum(control); 1183 if (res) 1184 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1185 res); 1186 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1187 /* This means that, the threshold was increased since 1188 * the last time the system was booted, and now, 1189 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1190 * so that at least one more record can be saved, 1191 * before the page count threshold is reached. 1192 */ 1193 dev_info(adev->dev, 1194 "records:%d threshold:%d, resetting " 1195 "RAS table header signature", 1196 control->ras_num_recs, 1197 ras->bad_page_cnt_threshold); 1198 res = amdgpu_ras_eeprom_correct_header_tag(control, 1199 RAS_TABLE_HDR_VAL); 1200 } else { 1201 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1202 control->ras_num_recs, ras->bad_page_cnt_threshold); 1203 if (amdgpu_bad_page_threshold == -1) { 1204 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1."); 1205 res = 0; 1206 } else { 1207 *exceed_err_limit = true; 1208 dev_err(adev->dev, 1209 "RAS records:%d exceed threshold:%d, " 1210 "GPU will not be initialized. Replace this GPU or increase the threshold", 1211 control->ras_num_recs, ras->bad_page_cnt_threshold); 1212 } 1213 } 1214 } else { 1215 DRM_INFO("Creating a new EEPROM table"); 1216 1217 res = amdgpu_ras_eeprom_reset_table(control); 1218 } 1219 1220 return res < 0 ? res : 0; 1221 } 1222