1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu_ras_eeprom.h"
25 #include "amdgpu.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
28 #include "atom.h"
29 #include "amdgpu_eeprom.h"
30 #include "amdgpu_atomfirmware.h"
31 #include <linux/debugfs.h>
32 #include <linux/uaccess.h>
33 
34 #include "amdgpu_reset.h"
35 
36 /* These are memory addresses as would be seen by one or more EEPROM
37  * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
38  * set of EEPROM devices. They form a continuous memory space.
39  *
40  * The I2C device address includes the device type identifier, 1010b,
41  * which is a reserved value and indicates that this is an I2C EEPROM
42  * device. It also includes the top 3 bits of the 19 bit EEPROM memory
43  * address, namely bits 18, 17, and 16. This makes up the 7 bit
44  * address sent on the I2C bus with bit 0 being the direction bit,
45  * which is not represented here, and sent by the hardware directly.
46  *
47  * For instance,
48  *   50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
49  *   54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
50  *   56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
51  * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
52  * address memory in a device or a device on the I2C bus, depending on
53  * the status of pins 1-3. See top of amdgpu_eeprom.c.
54  *
55  * The RAS table lives either at address 0 or address 40000h of EEPROM.
56  */
57 #define EEPROM_I2C_MADDR_0      0x0
58 #define EEPROM_I2C_MADDR_4      0x40000
59 
60 /*
61  * The 2 macros bellow represent the actual size in bytes that
62  * those entities occupy in the EEPROM memory.
63  * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
64  * uses uint64 to store 6b fields such as retired_page.
65  */
66 #define RAS_TABLE_HEADER_SIZE   20
67 #define RAS_TABLE_RECORD_SIZE   24
68 
69 /* Table hdr is 'AMDR' */
70 #define RAS_TABLE_HDR_VAL       0x414d4452
71 
72 /* Bad GPU tag ‘BADG’ */
73 #define RAS_TABLE_HDR_BAD       0x42414447
74 
75 /*
76  * EEPROM Table structure v1
77  * ---------------------------------
78  * |                               |
79  * |     EEPROM TABLE HEADER       |
80  * |      ( size 20 Bytes )        |
81  * |                               |
82  * ---------------------------------
83  * |                               |
84  * |    BAD PAGE RECORD AREA       |
85  * |                               |
86  * ---------------------------------
87  */
88 
89 /* Assume 2-Mbit size EEPROM and take up the whole space. */
90 #define RAS_TBL_SIZE_BYTES      (256 * 1024)
91 #define RAS_TABLE_START         0
92 #define RAS_HDR_START           RAS_TABLE_START
93 #define RAS_RECORD_START        (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
94 #define RAS_MAX_RECORD_COUNT    ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
95 				 / RAS_TABLE_RECORD_SIZE)
96 
97 /*
98  * EEPROM Table structrue v2.1
99  * ---------------------------------
100  * |                               |
101  * |     EEPROM TABLE HEADER       |
102  * |      ( size 20 Bytes )        |
103  * |                               |
104  * ---------------------------------
105  * |                               |
106  * |     EEPROM TABLE RAS INFO     |
107  * | (available info size 4 Bytes) |
108  * |  ( reserved size 252 Bytes )  |
109  * |                               |
110  * ---------------------------------
111  * |                               |
112  * |     BAD PAGE RECORD AREA      |
113  * |                               |
114  * ---------------------------------
115  */
116 
117 /* EEPROM Table V2_1 */
118 #define RAS_TABLE_V2_1_INFO_SIZE       256
119 #define RAS_TABLE_V2_1_INFO_START      RAS_TABLE_HEADER_SIZE
120 #define RAS_RECORD_START_V2_1          (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \
121 					RAS_TABLE_V2_1_INFO_SIZE)
122 #define RAS_MAX_RECORD_COUNT_V2_1      ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \
123 					RAS_TABLE_V2_1_INFO_SIZE) \
124 					/ RAS_TABLE_RECORD_SIZE)
125 
126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
127  * offset off of RAS_TABLE_START.  That is, this is something you can
128  * add to control->i2c_address, and then tell I2C layer to read
129  * from/write to there. _N is the so called absolute index,
130  * because it starts right after the table header.
131  */
132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
133 				     (_N) * RAS_TABLE_RECORD_SIZE)
134 
135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
136 				      (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
137 
138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
139  * of "fri", return the absolute record index off of the end of
140  * the table header.
141  */
142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
143 			      (_C)->ras_max_record_count)
144 
145 #define RAS_NUM_RECS(_tbl_hdr)  (((_tbl_hdr)->tbl_size - \
146 				  RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
147 
148 #define RAS_NUM_RECS_V2_1(_tbl_hdr)  (((_tbl_hdr)->tbl_size - \
149 				       RAS_TABLE_HEADER_SIZE - \
150 				       RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)
151 
152 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
153 
154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
155 {
156 	switch (adev->ip_versions[MP1_HWIP][0]) {
157 	case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
158 	case IP_VERSION(11, 0, 7): /* Sienna cichlid */
159 	case IP_VERSION(13, 0, 0):
160 	case IP_VERSION(13, 0, 2): /* Aldebaran */
161 	case IP_VERSION(13, 0, 10):
162 		return true;
163 	case IP_VERSION(13, 0, 6):
164 		return (adev->gmc.is_app_apu) ? false : true;
165 	default:
166 		return false;
167 	}
168 }
169 
170 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
171 				  struct amdgpu_ras_eeprom_control *control)
172 {
173 	struct atom_context *atom_ctx = adev->mode_info.atom_context;
174 	u8 i2c_addr;
175 
176 	if (!control)
177 		return false;
178 
179 	if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
180 		/* The address given by VBIOS is an 8-bit, wire-format
181 		 * address, i.e. the most significant byte.
182 		 *
183 		 * Normalize it to a 19-bit EEPROM address. Remove the
184 		 * device type identifier and make it a 7-bit address;
185 		 * then make it a 19-bit EEPROM address. See top of
186 		 * amdgpu_eeprom.c.
187 		 */
188 		i2c_addr = (i2c_addr & 0x0F) >> 1;
189 		control->i2c_address = ((u32) i2c_addr) << 16;
190 
191 		return true;
192 	}
193 
194 	switch (adev->ip_versions[MP1_HWIP][0]) {
195 	case IP_VERSION(11, 0, 2):
196 		/* VEGA20 and ARCTURUS */
197 		if (adev->asic_type == CHIP_VEGA20)
198 			control->i2c_address = EEPROM_I2C_MADDR_0;
199 		else if (strnstr(atom_ctx->vbios_pn,
200 				 "D342",
201 				 sizeof(atom_ctx->vbios_pn)))
202 			control->i2c_address = EEPROM_I2C_MADDR_0;
203 		else
204 			control->i2c_address = EEPROM_I2C_MADDR_4;
205 		return true;
206 	case IP_VERSION(11, 0, 7):
207 		control->i2c_address = EEPROM_I2C_MADDR_0;
208 		return true;
209 	case IP_VERSION(13, 0, 2):
210 		if (strnstr(atom_ctx->vbios_pn, "D673",
211 			    sizeof(atom_ctx->vbios_pn)))
212 			control->i2c_address = EEPROM_I2C_MADDR_4;
213 		else
214 			control->i2c_address = EEPROM_I2C_MADDR_0;
215 		return true;
216 	case IP_VERSION(13, 0, 0):
217 		if (strnstr(atom_ctx->vbios_pn, "D707",
218 			    sizeof(atom_ctx->vbios_pn)))
219 			control->i2c_address = EEPROM_I2C_MADDR_0;
220 		else
221 			control->i2c_address = EEPROM_I2C_MADDR_4;
222 		return true;
223 	case IP_VERSION(13, 0, 6):
224 	case IP_VERSION(13, 0, 10):
225 		control->i2c_address = EEPROM_I2C_MADDR_4;
226 		return true;
227 	default:
228 		return false;
229 	}
230 }
231 
232 static void
233 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
234 			     unsigned char *buf)
235 {
236 	u32 *pp = (uint32_t *)buf;
237 
238 	pp[0] = cpu_to_le32(hdr->header);
239 	pp[1] = cpu_to_le32(hdr->version);
240 	pp[2] = cpu_to_le32(hdr->first_rec_offset);
241 	pp[3] = cpu_to_le32(hdr->tbl_size);
242 	pp[4] = cpu_to_le32(hdr->checksum);
243 }
244 
245 static void
246 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
247 			       unsigned char *buf)
248 {
249 	u32 *pp = (uint32_t *)buf;
250 
251 	hdr->header	      = le32_to_cpu(pp[0]);
252 	hdr->version	      = le32_to_cpu(pp[1]);
253 	hdr->first_rec_offset = le32_to_cpu(pp[2]);
254 	hdr->tbl_size	      = le32_to_cpu(pp[3]);
255 	hdr->checksum	      = le32_to_cpu(pp[4]);
256 }
257 
258 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
259 {
260 	u8 buf[RAS_TABLE_HEADER_SIZE];
261 	struct amdgpu_device *adev = to_amdgpu_device(control);
262 	int res;
263 
264 	memset(buf, 0, sizeof(buf));
265 	__encode_table_header_to_buf(&control->tbl_hdr, buf);
266 
267 	/* i2c may be unstable in gpu reset */
268 	down_read(&adev->reset_domain->sem);
269 	res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
270 				  control->i2c_address +
271 				  control->ras_header_offset,
272 				  buf, RAS_TABLE_HEADER_SIZE);
273 	up_read(&adev->reset_domain->sem);
274 
275 	if (res < 0) {
276 		DRM_ERROR("Failed to write EEPROM table header:%d", res);
277 	} else if (res < RAS_TABLE_HEADER_SIZE) {
278 		DRM_ERROR("Short write:%d out of %d\n",
279 			  res, RAS_TABLE_HEADER_SIZE);
280 		res = -EIO;
281 	} else {
282 		res = 0;
283 	}
284 
285 	return res;
286 }
287 
288 static void
289 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
290 			       unsigned char *buf)
291 {
292 	u32 *pp = (uint32_t *)buf;
293 	u32 tmp;
294 
295 	tmp = ((uint32_t)(rai->rma_status) & 0xFF) |
296 	      (((uint32_t)(rai->health_percent) << 8) & 0xFF00) |
297 	      (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000);
298 	pp[0] = cpu_to_le32(tmp);
299 }
300 
301 static void
302 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
303 				 unsigned char *buf)
304 {
305 	u32 *pp = (uint32_t *)buf;
306 	u32 tmp;
307 
308 	tmp = le32_to_cpu(pp[0]);
309 	rai->rma_status = tmp & 0xFF;
310 	rai->health_percent = (tmp >> 8) & 0xFF;
311 	rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF;
312 }
313 
314 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)
315 {
316 	struct amdgpu_device *adev = to_amdgpu_device(control);
317 	u8 *buf;
318 	int res;
319 
320 	buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
321 	if (!buf) {
322 		DRM_ERROR("Failed to alloc buf to write table ras info\n");
323 		return -ENOMEM;
324 	}
325 
326 	__encode_table_ras_info_to_buf(&control->tbl_rai, buf);
327 
328 	/* i2c may be unstable in gpu reset */
329 	down_read(&adev->reset_domain->sem);
330 	res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
331 				  control->i2c_address +
332 				  control->ras_info_offset,
333 				  buf, RAS_TABLE_V2_1_INFO_SIZE);
334 	up_read(&adev->reset_domain->sem);
335 
336 	if (res < 0) {
337 		DRM_ERROR("Failed to write EEPROM table ras info:%d", res);
338 	} else if (res < RAS_TABLE_V2_1_INFO_SIZE) {
339 		DRM_ERROR("Short write:%d out of %d\n",
340 			  res, RAS_TABLE_V2_1_INFO_SIZE);
341 		res = -EIO;
342 	} else {
343 		res = 0;
344 	}
345 
346 	kfree(buf);
347 
348 	return res;
349 }
350 
351 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
352 {
353 	int ii;
354 	u8  *pp, csum;
355 	size_t sz;
356 
357 	/* Header checksum, skip checksum field in the calculation */
358 	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
359 	pp = (u8 *) &control->tbl_hdr;
360 	csum = 0;
361 	for (ii = 0; ii < sz; ii++, pp++)
362 		csum += *pp;
363 
364 	return csum;
365 }
366 
367 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)
368 {
369 	int ii;
370 	u8  *pp, csum;
371 	size_t sz;
372 
373 	sz = sizeof(control->tbl_rai);
374 	pp = (u8 *) &control->tbl_rai;
375 	csum = 0;
376 	for (ii = 0; ii < sz; ii++, pp++)
377 		csum += *pp;
378 
379 	return csum;
380 }
381 
382 static int amdgpu_ras_eeprom_correct_header_tag(
383 	struct amdgpu_ras_eeprom_control *control,
384 	uint32_t header)
385 {
386 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
387 	u8 *hh;
388 	int res;
389 	u8 csum;
390 
391 	csum = -hdr->checksum;
392 
393 	hh = (void *) &hdr->header;
394 	csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
395 	hh = (void *) &header;
396 	csum += hh[0] + hh[1] + hh[2] + hh[3];
397 	csum = -csum;
398 	mutex_lock(&control->ras_tbl_mutex);
399 	hdr->header = header;
400 	hdr->checksum = csum;
401 	res = __write_table_header(control);
402 	mutex_unlock(&control->ras_tbl_mutex);
403 
404 	return res;
405 }
406 
407 /**
408  * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
409  * @control: pointer to control structure
410  *
411  * Reset the contents of the header of the RAS EEPROM table.
412  * Return 0 on success, -errno on error.
413  */
414 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
415 {
416 	struct amdgpu_device *adev = to_amdgpu_device(control);
417 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
418 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
419 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
420 	u8 csum;
421 	int res;
422 
423 	mutex_lock(&control->ras_tbl_mutex);
424 
425 	hdr->header = RAS_TABLE_HDR_VAL;
426 	if (adev->umc.ras &&
427 	    adev->umc.ras->set_eeprom_table_version)
428 		adev->umc.ras->set_eeprom_table_version(hdr);
429 	else
430 		hdr->version = RAS_TABLE_VER_V1;
431 
432 	if (hdr->version == RAS_TABLE_VER_V2_1) {
433 		hdr->first_rec_offset = RAS_RECORD_START_V2_1;
434 		hdr->tbl_size = RAS_TABLE_HEADER_SIZE +
435 				RAS_TABLE_V2_1_INFO_SIZE;
436 		rai->rma_status = GPU_HEALTH_USABLE;
437 		/**
438 		 * GPU health represented as a percentage.
439 		 * 0 means worst health, 100 means fully health.
440 		 */
441 		rai->health_percent = 100;
442 		/* ecc_page_threshold = 0 means disable bad page retirement */
443 		rai->ecc_page_threshold = con->bad_page_cnt_threshold;
444 	} else {
445 		hdr->first_rec_offset = RAS_RECORD_START;
446 		hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
447 	}
448 
449 	csum = __calc_hdr_byte_sum(control);
450 	if (hdr->version == RAS_TABLE_VER_V2_1)
451 		csum += __calc_ras_info_byte_sum(control);
452 	csum = -csum;
453 	hdr->checksum = csum;
454 	res = __write_table_header(control);
455 	if (!res && hdr->version > RAS_TABLE_VER_V1)
456 		res = __write_table_ras_info(control);
457 
458 	control->ras_num_recs = 0;
459 	control->ras_fri = 0;
460 
461 	amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);
462 
463 	control->bad_channel_bitmap = 0;
464 	amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
465 	con->update_channel_flag = false;
466 
467 	amdgpu_ras_debugfs_set_ret_size(control);
468 
469 	mutex_unlock(&control->ras_tbl_mutex);
470 
471 	return res;
472 }
473 
474 static void
475 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
476 			     struct eeprom_table_record *record,
477 			     unsigned char *buf)
478 {
479 	__le64 tmp = 0;
480 	int i = 0;
481 
482 	/* Next are all record fields according to EEPROM page spec in LE foramt */
483 	buf[i++] = record->err_type;
484 
485 	buf[i++] = record->bank;
486 
487 	tmp = cpu_to_le64(record->ts);
488 	memcpy(buf + i, &tmp, 8);
489 	i += 8;
490 
491 	tmp = cpu_to_le64((record->offset & 0xffffffffffff));
492 	memcpy(buf + i, &tmp, 6);
493 	i += 6;
494 
495 	buf[i++] = record->mem_channel;
496 	buf[i++] = record->mcumc_id;
497 
498 	tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
499 	memcpy(buf + i, &tmp, 6);
500 }
501 
502 static void
503 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
504 			       struct eeprom_table_record *record,
505 			       unsigned char *buf)
506 {
507 	__le64 tmp = 0;
508 	int i =  0;
509 
510 	/* Next are all record fields according to EEPROM page spec in LE foramt */
511 	record->err_type = buf[i++];
512 
513 	record->bank = buf[i++];
514 
515 	memcpy(&tmp, buf + i, 8);
516 	record->ts = le64_to_cpu(tmp);
517 	i += 8;
518 
519 	memcpy(&tmp, buf + i, 6);
520 	record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
521 	i += 6;
522 
523 	record->mem_channel = buf[i++];
524 	record->mcumc_id = buf[i++];
525 
526 	memcpy(&tmp, buf + i,  6);
527 	record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
528 }
529 
530 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
531 {
532 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
533 
534 	if (!__is_ras_eeprom_supported(adev) ||
535 	    !amdgpu_bad_page_threshold)
536 		return false;
537 
538 	/* skip check eeprom table for VEGA20 Gaming */
539 	if (!con)
540 		return false;
541 	else
542 		if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
543 			return false;
544 
545 	if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
546 		if (amdgpu_bad_page_threshold == -1) {
547 			dev_warn(adev->dev, "RAS records:%d exceed threshold:%d",
548 				con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold);
549 			dev_warn(adev->dev,
550 				"But GPU can be operated due to bad_page_threshold = -1.\n");
551 			return false;
552 		} else {
553 			dev_warn(adev->dev, "This GPU is in BAD status.");
554 			dev_warn(adev->dev, "Please retire it or set a larger "
555 				 "threshold value when reloading driver.\n");
556 			return true;
557 		}
558 	}
559 
560 	return false;
561 }
562 
563 /**
564  * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
565  * @control: pointer to control structure
566  * @buf: pointer to buffer containing data to write
567  * @fri: start writing at this index
568  * @num: number of records to write
569  *
570  * The caller must hold the table mutex in @control.
571  * Return 0 on success, -errno otherwise.
572  */
573 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
574 				     u8 *buf, const u32 fri, const u32 num)
575 {
576 	struct amdgpu_device *adev = to_amdgpu_device(control);
577 	u32 buf_size;
578 	int res;
579 
580 	/* i2c may be unstable in gpu reset */
581 	down_read(&adev->reset_domain->sem);
582 	buf_size = num * RAS_TABLE_RECORD_SIZE;
583 	res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
584 				  control->i2c_address +
585 				  RAS_INDEX_TO_OFFSET(control, fri),
586 				  buf, buf_size);
587 	up_read(&adev->reset_domain->sem);
588 	if (res < 0) {
589 		DRM_ERROR("Writing %d EEPROM table records error:%d",
590 			  num, res);
591 	} else if (res < buf_size) {
592 		/* Short write, return error.
593 		 */
594 		DRM_ERROR("Wrote %d records out of %d",
595 			  res / RAS_TABLE_RECORD_SIZE, num);
596 		res = -EIO;
597 	} else {
598 		res = 0;
599 	}
600 
601 	return res;
602 }
603 
604 static int
605 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
606 			       struct eeprom_table_record *record,
607 			       const u32 num)
608 {
609 	struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
610 	u32 a, b, i;
611 	u8 *buf, *pp;
612 	int res;
613 
614 	buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
615 	if (!buf)
616 		return -ENOMEM;
617 
618 	/* Encode all of them in one go.
619 	 */
620 	pp = buf;
621 	for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
622 		__encode_table_record_to_buf(control, &record[i], pp);
623 
624 		/* update bad channel bitmap */
625 		if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
626 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;
627 			con->update_channel_flag = true;
628 		}
629 	}
630 
631 	/* a, first record index to write into.
632 	 * b, last record index to write into.
633 	 * a = first index to read (fri) + number of records in the table,
634 	 * b = a + @num - 1.
635 	 * Let N = control->ras_max_num_record_count, then we have,
636 	 * case 0: 0 <= a <= b < N,
637 	 *   just append @num records starting at a;
638 	 * case 1: 0 <= a < N <= b,
639 	 *   append (N - a) records starting at a, and
640 	 *   append the remainder,  b % N + 1, starting at 0.
641 	 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
642 	 * case 2a: 0 <= a <= b < N
643 	 *   append num records starting at a; and fix fri if b overwrote it,
644 	 *   and since a <= b, if b overwrote it then a must've also,
645 	 *   and if b didn't overwrite it, then a didn't also.
646 	 * case 2b: 0 <= b < a < N
647 	 *   write num records starting at a, which wraps around 0=N
648 	 *   and overwrite fri unconditionally. Now from case 2a,
649 	 *   this means that b eclipsed fri to overwrite it and wrap
650 	 *   around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
651 	 *   set fri = b + 1 (mod N).
652 	 * Now, since fri is updated in every case, except the trivial case 0,
653 	 * the number of records present in the table after writing, is,
654 	 * num_recs - 1 = b - fri (mod N), and we take the positive value,
655 	 * by adding an arbitrary multiple of N before taking the modulo N
656 	 * as shown below.
657 	 */
658 	a = control->ras_fri + control->ras_num_recs;
659 	b = a + num  - 1;
660 	if (b < control->ras_max_record_count) {
661 		res = __amdgpu_ras_eeprom_write(control, buf, a, num);
662 	} else if (a < control->ras_max_record_count) {
663 		u32 g0, g1;
664 
665 		g0 = control->ras_max_record_count - a;
666 		g1 = b % control->ras_max_record_count + 1;
667 		res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
668 		if (res)
669 			goto Out;
670 		res = __amdgpu_ras_eeprom_write(control,
671 						buf + g0 * RAS_TABLE_RECORD_SIZE,
672 						0, g1);
673 		if (res)
674 			goto Out;
675 		if (g1 > control->ras_fri)
676 			control->ras_fri = g1 % control->ras_max_record_count;
677 	} else {
678 		a %= control->ras_max_record_count;
679 		b %= control->ras_max_record_count;
680 
681 		if (a <= b) {
682 			/* Note that, b - a + 1 = num. */
683 			res = __amdgpu_ras_eeprom_write(control, buf, a, num);
684 			if (res)
685 				goto Out;
686 			if (b >= control->ras_fri)
687 				control->ras_fri = (b + 1) % control->ras_max_record_count;
688 		} else {
689 			u32 g0, g1;
690 
691 			/* b < a, which means, we write from
692 			 * a to the end of the table, and from
693 			 * the start of the table to b.
694 			 */
695 			g0 = control->ras_max_record_count - a;
696 			g1 = b + 1;
697 			res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
698 			if (res)
699 				goto Out;
700 			res = __amdgpu_ras_eeprom_write(control,
701 							buf + g0 * RAS_TABLE_RECORD_SIZE,
702 							0, g1);
703 			if (res)
704 				goto Out;
705 			control->ras_fri = g1 % control->ras_max_record_count;
706 		}
707 	}
708 	control->ras_num_recs = 1 + (control->ras_max_record_count + b
709 				     - control->ras_fri)
710 		% control->ras_max_record_count;
711 Out:
712 	kfree(buf);
713 	return res;
714 }
715 
716 static int
717 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
718 {
719 	struct amdgpu_device *adev = to_amdgpu_device(control);
720 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
721 	u8 *buf, *pp, csum;
722 	u32 buf_size;
723 	int res;
724 
725 	/* Modify the header if it exceeds.
726 	 */
727 	if (amdgpu_bad_page_threshold != 0 &&
728 	    control->ras_num_recs >= ras->bad_page_cnt_threshold) {
729 		dev_warn(adev->dev,
730 			"Saved bad pages %d reaches threshold value %d\n",
731 			control->ras_num_recs, ras->bad_page_cnt_threshold);
732 		control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
733 		if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) {
734 			control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;
735 			control->tbl_rai.health_percent = 0;
736 		}
737 	}
738 
739 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
740 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
741 					    RAS_TABLE_V2_1_INFO_SIZE +
742 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
743 	else
744 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
745 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
746 	control->tbl_hdr.checksum = 0;
747 
748 	buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
749 	buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
750 	if (!buf) {
751 		DRM_ERROR("allocating memory for table of size %d bytes failed\n",
752 			  control->tbl_hdr.tbl_size);
753 		res = -ENOMEM;
754 		goto Out;
755 	}
756 
757 	down_read(&adev->reset_domain->sem);
758 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
759 				 control->i2c_address +
760 				 control->ras_record_offset,
761 				 buf, buf_size);
762 	up_read(&adev->reset_domain->sem);
763 	if (res < 0) {
764 		DRM_ERROR("EEPROM failed reading records:%d\n",
765 			  res);
766 		goto Out;
767 	} else if (res < buf_size) {
768 		DRM_ERROR("EEPROM read %d out of %d bytes\n",
769 			  res, buf_size);
770 		res = -EIO;
771 		goto Out;
772 	}
773 
774 	/**
775 	 * bad page records have been stored in eeprom,
776 	 * now calculate gpu health percent
777 	 */
778 	if (amdgpu_bad_page_threshold != 0 &&
779 	    control->tbl_hdr.version == RAS_TABLE_VER_V2_1 &&
780 	    control->ras_num_recs < ras->bad_page_cnt_threshold)
781 		control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold -
782 						   control->ras_num_recs) * 100) /
783 						   ras->bad_page_cnt_threshold;
784 
785 	/* Recalc the checksum.
786 	 */
787 	csum = 0;
788 	for (pp = buf; pp < buf + buf_size; pp++)
789 		csum += *pp;
790 
791 	csum += __calc_hdr_byte_sum(control);
792 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
793 		csum += __calc_ras_info_byte_sum(control);
794 	/* avoid sign extension when assigning to "checksum" */
795 	csum = -csum;
796 	control->tbl_hdr.checksum = csum;
797 	res = __write_table_header(control);
798 	if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1)
799 		res = __write_table_ras_info(control);
800 Out:
801 	kfree(buf);
802 	return res;
803 }
804 
805 /**
806  * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
807  * @control: pointer to control structure
808  * @record: array of records to append
809  * @num: number of records in @record array
810  *
811  * Append @num records to the table, calculate the checksum and write
812  * the table back to EEPROM. The maximum number of records that
813  * can be appended is between 1 and control->ras_max_record_count,
814  * regardless of how many records are already stored in the table.
815  *
816  * Return 0 on success or if EEPROM is not supported, -errno on error.
817  */
818 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
819 			     struct eeprom_table_record *record,
820 			     const u32 num)
821 {
822 	struct amdgpu_device *adev = to_amdgpu_device(control);
823 	int res;
824 
825 	if (!__is_ras_eeprom_supported(adev))
826 		return 0;
827 
828 	if (num == 0) {
829 		DRM_ERROR("will not append 0 records\n");
830 		return -EINVAL;
831 	} else if (num > control->ras_max_record_count) {
832 		DRM_ERROR("cannot append %d records than the size of table %d\n",
833 			  num, control->ras_max_record_count);
834 		return -EINVAL;
835 	}
836 
837 	mutex_lock(&control->ras_tbl_mutex);
838 
839 	res = amdgpu_ras_eeprom_append_table(control, record, num);
840 	if (!res)
841 		res = amdgpu_ras_eeprom_update_header(control);
842 	if (!res)
843 		amdgpu_ras_debugfs_set_ret_size(control);
844 
845 	mutex_unlock(&control->ras_tbl_mutex);
846 	return res;
847 }
848 
849 /**
850  * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
851  * @control: pointer to control structure
852  * @buf: pointer to buffer to read into
853  * @fri: first record index, start reading at this index, absolute index
854  * @num: number of records to read
855  *
856  * The caller must hold the table mutex in @control.
857  * Return 0 on success, -errno otherwise.
858  */
859 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
860 				    u8 *buf, const u32 fri, const u32 num)
861 {
862 	struct amdgpu_device *adev = to_amdgpu_device(control);
863 	u32 buf_size;
864 	int res;
865 
866 	/* i2c may be unstable in gpu reset */
867 	down_read(&adev->reset_domain->sem);
868 	buf_size = num * RAS_TABLE_RECORD_SIZE;
869 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
870 				 control->i2c_address +
871 				 RAS_INDEX_TO_OFFSET(control, fri),
872 				 buf, buf_size);
873 	up_read(&adev->reset_domain->sem);
874 	if (res < 0) {
875 		DRM_ERROR("Reading %d EEPROM table records error:%d",
876 			  num, res);
877 	} else if (res < buf_size) {
878 		/* Short read, return error.
879 		 */
880 		DRM_ERROR("Read %d records out of %d",
881 			  res / RAS_TABLE_RECORD_SIZE, num);
882 		res = -EIO;
883 	} else {
884 		res = 0;
885 	}
886 
887 	return res;
888 }
889 
890 /**
891  * amdgpu_ras_eeprom_read -- read EEPROM
892  * @control: pointer to control structure
893  * @record: array of records to read into
894  * @num: number of records in @record
895  *
896  * Reads num records from the RAS table in EEPROM and
897  * writes the data into @record array.
898  *
899  * Returns 0 on success, -errno on error.
900  */
901 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
902 			   struct eeprom_table_record *record,
903 			   const u32 num)
904 {
905 	struct amdgpu_device *adev = to_amdgpu_device(control);
906 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
907 	int i, res;
908 	u8 *buf, *pp;
909 	u32 g0, g1;
910 
911 	if (!__is_ras_eeprom_supported(adev))
912 		return 0;
913 
914 	if (num == 0) {
915 		DRM_ERROR("will not read 0 records\n");
916 		return -EINVAL;
917 	} else if (num > control->ras_num_recs) {
918 		DRM_ERROR("too many records to read:%d available:%d\n",
919 			  num, control->ras_num_recs);
920 		return -EINVAL;
921 	}
922 
923 	buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
924 	if (!buf)
925 		return -ENOMEM;
926 
927 	/* Determine how many records to read, from the first record
928 	 * index, fri, to the end of the table, and from the beginning
929 	 * of the table, such that the total number of records is
930 	 * @num, and we handle wrap around when fri > 0 and
931 	 * fri + num > RAS_MAX_RECORD_COUNT.
932 	 *
933 	 * First we compute the index of the last element
934 	 * which would be fetched from each region,
935 	 * g0 is in [fri, fri + num - 1], and
936 	 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
937 	 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
938 	 * the last element to fetch, we set g0 to _the number_
939 	 * of elements to fetch, @num, since we know that the last
940 	 * indexed to be fetched does not exceed the table.
941 	 *
942 	 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
943 	 * we set g0 to the number of elements to read
944 	 * until the end of the table, and g1 to the number of
945 	 * elements to read from the beginning of the table.
946 	 */
947 	g0 = control->ras_fri + num - 1;
948 	g1 = g0 % control->ras_max_record_count;
949 	if (g0 < control->ras_max_record_count) {
950 		g0 = num;
951 		g1 = 0;
952 	} else {
953 		g0 = control->ras_max_record_count - control->ras_fri;
954 		g1 += 1;
955 	}
956 
957 	mutex_lock(&control->ras_tbl_mutex);
958 	res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
959 	if (res)
960 		goto Out;
961 	if (g1) {
962 		res = __amdgpu_ras_eeprom_read(control,
963 					       buf + g0 * RAS_TABLE_RECORD_SIZE,
964 					       0, g1);
965 		if (res)
966 			goto Out;
967 	}
968 
969 	res = 0;
970 
971 	/* Read up everything? Then transform.
972 	 */
973 	pp = buf;
974 	for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
975 		__decode_table_record_from_buf(control, &record[i], pp);
976 
977 		/* update bad channel bitmap */
978 		if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
979 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;
980 			con->update_channel_flag = true;
981 		}
982 	}
983 Out:
984 	kfree(buf);
985 	mutex_unlock(&control->ras_tbl_mutex);
986 
987 	return res;
988 }
989 
990 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)
991 {
992 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
993 		return RAS_MAX_RECORD_COUNT_V2_1;
994 	else
995 		return RAS_MAX_RECORD_COUNT;
996 }
997 
998 static ssize_t
999 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
1000 				    size_t size, loff_t *pos)
1001 {
1002 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1003 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1004 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1005 	u8 data[50];
1006 	int res;
1007 
1008 	if (!size)
1009 		return size;
1010 
1011 	if (!ras || !control) {
1012 		res = snprintf(data, sizeof(data), "Not supported\n");
1013 	} else {
1014 		res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
1015 			       RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
1016 	}
1017 
1018 	if (*pos >= res)
1019 		return 0;
1020 
1021 	res -= *pos;
1022 	res = min_t(size_t, res, size);
1023 
1024 	if (copy_to_user(buf, &data[*pos], res))
1025 		return -EFAULT;
1026 
1027 	*pos += res;
1028 
1029 	return res;
1030 }
1031 
1032 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
1033 	.owner = THIS_MODULE,
1034 	.read = amdgpu_ras_debugfs_eeprom_size_read,
1035 	.write = NULL,
1036 	.llseek = default_llseek,
1037 };
1038 
1039 static const char *tbl_hdr_str = " Signature    Version  FirstOffs       Size   Checksum\n";
1040 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
1041 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
1042 static const char *rec_hdr_str = "Index  Offset ErrType Bank/CU          TimeStamp      Offs/Addr MemChl MCUMCID    RetiredPage\n";
1043 static const char *rec_hdr_fmt = "%5d 0x%05X %7s    0x%02X 0x%016llX 0x%012llX   0x%02X    0x%02X 0x%012llX\n";
1044 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
1045 
1046 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
1047 	"ignore",
1048 	"re",
1049 	"ue",
1050 };
1051 
1052 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
1053 {
1054 	return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
1055 		strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
1056 }
1057 
1058 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
1059 {
1060 	struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
1061 					      eeprom_control);
1062 	struct dentry *de = ras->de_ras_eeprom_table;
1063 
1064 	if (de)
1065 		d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
1066 }
1067 
1068 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
1069 					     size_t size, loff_t *pos)
1070 {
1071 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1072 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1073 	struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
1074 	const size_t orig_size = size;
1075 	int res = -EFAULT;
1076 	size_t data_len;
1077 
1078 	mutex_lock(&control->ras_tbl_mutex);
1079 
1080 	/* We want *pos - data_len > 0, which means there's
1081 	 * bytes to be printed from data.
1082 	 */
1083 	data_len = strlen(tbl_hdr_str);
1084 	if (*pos < data_len) {
1085 		data_len -= *pos;
1086 		data_len = min_t(size_t, data_len, size);
1087 		if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
1088 			goto Out;
1089 		buf += data_len;
1090 		size -= data_len;
1091 		*pos += data_len;
1092 	}
1093 
1094 	data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
1095 	if (*pos < data_len && size > 0) {
1096 		u8 data[tbl_hdr_fmt_size + 1];
1097 		loff_t lpos;
1098 
1099 		snprintf(data, sizeof(data), tbl_hdr_fmt,
1100 			 control->tbl_hdr.header,
1101 			 control->tbl_hdr.version,
1102 			 control->tbl_hdr.first_rec_offset,
1103 			 control->tbl_hdr.tbl_size,
1104 			 control->tbl_hdr.checksum);
1105 
1106 		data_len -= *pos;
1107 		data_len = min_t(size_t, data_len, size);
1108 		lpos = *pos - strlen(tbl_hdr_str);
1109 		if (copy_to_user(buf, &data[lpos], data_len))
1110 			goto Out;
1111 		buf += data_len;
1112 		size -= data_len;
1113 		*pos += data_len;
1114 	}
1115 
1116 	data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
1117 	if (*pos < data_len && size > 0) {
1118 		loff_t lpos;
1119 
1120 		data_len -= *pos;
1121 		data_len = min_t(size_t, data_len, size);
1122 		lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
1123 		if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
1124 			goto Out;
1125 		buf += data_len;
1126 		size -= data_len;
1127 		*pos += data_len;
1128 	}
1129 
1130 	data_len = amdgpu_ras_debugfs_table_size(control);
1131 	if (*pos < data_len && size > 0) {
1132 		u8 dare[RAS_TABLE_RECORD_SIZE];
1133 		u8 data[rec_hdr_fmt_size + 1];
1134 		struct eeprom_table_record record;
1135 		int s, r;
1136 
1137 		/* Find the starting record index
1138 		 */
1139 		s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1140 			strlen(rec_hdr_str);
1141 		s = s / rec_hdr_fmt_size;
1142 		r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1143 			strlen(rec_hdr_str);
1144 		r = r % rec_hdr_fmt_size;
1145 
1146 		for ( ; size > 0 && s < control->ras_num_recs; s++) {
1147 			u32 ai = RAS_RI_TO_AI(control, s);
1148 			/* Read a single record
1149 			 */
1150 			res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
1151 			if (res)
1152 				goto Out;
1153 			__decode_table_record_from_buf(control, &record, dare);
1154 			snprintf(data, sizeof(data), rec_hdr_fmt,
1155 				 s,
1156 				 RAS_INDEX_TO_OFFSET(control, ai),
1157 				 record_err_type_str[record.err_type],
1158 				 record.bank,
1159 				 record.ts,
1160 				 record.offset,
1161 				 record.mem_channel,
1162 				 record.mcumc_id,
1163 				 record.retired_page);
1164 
1165 			data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
1166 			if (copy_to_user(buf, &data[r], data_len)) {
1167 				res = -EFAULT;
1168 				goto Out;
1169 			}
1170 			buf += data_len;
1171 			size -= data_len;
1172 			*pos += data_len;
1173 			r = 0;
1174 		}
1175 	}
1176 	res = 0;
1177 Out:
1178 	mutex_unlock(&control->ras_tbl_mutex);
1179 	return res < 0 ? res : orig_size - size;
1180 }
1181 
1182 static ssize_t
1183 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
1184 				     size_t size, loff_t *pos)
1185 {
1186 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1187 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1188 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1189 	u8 data[81];
1190 	int res;
1191 
1192 	if (!size)
1193 		return size;
1194 
1195 	if (!ras || !control) {
1196 		res = snprintf(data, sizeof(data), "Not supported\n");
1197 		if (*pos >= res)
1198 			return 0;
1199 
1200 		res -= *pos;
1201 		res = min_t(size_t, res, size);
1202 
1203 		if (copy_to_user(buf, &data[*pos], res))
1204 			return -EFAULT;
1205 
1206 		*pos += res;
1207 
1208 		return res;
1209 	} else {
1210 		return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
1211 	}
1212 }
1213 
1214 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
1215 	.owner = THIS_MODULE,
1216 	.read = amdgpu_ras_debugfs_eeprom_table_read,
1217 	.write = NULL,
1218 	.llseek = default_llseek,
1219 };
1220 
1221 /**
1222  * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
1223  * @control: pointer to control structure
1224  *
1225  * Check the checksum of the stored in EEPROM RAS table.
1226  *
1227  * Return 0 if the checksum is correct,
1228  * positive if it is not correct, and
1229  * -errno on I/O error.
1230  */
1231 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1232 {
1233 	struct amdgpu_device *adev = to_amdgpu_device(control);
1234 	int buf_size, res;
1235 	u8  csum, *buf, *pp;
1236 
1237 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
1238 		buf_size = RAS_TABLE_HEADER_SIZE +
1239 			   RAS_TABLE_V2_1_INFO_SIZE +
1240 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1241 	else
1242 		buf_size = RAS_TABLE_HEADER_SIZE +
1243 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1244 
1245 	buf = kzalloc(buf_size, GFP_KERNEL);
1246 	if (!buf) {
1247 		DRM_ERROR("Out of memory checking RAS table checksum.\n");
1248 		return -ENOMEM;
1249 	}
1250 
1251 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1252 				 control->i2c_address +
1253 				 control->ras_header_offset,
1254 				 buf, buf_size);
1255 	if (res < buf_size) {
1256 		DRM_ERROR("Partial read for checksum, res:%d\n", res);
1257 		/* On partial reads, return -EIO.
1258 		 */
1259 		if (res >= 0)
1260 			res = -EIO;
1261 		goto Out;
1262 	}
1263 
1264 	csum = 0;
1265 	for (pp = buf; pp < buf + buf_size; pp++)
1266 		csum += *pp;
1267 Out:
1268 	kfree(buf);
1269 	return res < 0 ? res : csum;
1270 }
1271 
1272 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)
1273 {
1274 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
1275 	struct amdgpu_device *adev = to_amdgpu_device(control);
1276 	unsigned char *buf;
1277 	int res;
1278 
1279 	buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
1280 	if (!buf) {
1281 		DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n");
1282 		return -ENOMEM;
1283 	}
1284 
1285 	/**
1286 	 * EEPROM table V2_1 supports ras info,
1287 	 * read EEPROM table ras info
1288 	 */
1289 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1290 				 control->i2c_address + control->ras_info_offset,
1291 				 buf, RAS_TABLE_V2_1_INFO_SIZE);
1292 	if (res < RAS_TABLE_V2_1_INFO_SIZE) {
1293 		DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res);
1294 		res = res >= 0 ? -EIO : res;
1295 		goto Out;
1296 	}
1297 
1298 	__decode_table_ras_info_from_buf(rai, buf);
1299 
1300 Out:
1301 	kfree(buf);
1302 	return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res;
1303 }
1304 
1305 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
1306 			   bool *exceed_err_limit)
1307 {
1308 	struct amdgpu_device *adev = to_amdgpu_device(control);
1309 	unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1310 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1311 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1312 	int res;
1313 
1314 	*exceed_err_limit = false;
1315 
1316 	if (!__is_ras_eeprom_supported(adev))
1317 		return 0;
1318 
1319 	/* Verify i2c adapter is initialized */
1320 	if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1321 		return -ENOENT;
1322 
1323 	if (!__get_eeprom_i2c_addr(adev, control))
1324 		return -EINVAL;
1325 
1326 	control->ras_header_offset = RAS_HDR_START;
1327 	control->ras_info_offset = RAS_TABLE_V2_1_INFO_START;
1328 	mutex_init(&control->ras_tbl_mutex);
1329 
1330 	/* Read the table header from EEPROM address */
1331 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1332 				 control->i2c_address + control->ras_header_offset,
1333 				 buf, RAS_TABLE_HEADER_SIZE);
1334 	if (res < RAS_TABLE_HEADER_SIZE) {
1335 		DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1336 		return res >= 0 ? -EIO : res;
1337 	}
1338 
1339 	__decode_table_header_from_buf(hdr, buf);
1340 
1341 	if (hdr->version == RAS_TABLE_VER_V2_1) {
1342 		control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);
1343 		control->ras_record_offset = RAS_RECORD_START_V2_1;
1344 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;
1345 	} else {
1346 		control->ras_num_recs = RAS_NUM_RECS(hdr);
1347 		control->ras_record_offset = RAS_RECORD_START;
1348 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1349 	}
1350 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1351 
1352 	if (hdr->header == RAS_TABLE_HDR_VAL) {
1353 		DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1354 				 control->ras_num_recs);
1355 
1356 		if (hdr->version == RAS_TABLE_VER_V2_1) {
1357 			res = __read_table_ras_info(control);
1358 			if (res)
1359 				return res;
1360 		}
1361 
1362 		res = __verify_ras_table_checksum(control);
1363 		if (res)
1364 			DRM_ERROR("RAS table incorrect checksum or error:%d\n",
1365 				  res);
1366 
1367 		/* Warn if we are at 90% of the threshold or above
1368 		 */
1369 		if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold)
1370 			dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
1371 					control->ras_num_recs,
1372 					ras->bad_page_cnt_threshold);
1373 	} else if (hdr->header == RAS_TABLE_HDR_BAD &&
1374 		   amdgpu_bad_page_threshold != 0) {
1375 		if (hdr->version == RAS_TABLE_VER_V2_1) {
1376 			res = __read_table_ras_info(control);
1377 			if (res)
1378 				return res;
1379 		}
1380 
1381 		res = __verify_ras_table_checksum(control);
1382 		if (res)
1383 			DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
1384 				  res);
1385 		if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
1386 			/* This means that, the threshold was increased since
1387 			 * the last time the system was booted, and now,
1388 			 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1389 			 * so that at least one more record can be saved,
1390 			 * before the page count threshold is reached.
1391 			 */
1392 			dev_info(adev->dev,
1393 				 "records:%d threshold:%d, resetting "
1394 				 "RAS table header signature",
1395 				 control->ras_num_recs,
1396 				 ras->bad_page_cnt_threshold);
1397 			res = amdgpu_ras_eeprom_correct_header_tag(control,
1398 								   RAS_TABLE_HDR_VAL);
1399 		} else {
1400 			dev_err(adev->dev, "RAS records:%d exceed threshold:%d",
1401 				control->ras_num_recs, ras->bad_page_cnt_threshold);
1402 			if (amdgpu_bad_page_threshold == -1) {
1403 				dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1.");
1404 				res = 0;
1405 			} else {
1406 				*exceed_err_limit = true;
1407 				dev_err(adev->dev,
1408 					"RAS records:%d exceed threshold:%d, "
1409 					"GPU will not be initialized. Replace this GPU or increase the threshold",
1410 					control->ras_num_recs, ras->bad_page_cnt_threshold);
1411 			}
1412 		}
1413 	} else {
1414 		DRM_INFO("Creating a new EEPROM table");
1415 
1416 		res = amdgpu_ras_eeprom_reset_table(control);
1417 	}
1418 
1419 	return res < 0 ? res : 0;
1420 }
1421