1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (adev->ip_versions[MP1_HWIP][0]) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 10): 162 return true; 163 case IP_VERSION(13, 0, 6): 164 return (adev->gmc.is_app_apu) ? false : true; 165 default: 166 return false; 167 } 168 } 169 170 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 171 struct amdgpu_ras_eeprom_control *control) 172 { 173 struct atom_context *atom_ctx = adev->mode_info.atom_context; 174 u8 i2c_addr; 175 176 if (!control) 177 return false; 178 179 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 180 /* The address given by VBIOS is an 8-bit, wire-format 181 * address, i.e. the most significant byte. 182 * 183 * Normalize it to a 19-bit EEPROM address. Remove the 184 * device type identifier and make it a 7-bit address; 185 * then make it a 19-bit EEPROM address. See top of 186 * amdgpu_eeprom.c. 187 */ 188 i2c_addr = (i2c_addr & 0x0F) >> 1; 189 control->i2c_address = ((u32) i2c_addr) << 16; 190 191 return true; 192 } 193 194 switch (adev->ip_versions[MP1_HWIP][0]) { 195 case IP_VERSION(11, 0, 2): 196 /* VEGA20 and ARCTURUS */ 197 if (adev->asic_type == CHIP_VEGA20) 198 control->i2c_address = EEPROM_I2C_MADDR_0; 199 else if (strnstr(atom_ctx->vbios_pn, 200 "D342", 201 sizeof(atom_ctx->vbios_pn))) 202 control->i2c_address = EEPROM_I2C_MADDR_0; 203 else 204 control->i2c_address = EEPROM_I2C_MADDR_4; 205 return true; 206 case IP_VERSION(11, 0, 7): 207 control->i2c_address = EEPROM_I2C_MADDR_0; 208 return true; 209 case IP_VERSION(13, 0, 2): 210 if (strnstr(atom_ctx->vbios_pn, "D673", 211 sizeof(atom_ctx->vbios_pn))) 212 control->i2c_address = EEPROM_I2C_MADDR_4; 213 else 214 control->i2c_address = EEPROM_I2C_MADDR_0; 215 return true; 216 case IP_VERSION(13, 0, 0): 217 case IP_VERSION(13, 0, 6): 218 case IP_VERSION(13, 0, 10): 219 control->i2c_address = EEPROM_I2C_MADDR_4; 220 return true; 221 default: 222 return false; 223 } 224 } 225 226 static void 227 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 228 unsigned char *buf) 229 { 230 u32 *pp = (uint32_t *)buf; 231 232 pp[0] = cpu_to_le32(hdr->header); 233 pp[1] = cpu_to_le32(hdr->version); 234 pp[2] = cpu_to_le32(hdr->first_rec_offset); 235 pp[3] = cpu_to_le32(hdr->tbl_size); 236 pp[4] = cpu_to_le32(hdr->checksum); 237 } 238 239 static void 240 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 241 unsigned char *buf) 242 { 243 u32 *pp = (uint32_t *)buf; 244 245 hdr->header = le32_to_cpu(pp[0]); 246 hdr->version = le32_to_cpu(pp[1]); 247 hdr->first_rec_offset = le32_to_cpu(pp[2]); 248 hdr->tbl_size = le32_to_cpu(pp[3]); 249 hdr->checksum = le32_to_cpu(pp[4]); 250 } 251 252 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 253 { 254 u8 buf[RAS_TABLE_HEADER_SIZE]; 255 struct amdgpu_device *adev = to_amdgpu_device(control); 256 int res; 257 258 memset(buf, 0, sizeof(buf)); 259 __encode_table_header_to_buf(&control->tbl_hdr, buf); 260 261 /* i2c may be unstable in gpu reset */ 262 down_read(&adev->reset_domain->sem); 263 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 264 control->i2c_address + 265 control->ras_header_offset, 266 buf, RAS_TABLE_HEADER_SIZE); 267 up_read(&adev->reset_domain->sem); 268 269 if (res < 0) { 270 DRM_ERROR("Failed to write EEPROM table header:%d", res); 271 } else if (res < RAS_TABLE_HEADER_SIZE) { 272 DRM_ERROR("Short write:%d out of %d\n", 273 res, RAS_TABLE_HEADER_SIZE); 274 res = -EIO; 275 } else { 276 res = 0; 277 } 278 279 return res; 280 } 281 282 static void 283 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 284 unsigned char *buf) 285 { 286 u32 *pp = (uint32_t *)buf; 287 u32 tmp; 288 289 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 290 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 291 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 292 pp[0] = cpu_to_le32(tmp); 293 } 294 295 static void 296 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 297 unsigned char *buf) 298 { 299 u32 *pp = (uint32_t *)buf; 300 u32 tmp; 301 302 tmp = le32_to_cpu(pp[0]); 303 rai->rma_status = tmp & 0xFF; 304 rai->health_percent = (tmp >> 8) & 0xFF; 305 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 306 } 307 308 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 309 { 310 struct amdgpu_device *adev = to_amdgpu_device(control); 311 u8 *buf; 312 int res; 313 314 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 315 if (!buf) { 316 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 317 return -ENOMEM; 318 } 319 320 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 321 322 /* i2c may be unstable in gpu reset */ 323 down_read(&adev->reset_domain->sem); 324 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 325 control->i2c_address + 326 control->ras_info_offset, 327 buf, RAS_TABLE_V2_1_INFO_SIZE); 328 up_read(&adev->reset_domain->sem); 329 330 if (res < 0) { 331 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 332 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 333 DRM_ERROR("Short write:%d out of %d\n", 334 res, RAS_TABLE_V2_1_INFO_SIZE); 335 res = -EIO; 336 } else { 337 res = 0; 338 } 339 340 kfree(buf); 341 342 return res; 343 } 344 345 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 346 { 347 int ii; 348 u8 *pp, csum; 349 size_t sz; 350 351 /* Header checksum, skip checksum field in the calculation */ 352 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 353 pp = (u8 *) &control->tbl_hdr; 354 csum = 0; 355 for (ii = 0; ii < sz; ii++, pp++) 356 csum += *pp; 357 358 return csum; 359 } 360 361 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 362 { 363 int ii; 364 u8 *pp, csum; 365 size_t sz; 366 367 sz = sizeof(control->tbl_rai); 368 pp = (u8 *) &control->tbl_rai; 369 csum = 0; 370 for (ii = 0; ii < sz; ii++, pp++) 371 csum += *pp; 372 373 return csum; 374 } 375 376 static int amdgpu_ras_eeprom_correct_header_tag( 377 struct amdgpu_ras_eeprom_control *control, 378 uint32_t header) 379 { 380 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 381 u8 *hh; 382 int res; 383 u8 csum; 384 385 csum = -hdr->checksum; 386 387 hh = (void *) &hdr->header; 388 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 389 hh = (void *) &header; 390 csum += hh[0] + hh[1] + hh[2] + hh[3]; 391 csum = -csum; 392 mutex_lock(&control->ras_tbl_mutex); 393 hdr->header = header; 394 hdr->checksum = csum; 395 res = __write_table_header(control); 396 mutex_unlock(&control->ras_tbl_mutex); 397 398 return res; 399 } 400 401 /** 402 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 403 * @control: pointer to control structure 404 * 405 * Reset the contents of the header of the RAS EEPROM table. 406 * Return 0 on success, -errno on error. 407 */ 408 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 409 { 410 struct amdgpu_device *adev = to_amdgpu_device(control); 411 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 412 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 413 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 414 u8 csum; 415 int res; 416 417 mutex_lock(&control->ras_tbl_mutex); 418 419 hdr->header = RAS_TABLE_HDR_VAL; 420 if (adev->umc.ras && 421 adev->umc.ras->set_eeprom_table_version) 422 adev->umc.ras->set_eeprom_table_version(hdr); 423 else 424 hdr->version = RAS_TABLE_VER_V1; 425 426 if (hdr->version == RAS_TABLE_VER_V2_1) { 427 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 428 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 429 RAS_TABLE_V2_1_INFO_SIZE; 430 rai->rma_status = GPU_HEALTH_USABLE; 431 /** 432 * GPU health represented as a percentage. 433 * 0 means worst health, 100 means fully health. 434 */ 435 rai->health_percent = 100; 436 /* ecc_page_threshold = 0 means disable bad page retirement */ 437 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 438 } else { 439 hdr->first_rec_offset = RAS_RECORD_START; 440 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 441 } 442 443 csum = __calc_hdr_byte_sum(control); 444 if (hdr->version == RAS_TABLE_VER_V2_1) 445 csum += __calc_ras_info_byte_sum(control); 446 csum = -csum; 447 hdr->checksum = csum; 448 res = __write_table_header(control); 449 if (!res && hdr->version > RAS_TABLE_VER_V1) 450 res = __write_table_ras_info(control); 451 452 control->ras_num_recs = 0; 453 control->ras_fri = 0; 454 455 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 456 457 control->bad_channel_bitmap = 0; 458 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 459 con->update_channel_flag = false; 460 461 amdgpu_ras_debugfs_set_ret_size(control); 462 463 mutex_unlock(&control->ras_tbl_mutex); 464 465 return res; 466 } 467 468 static void 469 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 470 struct eeprom_table_record *record, 471 unsigned char *buf) 472 { 473 __le64 tmp = 0; 474 int i = 0; 475 476 /* Next are all record fields according to EEPROM page spec in LE foramt */ 477 buf[i++] = record->err_type; 478 479 buf[i++] = record->bank; 480 481 tmp = cpu_to_le64(record->ts); 482 memcpy(buf + i, &tmp, 8); 483 i += 8; 484 485 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 486 memcpy(buf + i, &tmp, 6); 487 i += 6; 488 489 buf[i++] = record->mem_channel; 490 buf[i++] = record->mcumc_id; 491 492 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 493 memcpy(buf + i, &tmp, 6); 494 } 495 496 static void 497 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 498 struct eeprom_table_record *record, 499 unsigned char *buf) 500 { 501 __le64 tmp = 0; 502 int i = 0; 503 504 /* Next are all record fields according to EEPROM page spec in LE foramt */ 505 record->err_type = buf[i++]; 506 507 record->bank = buf[i++]; 508 509 memcpy(&tmp, buf + i, 8); 510 record->ts = le64_to_cpu(tmp); 511 i += 8; 512 513 memcpy(&tmp, buf + i, 6); 514 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 515 i += 6; 516 517 record->mem_channel = buf[i++]; 518 record->mcumc_id = buf[i++]; 519 520 memcpy(&tmp, buf + i, 6); 521 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 522 } 523 524 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 525 { 526 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 527 528 if (!__is_ras_eeprom_supported(adev) || 529 !amdgpu_bad_page_threshold) 530 return false; 531 532 /* skip check eeprom table for VEGA20 Gaming */ 533 if (!con) 534 return false; 535 else 536 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 537 return false; 538 539 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 540 if (amdgpu_bad_page_threshold == -1) { 541 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 542 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold); 543 dev_warn(adev->dev, 544 "But GPU can be operated due to bad_page_threshold = -1.\n"); 545 return false; 546 } else { 547 dev_warn(adev->dev, "This GPU is in BAD status."); 548 dev_warn(adev->dev, "Please retire it or set a larger " 549 "threshold value when reloading driver.\n"); 550 return true; 551 } 552 } 553 554 return false; 555 } 556 557 /** 558 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 559 * @control: pointer to control structure 560 * @buf: pointer to buffer containing data to write 561 * @fri: start writing at this index 562 * @num: number of records to write 563 * 564 * The caller must hold the table mutex in @control. 565 * Return 0 on success, -errno otherwise. 566 */ 567 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 568 u8 *buf, const u32 fri, const u32 num) 569 { 570 struct amdgpu_device *adev = to_amdgpu_device(control); 571 u32 buf_size; 572 int res; 573 574 /* i2c may be unstable in gpu reset */ 575 down_read(&adev->reset_domain->sem); 576 buf_size = num * RAS_TABLE_RECORD_SIZE; 577 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 578 control->i2c_address + 579 RAS_INDEX_TO_OFFSET(control, fri), 580 buf, buf_size); 581 up_read(&adev->reset_domain->sem); 582 if (res < 0) { 583 DRM_ERROR("Writing %d EEPROM table records error:%d", 584 num, res); 585 } else if (res < buf_size) { 586 /* Short write, return error. 587 */ 588 DRM_ERROR("Wrote %d records out of %d", 589 res / RAS_TABLE_RECORD_SIZE, num); 590 res = -EIO; 591 } else { 592 res = 0; 593 } 594 595 return res; 596 } 597 598 static int 599 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 600 struct eeprom_table_record *record, 601 const u32 num) 602 { 603 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 604 u32 a, b, i; 605 u8 *buf, *pp; 606 int res; 607 608 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 609 if (!buf) 610 return -ENOMEM; 611 612 /* Encode all of them in one go. 613 */ 614 pp = buf; 615 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 616 __encode_table_record_to_buf(control, &record[i], pp); 617 618 /* update bad channel bitmap */ 619 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 620 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 621 con->update_channel_flag = true; 622 } 623 } 624 625 /* a, first record index to write into. 626 * b, last record index to write into. 627 * a = first index to read (fri) + number of records in the table, 628 * b = a + @num - 1. 629 * Let N = control->ras_max_num_record_count, then we have, 630 * case 0: 0 <= a <= b < N, 631 * just append @num records starting at a; 632 * case 1: 0 <= a < N <= b, 633 * append (N - a) records starting at a, and 634 * append the remainder, b % N + 1, starting at 0. 635 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 636 * case 2a: 0 <= a <= b < N 637 * append num records starting at a; and fix fri if b overwrote it, 638 * and since a <= b, if b overwrote it then a must've also, 639 * and if b didn't overwrite it, then a didn't also. 640 * case 2b: 0 <= b < a < N 641 * write num records starting at a, which wraps around 0=N 642 * and overwrite fri unconditionally. Now from case 2a, 643 * this means that b eclipsed fri to overwrite it and wrap 644 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 645 * set fri = b + 1 (mod N). 646 * Now, since fri is updated in every case, except the trivial case 0, 647 * the number of records present in the table after writing, is, 648 * num_recs - 1 = b - fri (mod N), and we take the positive value, 649 * by adding an arbitrary multiple of N before taking the modulo N 650 * as shown below. 651 */ 652 a = control->ras_fri + control->ras_num_recs; 653 b = a + num - 1; 654 if (b < control->ras_max_record_count) { 655 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 656 } else if (a < control->ras_max_record_count) { 657 u32 g0, g1; 658 659 g0 = control->ras_max_record_count - a; 660 g1 = b % control->ras_max_record_count + 1; 661 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 662 if (res) 663 goto Out; 664 res = __amdgpu_ras_eeprom_write(control, 665 buf + g0 * RAS_TABLE_RECORD_SIZE, 666 0, g1); 667 if (res) 668 goto Out; 669 if (g1 > control->ras_fri) 670 control->ras_fri = g1 % control->ras_max_record_count; 671 } else { 672 a %= control->ras_max_record_count; 673 b %= control->ras_max_record_count; 674 675 if (a <= b) { 676 /* Note that, b - a + 1 = num. */ 677 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 678 if (res) 679 goto Out; 680 if (b >= control->ras_fri) 681 control->ras_fri = (b + 1) % control->ras_max_record_count; 682 } else { 683 u32 g0, g1; 684 685 /* b < a, which means, we write from 686 * a to the end of the table, and from 687 * the start of the table to b. 688 */ 689 g0 = control->ras_max_record_count - a; 690 g1 = b + 1; 691 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 692 if (res) 693 goto Out; 694 res = __amdgpu_ras_eeprom_write(control, 695 buf + g0 * RAS_TABLE_RECORD_SIZE, 696 0, g1); 697 if (res) 698 goto Out; 699 control->ras_fri = g1 % control->ras_max_record_count; 700 } 701 } 702 control->ras_num_recs = 1 + (control->ras_max_record_count + b 703 - control->ras_fri) 704 % control->ras_max_record_count; 705 Out: 706 kfree(buf); 707 return res; 708 } 709 710 static int 711 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 712 { 713 struct amdgpu_device *adev = to_amdgpu_device(control); 714 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 715 u8 *buf, *pp, csum; 716 u32 buf_size; 717 int res; 718 719 /* Modify the header if it exceeds. 720 */ 721 if (amdgpu_bad_page_threshold != 0 && 722 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 723 dev_warn(adev->dev, 724 "Saved bad pages %d reaches threshold value %d\n", 725 control->ras_num_recs, ras->bad_page_cnt_threshold); 726 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 727 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { 728 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 729 control->tbl_rai.health_percent = 0; 730 } 731 } 732 733 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 734 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 735 RAS_TABLE_V2_1_INFO_SIZE + 736 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 737 else 738 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 739 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 740 control->tbl_hdr.checksum = 0; 741 742 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 743 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 744 if (!buf) { 745 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 746 control->tbl_hdr.tbl_size); 747 res = -ENOMEM; 748 goto Out; 749 } 750 751 down_read(&adev->reset_domain->sem); 752 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 753 control->i2c_address + 754 control->ras_record_offset, 755 buf, buf_size); 756 up_read(&adev->reset_domain->sem); 757 if (res < 0) { 758 DRM_ERROR("EEPROM failed reading records:%d\n", 759 res); 760 goto Out; 761 } else if (res < buf_size) { 762 DRM_ERROR("EEPROM read %d out of %d bytes\n", 763 res, buf_size); 764 res = -EIO; 765 goto Out; 766 } 767 768 /** 769 * bad page records have been stored in eeprom, 770 * now calculate gpu health percent 771 */ 772 if (amdgpu_bad_page_threshold != 0 && 773 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && 774 control->ras_num_recs < ras->bad_page_cnt_threshold) 775 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 776 control->ras_num_recs) * 100) / 777 ras->bad_page_cnt_threshold; 778 779 /* Recalc the checksum. 780 */ 781 csum = 0; 782 for (pp = buf; pp < buf + buf_size; pp++) 783 csum += *pp; 784 785 csum += __calc_hdr_byte_sum(control); 786 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 787 csum += __calc_ras_info_byte_sum(control); 788 /* avoid sign extension when assigning to "checksum" */ 789 csum = -csum; 790 control->tbl_hdr.checksum = csum; 791 res = __write_table_header(control); 792 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 793 res = __write_table_ras_info(control); 794 Out: 795 kfree(buf); 796 return res; 797 } 798 799 /** 800 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 801 * @control: pointer to control structure 802 * @record: array of records to append 803 * @num: number of records in @record array 804 * 805 * Append @num records to the table, calculate the checksum and write 806 * the table back to EEPROM. The maximum number of records that 807 * can be appended is between 1 and control->ras_max_record_count, 808 * regardless of how many records are already stored in the table. 809 * 810 * Return 0 on success or if EEPROM is not supported, -errno on error. 811 */ 812 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 813 struct eeprom_table_record *record, 814 const u32 num) 815 { 816 struct amdgpu_device *adev = to_amdgpu_device(control); 817 int res; 818 819 if (!__is_ras_eeprom_supported(adev)) 820 return 0; 821 822 if (num == 0) { 823 DRM_ERROR("will not append 0 records\n"); 824 return -EINVAL; 825 } else if (num > control->ras_max_record_count) { 826 DRM_ERROR("cannot append %d records than the size of table %d\n", 827 num, control->ras_max_record_count); 828 return -EINVAL; 829 } 830 831 mutex_lock(&control->ras_tbl_mutex); 832 833 res = amdgpu_ras_eeprom_append_table(control, record, num); 834 if (!res) 835 res = amdgpu_ras_eeprom_update_header(control); 836 if (!res) 837 amdgpu_ras_debugfs_set_ret_size(control); 838 839 mutex_unlock(&control->ras_tbl_mutex); 840 return res; 841 } 842 843 /** 844 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 845 * @control: pointer to control structure 846 * @buf: pointer to buffer to read into 847 * @fri: first record index, start reading at this index, absolute index 848 * @num: number of records to read 849 * 850 * The caller must hold the table mutex in @control. 851 * Return 0 on success, -errno otherwise. 852 */ 853 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 854 u8 *buf, const u32 fri, const u32 num) 855 { 856 struct amdgpu_device *adev = to_amdgpu_device(control); 857 u32 buf_size; 858 int res; 859 860 /* i2c may be unstable in gpu reset */ 861 down_read(&adev->reset_domain->sem); 862 buf_size = num * RAS_TABLE_RECORD_SIZE; 863 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 864 control->i2c_address + 865 RAS_INDEX_TO_OFFSET(control, fri), 866 buf, buf_size); 867 up_read(&adev->reset_domain->sem); 868 if (res < 0) { 869 DRM_ERROR("Reading %d EEPROM table records error:%d", 870 num, res); 871 } else if (res < buf_size) { 872 /* Short read, return error. 873 */ 874 DRM_ERROR("Read %d records out of %d", 875 res / RAS_TABLE_RECORD_SIZE, num); 876 res = -EIO; 877 } else { 878 res = 0; 879 } 880 881 return res; 882 } 883 884 /** 885 * amdgpu_ras_eeprom_read -- read EEPROM 886 * @control: pointer to control structure 887 * @record: array of records to read into 888 * @num: number of records in @record 889 * 890 * Reads num records from the RAS table in EEPROM and 891 * writes the data into @record array. 892 * 893 * Returns 0 on success, -errno on error. 894 */ 895 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 896 struct eeprom_table_record *record, 897 const u32 num) 898 { 899 struct amdgpu_device *adev = to_amdgpu_device(control); 900 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 901 int i, res; 902 u8 *buf, *pp; 903 u32 g0, g1; 904 905 if (!__is_ras_eeprom_supported(adev)) 906 return 0; 907 908 if (num == 0) { 909 DRM_ERROR("will not read 0 records\n"); 910 return -EINVAL; 911 } else if (num > control->ras_num_recs) { 912 DRM_ERROR("too many records to read:%d available:%d\n", 913 num, control->ras_num_recs); 914 return -EINVAL; 915 } 916 917 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 918 if (!buf) 919 return -ENOMEM; 920 921 /* Determine how many records to read, from the first record 922 * index, fri, to the end of the table, and from the beginning 923 * of the table, such that the total number of records is 924 * @num, and we handle wrap around when fri > 0 and 925 * fri + num > RAS_MAX_RECORD_COUNT. 926 * 927 * First we compute the index of the last element 928 * which would be fetched from each region, 929 * g0 is in [fri, fri + num - 1], and 930 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 931 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 932 * the last element to fetch, we set g0 to _the number_ 933 * of elements to fetch, @num, since we know that the last 934 * indexed to be fetched does not exceed the table. 935 * 936 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 937 * we set g0 to the number of elements to read 938 * until the end of the table, and g1 to the number of 939 * elements to read from the beginning of the table. 940 */ 941 g0 = control->ras_fri + num - 1; 942 g1 = g0 % control->ras_max_record_count; 943 if (g0 < control->ras_max_record_count) { 944 g0 = num; 945 g1 = 0; 946 } else { 947 g0 = control->ras_max_record_count - control->ras_fri; 948 g1 += 1; 949 } 950 951 mutex_lock(&control->ras_tbl_mutex); 952 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 953 if (res) 954 goto Out; 955 if (g1) { 956 res = __amdgpu_ras_eeprom_read(control, 957 buf + g0 * RAS_TABLE_RECORD_SIZE, 958 0, g1); 959 if (res) 960 goto Out; 961 } 962 963 res = 0; 964 965 /* Read up everything? Then transform. 966 */ 967 pp = buf; 968 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 969 __decode_table_record_from_buf(control, &record[i], pp); 970 971 /* update bad channel bitmap */ 972 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 973 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 974 con->update_channel_flag = true; 975 } 976 } 977 Out: 978 kfree(buf); 979 mutex_unlock(&control->ras_tbl_mutex); 980 981 return res; 982 } 983 984 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 985 { 986 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 987 return RAS_MAX_RECORD_COUNT_V2_1; 988 else 989 return RAS_MAX_RECORD_COUNT; 990 } 991 992 static ssize_t 993 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 994 size_t size, loff_t *pos) 995 { 996 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 997 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 998 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 999 u8 data[50]; 1000 int res; 1001 1002 if (!size) 1003 return size; 1004 1005 if (!ras || !control) { 1006 res = snprintf(data, sizeof(data), "Not supported\n"); 1007 } else { 1008 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1009 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1010 } 1011 1012 if (*pos >= res) 1013 return 0; 1014 1015 res -= *pos; 1016 res = min_t(size_t, res, size); 1017 1018 if (copy_to_user(buf, &data[*pos], res)) 1019 return -EFAULT; 1020 1021 *pos += res; 1022 1023 return res; 1024 } 1025 1026 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1027 .owner = THIS_MODULE, 1028 .read = amdgpu_ras_debugfs_eeprom_size_read, 1029 .write = NULL, 1030 .llseek = default_llseek, 1031 }; 1032 1033 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1034 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1035 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1036 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1037 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1038 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1039 1040 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1041 "ignore", 1042 "re", 1043 "ue", 1044 }; 1045 1046 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1047 { 1048 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1049 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1050 } 1051 1052 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1053 { 1054 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1055 eeprom_control); 1056 struct dentry *de = ras->de_ras_eeprom_table; 1057 1058 if (de) 1059 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1060 } 1061 1062 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1063 size_t size, loff_t *pos) 1064 { 1065 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1066 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1067 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1068 const size_t orig_size = size; 1069 int res = -EFAULT; 1070 size_t data_len; 1071 1072 mutex_lock(&control->ras_tbl_mutex); 1073 1074 /* We want *pos - data_len > 0, which means there's 1075 * bytes to be printed from data. 1076 */ 1077 data_len = strlen(tbl_hdr_str); 1078 if (*pos < data_len) { 1079 data_len -= *pos; 1080 data_len = min_t(size_t, data_len, size); 1081 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1082 goto Out; 1083 buf += data_len; 1084 size -= data_len; 1085 *pos += data_len; 1086 } 1087 1088 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1089 if (*pos < data_len && size > 0) { 1090 u8 data[tbl_hdr_fmt_size + 1]; 1091 loff_t lpos; 1092 1093 snprintf(data, sizeof(data), tbl_hdr_fmt, 1094 control->tbl_hdr.header, 1095 control->tbl_hdr.version, 1096 control->tbl_hdr.first_rec_offset, 1097 control->tbl_hdr.tbl_size, 1098 control->tbl_hdr.checksum); 1099 1100 data_len -= *pos; 1101 data_len = min_t(size_t, data_len, size); 1102 lpos = *pos - strlen(tbl_hdr_str); 1103 if (copy_to_user(buf, &data[lpos], data_len)) 1104 goto Out; 1105 buf += data_len; 1106 size -= data_len; 1107 *pos += data_len; 1108 } 1109 1110 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1111 if (*pos < data_len && size > 0) { 1112 loff_t lpos; 1113 1114 data_len -= *pos; 1115 data_len = min_t(size_t, data_len, size); 1116 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1117 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1118 goto Out; 1119 buf += data_len; 1120 size -= data_len; 1121 *pos += data_len; 1122 } 1123 1124 data_len = amdgpu_ras_debugfs_table_size(control); 1125 if (*pos < data_len && size > 0) { 1126 u8 dare[RAS_TABLE_RECORD_SIZE]; 1127 u8 data[rec_hdr_fmt_size + 1]; 1128 struct eeprom_table_record record; 1129 int s, r; 1130 1131 /* Find the starting record index 1132 */ 1133 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1134 strlen(rec_hdr_str); 1135 s = s / rec_hdr_fmt_size; 1136 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1137 strlen(rec_hdr_str); 1138 r = r % rec_hdr_fmt_size; 1139 1140 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1141 u32 ai = RAS_RI_TO_AI(control, s); 1142 /* Read a single record 1143 */ 1144 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1145 if (res) 1146 goto Out; 1147 __decode_table_record_from_buf(control, &record, dare); 1148 snprintf(data, sizeof(data), rec_hdr_fmt, 1149 s, 1150 RAS_INDEX_TO_OFFSET(control, ai), 1151 record_err_type_str[record.err_type], 1152 record.bank, 1153 record.ts, 1154 record.offset, 1155 record.mem_channel, 1156 record.mcumc_id, 1157 record.retired_page); 1158 1159 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1160 if (copy_to_user(buf, &data[r], data_len)) { 1161 res = -EFAULT; 1162 goto Out; 1163 } 1164 buf += data_len; 1165 size -= data_len; 1166 *pos += data_len; 1167 r = 0; 1168 } 1169 } 1170 res = 0; 1171 Out: 1172 mutex_unlock(&control->ras_tbl_mutex); 1173 return res < 0 ? res : orig_size - size; 1174 } 1175 1176 static ssize_t 1177 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1178 size_t size, loff_t *pos) 1179 { 1180 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1181 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1182 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1183 u8 data[81]; 1184 int res; 1185 1186 if (!size) 1187 return size; 1188 1189 if (!ras || !control) { 1190 res = snprintf(data, sizeof(data), "Not supported\n"); 1191 if (*pos >= res) 1192 return 0; 1193 1194 res -= *pos; 1195 res = min_t(size_t, res, size); 1196 1197 if (copy_to_user(buf, &data[*pos], res)) 1198 return -EFAULT; 1199 1200 *pos += res; 1201 1202 return res; 1203 } else { 1204 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1205 } 1206 } 1207 1208 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1209 .owner = THIS_MODULE, 1210 .read = amdgpu_ras_debugfs_eeprom_table_read, 1211 .write = NULL, 1212 .llseek = default_llseek, 1213 }; 1214 1215 /** 1216 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1217 * @control: pointer to control structure 1218 * 1219 * Check the checksum of the stored in EEPROM RAS table. 1220 * 1221 * Return 0 if the checksum is correct, 1222 * positive if it is not correct, and 1223 * -errno on I/O error. 1224 */ 1225 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1226 { 1227 struct amdgpu_device *adev = to_amdgpu_device(control); 1228 int buf_size, res; 1229 u8 csum, *buf, *pp; 1230 1231 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1232 buf_size = RAS_TABLE_HEADER_SIZE + 1233 RAS_TABLE_V2_1_INFO_SIZE + 1234 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1235 else 1236 buf_size = RAS_TABLE_HEADER_SIZE + 1237 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1238 1239 buf = kzalloc(buf_size, GFP_KERNEL); 1240 if (!buf) { 1241 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1242 return -ENOMEM; 1243 } 1244 1245 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1246 control->i2c_address + 1247 control->ras_header_offset, 1248 buf, buf_size); 1249 if (res < buf_size) { 1250 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1251 /* On partial reads, return -EIO. 1252 */ 1253 if (res >= 0) 1254 res = -EIO; 1255 goto Out; 1256 } 1257 1258 csum = 0; 1259 for (pp = buf; pp < buf + buf_size; pp++) 1260 csum += *pp; 1261 Out: 1262 kfree(buf); 1263 return res < 0 ? res : csum; 1264 } 1265 1266 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1267 { 1268 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1269 struct amdgpu_device *adev = to_amdgpu_device(control); 1270 unsigned char *buf; 1271 int res; 1272 1273 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1274 if (!buf) { 1275 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1276 return -ENOMEM; 1277 } 1278 1279 /** 1280 * EEPROM table V2_1 supports ras info, 1281 * read EEPROM table ras info 1282 */ 1283 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1284 control->i2c_address + control->ras_info_offset, 1285 buf, RAS_TABLE_V2_1_INFO_SIZE); 1286 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1287 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1288 res = res >= 0 ? -EIO : res; 1289 goto Out; 1290 } 1291 1292 __decode_table_ras_info_from_buf(rai, buf); 1293 1294 Out: 1295 kfree(buf); 1296 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1297 } 1298 1299 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 1300 bool *exceed_err_limit) 1301 { 1302 struct amdgpu_device *adev = to_amdgpu_device(control); 1303 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1304 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1305 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1306 int res; 1307 1308 *exceed_err_limit = false; 1309 1310 if (!__is_ras_eeprom_supported(adev)) 1311 return 0; 1312 1313 /* Verify i2c adapter is initialized */ 1314 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1315 return -ENOENT; 1316 1317 if (!__get_eeprom_i2c_addr(adev, control)) 1318 return -EINVAL; 1319 1320 control->ras_header_offset = RAS_HDR_START; 1321 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1322 mutex_init(&control->ras_tbl_mutex); 1323 1324 /* Read the table header from EEPROM address */ 1325 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1326 control->i2c_address + control->ras_header_offset, 1327 buf, RAS_TABLE_HEADER_SIZE); 1328 if (res < RAS_TABLE_HEADER_SIZE) { 1329 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1330 return res >= 0 ? -EIO : res; 1331 } 1332 1333 __decode_table_header_from_buf(hdr, buf); 1334 1335 if (hdr->version == RAS_TABLE_VER_V2_1) { 1336 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1337 control->ras_record_offset = RAS_RECORD_START_V2_1; 1338 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1339 } else { 1340 control->ras_num_recs = RAS_NUM_RECS(hdr); 1341 control->ras_record_offset = RAS_RECORD_START; 1342 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1343 } 1344 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1345 1346 if (hdr->header == RAS_TABLE_HDR_VAL) { 1347 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1348 control->ras_num_recs); 1349 1350 if (hdr->version == RAS_TABLE_VER_V2_1) { 1351 res = __read_table_ras_info(control); 1352 if (res) 1353 return res; 1354 } 1355 1356 res = __verify_ras_table_checksum(control); 1357 if (res) 1358 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1359 res); 1360 1361 /* Warn if we are at 90% of the threshold or above 1362 */ 1363 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1364 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1365 control->ras_num_recs, 1366 ras->bad_page_cnt_threshold); 1367 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1368 amdgpu_bad_page_threshold != 0) { 1369 if (hdr->version == RAS_TABLE_VER_V2_1) { 1370 res = __read_table_ras_info(control); 1371 if (res) 1372 return res; 1373 } 1374 1375 res = __verify_ras_table_checksum(control); 1376 if (res) 1377 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1378 res); 1379 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1380 /* This means that, the threshold was increased since 1381 * the last time the system was booted, and now, 1382 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1383 * so that at least one more record can be saved, 1384 * before the page count threshold is reached. 1385 */ 1386 dev_info(adev->dev, 1387 "records:%d threshold:%d, resetting " 1388 "RAS table header signature", 1389 control->ras_num_recs, 1390 ras->bad_page_cnt_threshold); 1391 res = amdgpu_ras_eeprom_correct_header_tag(control, 1392 RAS_TABLE_HDR_VAL); 1393 } else { 1394 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1395 control->ras_num_recs, ras->bad_page_cnt_threshold); 1396 if (amdgpu_bad_page_threshold == -1) { 1397 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1."); 1398 res = 0; 1399 } else { 1400 *exceed_err_limit = true; 1401 dev_err(adev->dev, 1402 "RAS records:%d exceed threshold:%d, " 1403 "GPU will not be initialized. Replace this GPU or increase the threshold", 1404 control->ras_num_recs, ras->bad_page_cnt_threshold); 1405 } 1406 } 1407 } else { 1408 DRM_INFO("Creating a new EEPROM table"); 1409 1410 res = amdgpu_ras_eeprom_reset_table(control); 1411 } 1412 1413 return res < 0 ? res : 0; 1414 } 1415