1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "smu_v11_0_i2c.h" 29 30 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8 31 #define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0 32 33 /* 34 * The 2 macros bellow represent the actual size in bytes that 35 * those entities occupy in the EEPROM memory. 36 * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 37 * uses uint64 to store 6b fields such as retired_page. 38 */ 39 #define EEPROM_TABLE_HEADER_SIZE 20 40 #define EEPROM_TABLE_RECORD_SIZE 24 41 42 #define EEPROM_ADDRESS_SIZE 0x2 43 44 /* Table hdr is 'AMDR' */ 45 #define EEPROM_TABLE_HDR_VAL 0x414d4452 46 #define EEPROM_TABLE_VER 0x00010000 47 48 /* Assume 2 Mbit size */ 49 #define EEPROM_SIZE_BYTES 256000 50 #define EEPROM_PAGE__SIZE_BYTES 256 51 #define EEPROM_HDR_START 0 52 #define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE) 53 #define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE) 54 #define EEPROM_ADDR_MSB_MASK GENMASK(17, 8) 55 56 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev 57 58 static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr, 59 unsigned char *buff) 60 { 61 uint32_t *pp = (uint32_t *) buff; 62 63 pp[0] = cpu_to_le32(hdr->header); 64 pp[1] = cpu_to_le32(hdr->version); 65 pp[2] = cpu_to_le32(hdr->first_rec_offset); 66 pp[3] = cpu_to_le32(hdr->tbl_size); 67 pp[4] = cpu_to_le32(hdr->checksum); 68 } 69 70 static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr, 71 unsigned char *buff) 72 { 73 uint32_t *pp = (uint32_t *)buff; 74 75 hdr->header = le32_to_cpu(pp[0]); 76 hdr->version = le32_to_cpu(pp[1]); 77 hdr->first_rec_offset = le32_to_cpu(pp[2]); 78 hdr->tbl_size = le32_to_cpu(pp[3]); 79 hdr->checksum = le32_to_cpu(pp[4]); 80 } 81 82 static int __update_table_header(struct amdgpu_ras_eeprom_control *control, 83 unsigned char *buff) 84 { 85 int ret = 0; 86 struct i2c_msg msg = { 87 .addr = 0, 88 .flags = 0, 89 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, 90 .buf = buff, 91 }; 92 93 94 *(uint16_t *)buff = EEPROM_HDR_START; 95 __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE); 96 97 msg.addr = control->i2c_address; 98 99 ret = i2c_transfer(&control->eeprom_accessor, &msg, 1); 100 if (ret < 1) 101 DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret); 102 103 return ret; 104 } 105 106 107 108 static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control) 109 { 110 int i; 111 uint32_t tbl_sum = 0; 112 113 /* Header checksum, skip checksum field in the calculation */ 114 for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++) 115 tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i); 116 117 return tbl_sum; 118 } 119 120 static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records, 121 int num) 122 { 123 int i, j; 124 uint32_t tbl_sum = 0; 125 126 /* Records checksum */ 127 for (i = 0; i < num; i++) { 128 struct eeprom_table_record *record = &records[i]; 129 130 for (j = 0; j < sizeof(*record); j++) { 131 tbl_sum += *(((unsigned char *)record) + j); 132 } 133 } 134 135 return tbl_sum; 136 } 137 138 static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control, 139 struct eeprom_table_record *records, int num) 140 { 141 return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num); 142 } 143 144 /* Checksum = 256 -((sum of all table entries) mod 256) */ 145 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control, 146 struct eeprom_table_record *records, int num, 147 uint32_t old_hdr_byte_sum) 148 { 149 /* 150 * This will update the table sum with new records. 151 * 152 * TODO: What happens when the EEPROM table is to be wrapped around 153 * and old records from start will get overridden. 154 */ 155 156 /* need to recalculate updated header byte sum */ 157 control->tbl_byte_sum -= old_hdr_byte_sum; 158 control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num); 159 160 control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256); 161 } 162 163 /* table sum mod 256 + checksum must equals 256 */ 164 static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control, 165 struct eeprom_table_record *records, int num) 166 { 167 control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num); 168 169 if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) { 170 DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum); 171 return false; 172 } 173 174 return true; 175 } 176 177 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 178 { 179 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 }; 180 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 181 int ret = 0; 182 183 mutex_lock(&control->tbl_mutex); 184 185 hdr->header = EEPROM_TABLE_HDR_VAL; 186 hdr->version = EEPROM_TABLE_VER; 187 hdr->first_rec_offset = EEPROM_RECORD_START; 188 hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE; 189 190 control->tbl_byte_sum = 0; 191 __update_tbl_checksum(control, NULL, 0, 0); 192 control->next_addr = EEPROM_RECORD_START; 193 194 ret = __update_table_header(control, buff); 195 196 mutex_unlock(&control->tbl_mutex); 197 198 return ret; 199 200 } 201 202 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 203 { 204 int ret = 0; 205 struct amdgpu_device *adev = to_amdgpu_device(control); 206 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 }; 207 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 208 struct i2c_msg msg = { 209 .addr = 0, 210 .flags = I2C_M_RD, 211 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, 212 .buf = buff, 213 }; 214 215 mutex_init(&control->tbl_mutex); 216 217 switch (adev->asic_type) { 218 case CHIP_VEGA20: 219 control->i2c_address = EEPROM_I2C_TARGET_ADDR_VEGA20; 220 ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor); 221 break; 222 223 case CHIP_ARCTURUS: 224 control->i2c_address = EEPROM_I2C_TARGET_ADDR_ARCTURUS; 225 ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor); 226 break; 227 228 default: 229 return 0; 230 } 231 232 if (ret) { 233 DRM_ERROR("Failed to init I2C controller, ret:%d", ret); 234 return ret; 235 } 236 237 msg.addr = control->i2c_address; 238 239 /* Read/Create table header from EEPROM address 0 */ 240 ret = i2c_transfer(&control->eeprom_accessor, &msg, 1); 241 if (ret < 1) { 242 DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret); 243 return ret; 244 } 245 246 __decode_table_header_from_buff(hdr, &buff[2]); 247 248 if (hdr->header == EEPROM_TABLE_HDR_VAL) { 249 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) / 250 EEPROM_TABLE_RECORD_SIZE; 251 control->tbl_byte_sum = __calc_hdr_byte_sum(control); 252 control->next_addr = EEPROM_RECORD_START; 253 254 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 255 control->num_recs); 256 257 } else { 258 DRM_INFO("Creating new EEPROM table"); 259 260 ret = amdgpu_ras_eeprom_reset_table(control); 261 } 262 263 return ret == 1 ? 0 : -EIO; 264 } 265 266 void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control) 267 { 268 struct amdgpu_device *adev = to_amdgpu_device(control); 269 270 switch (adev->asic_type) { 271 case CHIP_VEGA20: 272 smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor); 273 break; 274 case CHIP_ARCTURUS: 275 smu_i2c_eeprom_fini(&adev->smu, &control->eeprom_accessor); 276 break; 277 278 default: 279 return; 280 } 281 } 282 283 static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control, 284 struct eeprom_table_record *record, 285 unsigned char *buff) 286 { 287 __le64 tmp = 0; 288 int i = 0; 289 290 /* Next are all record fields according to EEPROM page spec in LE foramt */ 291 buff[i++] = record->err_type; 292 293 buff[i++] = record->bank; 294 295 tmp = cpu_to_le64(record->ts); 296 memcpy(buff + i, &tmp, 8); 297 i += 8; 298 299 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 300 memcpy(buff + i, &tmp, 6); 301 i += 6; 302 303 buff[i++] = record->mem_channel; 304 buff[i++] = record->mcumc_id; 305 306 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 307 memcpy(buff + i, &tmp, 6); 308 } 309 310 static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control, 311 struct eeprom_table_record *record, 312 unsigned char *buff) 313 { 314 __le64 tmp = 0; 315 int i = 0; 316 317 /* Next are all record fields according to EEPROM page spec in LE foramt */ 318 record->err_type = buff[i++]; 319 320 record->bank = buff[i++]; 321 322 memcpy(&tmp, buff + i, 8); 323 record->ts = le64_to_cpu(tmp); 324 i += 8; 325 326 memcpy(&tmp, buff + i, 6); 327 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 328 i += 6; 329 330 record->mem_channel = buff[i++]; 331 record->mcumc_id = buff[i++]; 332 333 memcpy(&tmp, buff + i, 6); 334 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 335 } 336 337 /* 338 * When reaching end of EEPROM memory jump back to 0 record address 339 * When next record access will go beyond EEPROM page boundary modify bits A17/A8 340 * in I2C selector to go to next page 341 */ 342 static uint32_t __correct_eeprom_dest_address(uint32_t curr_address) 343 { 344 uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE; 345 346 /* When all EEPROM memory used jump back to 0 address */ 347 if (next_address > EEPROM_SIZE_BYTES) { 348 DRM_INFO("Reached end of EEPROM memory, jumping to 0 " 349 "and overriding old record"); 350 return EEPROM_RECORD_START; 351 } 352 353 /* 354 * To check if we overflow page boundary compare next address with 355 * current and see if bits 17/8 of the EEPROM address will change 356 * If they do start from the next 256b page 357 * 358 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2 359 */ 360 if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) { 361 DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx", 362 (next_address & EEPROM_ADDR_MSB_MASK)); 363 364 return (next_address & EEPROM_ADDR_MSB_MASK); 365 } 366 367 return curr_address; 368 } 369 370 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, 371 struct eeprom_table_record *records, 372 bool write, 373 int num) 374 { 375 int i, ret = 0; 376 struct i2c_msg *msgs, *msg; 377 unsigned char *buffs, *buff; 378 struct eeprom_table_record *record; 379 struct amdgpu_device *adev = to_amdgpu_device(control); 380 381 if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS) 382 return 0; 383 384 buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE, 385 GFP_KERNEL); 386 if (!buffs) 387 return -ENOMEM; 388 389 mutex_lock(&control->tbl_mutex); 390 391 msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL); 392 if (!msgs) { 393 ret = -ENOMEM; 394 goto free_buff; 395 } 396 397 /* In case of overflow just start from beginning to not lose newest records */ 398 if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES)) 399 control->next_addr = EEPROM_RECORD_START; 400 401 402 /* 403 * TODO Currently makes EEPROM writes for each record, this creates 404 * internal fragmentation. Optimized the code to do full page write of 405 * 256b 406 */ 407 for (i = 0; i < num; i++) { 408 buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)]; 409 record = &records[i]; 410 msg = &msgs[i]; 411 412 control->next_addr = __correct_eeprom_dest_address(control->next_addr); 413 414 /* 415 * Update bits 16,17 of EEPROM address in I2C address by setting them 416 * to bits 1,2 of Device address byte 417 */ 418 msg->addr = control->i2c_address | 419 ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15); 420 msg->flags = write ? 0 : I2C_M_RD; 421 msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE; 422 msg->buf = buff; 423 424 /* Insert the EEPROM dest addess, bits 0-15 */ 425 buff[0] = ((control->next_addr >> 8) & 0xff); 426 buff[1] = (control->next_addr & 0xff); 427 428 /* EEPROM table content is stored in LE format */ 429 if (write) 430 __encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE); 431 432 /* 433 * The destination EEPROM address might need to be corrected to account 434 * for page or entire memory wrapping 435 */ 436 control->next_addr += EEPROM_TABLE_RECORD_SIZE; 437 } 438 439 ret = i2c_transfer(&control->eeprom_accessor, msgs, num); 440 if (ret < 1) { 441 DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret); 442 443 /* TODO Restore prev next EEPROM address ? */ 444 goto free_msgs; 445 } 446 447 448 if (!write) { 449 for (i = 0; i < num; i++) { 450 buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)]; 451 record = &records[i]; 452 453 __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE); 454 } 455 } 456 457 if (write) { 458 uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control); 459 460 /* 461 * Update table header with size and CRC and account for table 462 * wrap around where the assumption is that we treat it as empty 463 * table 464 * 465 * TODO - Check the assumption is correct 466 */ 467 control->num_recs += num; 468 control->num_recs %= EEPROM_MAX_RECORD_NUM; 469 control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num; 470 if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES) 471 control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE + 472 control->num_recs * EEPROM_TABLE_RECORD_SIZE; 473 474 __update_tbl_checksum(control, records, num, old_hdr_byte_sum); 475 476 __update_table_header(control, buffs); 477 } else if (!__validate_tbl_checksum(control, records, num)) { 478 DRM_WARN("EEPROM Table checksum mismatch!"); 479 /* TODO Uncomment when EEPROM read/write is relliable */ 480 /* ret = -EIO; */ 481 } 482 483 free_msgs: 484 kfree(msgs); 485 486 free_buff: 487 kfree(buffs); 488 489 mutex_unlock(&control->tbl_mutex); 490 491 return ret == num ? 0 : -EIO; 492 } 493 494 /* Used for testing if bugs encountered */ 495 #if 0 496 void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control) 497 { 498 int i; 499 struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL); 500 501 if (!recs) 502 return; 503 504 for (i = 0; i < 1 ; i++) { 505 recs[i].address = 0xdeadbeef; 506 recs[i].retired_page = i; 507 } 508 509 if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) { 510 511 memset(recs, 0, sizeof(*recs) * 1); 512 513 control->next_addr = EEPROM_RECORD_START; 514 515 if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) { 516 for (i = 0; i < 1; i++) 517 DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu", 518 recs[i].address, recs[i].retired_page); 519 } else 520 DRM_ERROR("Failed in reading from table"); 521 522 } else 523 DRM_ERROR("Failed in writing to table"); 524 } 525 #endif 526