1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #ifndef _AMDGPU_RAS_H
25 #define _AMDGPU_RAS_H
26 
27 #include <linux/debugfs.h>
28 #include <linux/list.h>
29 #include "ta_ras_if.h"
30 #include "amdgpu_ras_eeprom.h"
31 
32 struct amdgpu_iv_entry;
33 
34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS		(0x1 << 0)
35 
36 enum amdgpu_ras_block {
37 	AMDGPU_RAS_BLOCK__UMC = 0,
38 	AMDGPU_RAS_BLOCK__SDMA,
39 	AMDGPU_RAS_BLOCK__GFX,
40 	AMDGPU_RAS_BLOCK__MMHUB,
41 	AMDGPU_RAS_BLOCK__ATHUB,
42 	AMDGPU_RAS_BLOCK__PCIE_BIF,
43 	AMDGPU_RAS_BLOCK__HDP,
44 	AMDGPU_RAS_BLOCK__XGMI_WAFL,
45 	AMDGPU_RAS_BLOCK__DF,
46 	AMDGPU_RAS_BLOCK__SMN,
47 	AMDGPU_RAS_BLOCK__SEM,
48 	AMDGPU_RAS_BLOCK__MP0,
49 	AMDGPU_RAS_BLOCK__MP1,
50 	AMDGPU_RAS_BLOCK__FUSE,
51 	AMDGPU_RAS_BLOCK__MCA,
52 	AMDGPU_RAS_BLOCK__VCN,
53 	AMDGPU_RAS_BLOCK__JPEG,
54 
55 	AMDGPU_RAS_BLOCK__LAST
56 };
57 
58 enum amdgpu_ras_mca_block {
59 	AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
60 	AMDGPU_RAS_MCA_BLOCK__MP1,
61 	AMDGPU_RAS_MCA_BLOCK__MPIO,
62 	AMDGPU_RAS_MCA_BLOCK__IOHC,
63 
64 	AMDGPU_RAS_MCA_BLOCK__LAST
65 };
66 
67 #define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST
68 #define AMDGPU_RAS_MCA_BLOCK_COUNT	AMDGPU_RAS_MCA_BLOCK__LAST
69 #define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
70 
71 enum amdgpu_ras_gfx_subblock {
72 	/* CPC */
73 	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
74 	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
75 		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
76 	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
77 	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
78 	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
79 	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
80 	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
81 	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
82 	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
83 	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
84 		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
85 	/* CPF */
86 	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
87 	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
88 		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
89 	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
90 	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
91 	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
92 	/* CPG */
93 	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
94 	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
95 		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
96 	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
97 	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
98 	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
99 	/* GDS */
100 	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
101 	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
102 	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
103 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
104 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
105 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
106 	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
107 		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
108 	/* SPI */
109 	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
110 	/* SQ */
111 	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
112 	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
113 	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
114 	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
115 	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
116 	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
117 	/* SQC (3 ranges) */
118 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
119 	/* SQC range 0 */
120 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
121 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
122 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
123 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
124 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
125 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
126 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
127 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
128 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
129 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
130 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
131 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
132 	/* SQC range 1 */
133 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
134 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
135 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
136 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
137 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
138 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
139 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
140 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
141 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
142 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
143 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
144 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
145 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
146 	/* SQC range 2 */
147 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
148 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
149 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
150 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
151 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
152 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
153 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
154 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
155 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
156 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
157 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
158 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
159 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
160 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
161 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
162 	/* TA */
163 	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
164 	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
165 		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
166 	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
167 	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
168 	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
169 	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
170 	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
171 	/* TCA */
172 	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
173 	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
174 		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
175 	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
176 	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
177 		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
178 	/* TCC (5 sub-ranges) */
179 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
180 	/* TCC range 0 */
181 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
182 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
183 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
184 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
185 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
186 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
187 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
188 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
189 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
190 	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
191 	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
192 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
193 		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
194 	/* TCC range 1 */
195 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
196 	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
197 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
198 	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
199 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
200 		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
201 	/* TCC range 2 */
202 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
203 	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
204 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
205 	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
206 	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
207 	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
208 	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
209 	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
210 	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
211 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
212 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
213 		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
214 	/* TCC range 3 */
215 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
216 	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
217 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
218 	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
219 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
220 		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
221 	/* TCC range 4 */
222 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
223 	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
224 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
225 	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
226 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
227 		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
228 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
229 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
230 	/* TCI */
231 	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
232 	/* TCP */
233 	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
234 	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
235 		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
236 	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
237 	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
238 	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
239 	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
240 	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
241 	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
242 	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
243 		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
244 	/* TD */
245 	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
246 	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
247 		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
248 	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
249 	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
250 	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
251 	/* EA (3 sub-ranges) */
252 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
253 	/* EA range 0 */
254 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
255 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
256 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
257 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
258 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
259 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
260 	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
261 	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
262 	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
263 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
264 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
265 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
266 		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
267 	/* EA range 1 */
268 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
269 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
270 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
271 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
272 	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
273 	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
274 	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
275 	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
276 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
277 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
278 		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
279 	/* EA range 2 */
280 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
281 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
282 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
283 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
284 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
285 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
286 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
287 		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
288 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
289 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
290 	/* UTC VM L2 bank */
291 	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
292 	/* UTC VM walker */
293 	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
294 	/* UTC ATC L2 2MB cache */
295 	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
296 	/* UTC ATC L2 4KB cache */
297 	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
298 	AMDGPU_RAS_BLOCK__GFX_MAX
299 };
300 
301 enum amdgpu_ras_error_type {
302 	AMDGPU_RAS_ERROR__NONE							= 0,
303 	AMDGPU_RAS_ERROR__PARITY						= 1,
304 	AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE					= 2,
305 	AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE					= 4,
306 	AMDGPU_RAS_ERROR__POISON						= 8,
307 };
308 
309 enum amdgpu_ras_ret {
310 	AMDGPU_RAS_SUCCESS = 0,
311 	AMDGPU_RAS_FAIL,
312 	AMDGPU_RAS_UE,
313 	AMDGPU_RAS_CE,
314 	AMDGPU_RAS_PT,
315 };
316 
317 struct ras_common_if {
318 	enum amdgpu_ras_block block;
319 	enum amdgpu_ras_error_type type;
320 	uint32_t sub_block_index;
321 	char name[32];
322 };
323 
324 #define MAX_UMC_CHANNEL_NUM 32
325 
326 struct ecc_info_per_ch {
327 	uint16_t ce_count_lo_chip;
328 	uint16_t ce_count_hi_chip;
329 	uint64_t mca_umc_status;
330 	uint64_t mca_umc_addr;
331 	uint64_t mca_ceumc_addr;
332 };
333 
334 struct umc_ecc_info {
335 	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
336 
337 	/* Determine smu ecctable whether support
338 	 * record correctable error address
339 	 */
340 	int record_ce_addr_supported;
341 };
342 
343 struct amdgpu_ras {
344 	/* ras infrastructure */
345 	/* for ras itself. */
346 	uint32_t features;
347 	struct list_head head;
348 	/* sysfs */
349 	struct device_attribute features_attr;
350 	struct bin_attribute badpages_attr;
351 	struct dentry *de_ras_eeprom_table;
352 	/* block array */
353 	struct ras_manager *objs;
354 
355 	/* gpu recovery */
356 	struct work_struct recovery_work;
357 	atomic_t in_recovery;
358 	struct amdgpu_device *adev;
359 	/* error handler data */
360 	struct ras_err_handler_data *eh_data;
361 	struct mutex recovery_lock;
362 
363 	uint32_t flags;
364 	bool reboot;
365 	struct amdgpu_ras_eeprom_control eeprom_control;
366 
367 	bool error_query_ready;
368 
369 	/* bad page count threshold */
370 	uint32_t bad_page_cnt_threshold;
371 
372 	/* disable ras error count harvest in recovery */
373 	bool disable_ras_err_cnt_harvest;
374 
375 	/* is poison mode supported */
376 	bool poison_supported;
377 
378 	/* RAS count errors delayed work */
379 	struct delayed_work ras_counte_delay_work;
380 	atomic_t ras_ue_count;
381 	atomic_t ras_ce_count;
382 
383 	/* record umc error info queried from smu */
384 	struct umc_ecc_info umc_ecc;
385 
386 	/* Indicates smu whether need update bad channel info */
387 	bool update_channel_flag;
388 };
389 
390 struct ras_fs_data {
391 	char sysfs_name[32];
392 	char debugfs_name[32];
393 };
394 
395 struct ras_err_data {
396 	unsigned long ue_count;
397 	unsigned long ce_count;
398 	unsigned long err_addr_cnt;
399 	struct eeprom_table_record *err_addr;
400 };
401 
402 struct ras_err_handler_data {
403 	/* point to bad page records array */
404 	struct eeprom_table_record *bps;
405 	/* the count of entries */
406 	int count;
407 	/* the space can place new entries */
408 	int space_left;
409 };
410 
411 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
412 		void *err_data,
413 		struct amdgpu_iv_entry *entry);
414 
415 struct ras_ih_data {
416 	/* interrupt bottom half */
417 	struct work_struct ih_work;
418 	int inuse;
419 	/* IP callback */
420 	ras_ih_cb cb;
421 	/* full of entries */
422 	unsigned char *ring;
423 	unsigned int ring_size;
424 	unsigned int element_size;
425 	unsigned int aligned_element_size;
426 	unsigned int rptr;
427 	unsigned int wptr;
428 };
429 
430 struct ras_manager {
431 	struct ras_common_if head;
432 	/* reference count */
433 	int use;
434 	/* ras block link */
435 	struct list_head node;
436 	/* the device */
437 	struct amdgpu_device *adev;
438 	/* sysfs */
439 	struct device_attribute sysfs_attr;
440 	int attr_inuse;
441 
442 	/* fs node name */
443 	struct ras_fs_data fs_data;
444 
445 	/* IH data */
446 	struct ras_ih_data ih_data;
447 
448 	struct ras_err_data err_data;
449 };
450 
451 struct ras_badpage {
452 	unsigned int bp;
453 	unsigned int size;
454 	unsigned int flags;
455 };
456 
457 /* interfaces for IP */
458 struct ras_fs_if {
459 	struct ras_common_if head;
460 	const char* sysfs_name;
461 	char debugfs_name[32];
462 };
463 
464 struct ras_query_if {
465 	struct ras_common_if head;
466 	unsigned long ue_count;
467 	unsigned long ce_count;
468 };
469 
470 struct ras_inject_if {
471 	struct ras_common_if head;
472 	uint64_t address;
473 	uint64_t value;
474 };
475 
476 struct ras_cure_if {
477 	struct ras_common_if head;
478 	uint64_t address;
479 };
480 
481 struct ras_ih_if {
482 	struct ras_common_if head;
483 	ras_ih_cb cb;
484 };
485 
486 struct ras_dispatch_if {
487 	struct ras_common_if head;
488 	struct amdgpu_iv_entry *entry;
489 };
490 
491 struct ras_debug_if {
492 	union {
493 		struct ras_common_if head;
494 		struct ras_inject_if inject;
495 	};
496 	int op;
497 };
498 
499 struct amdgpu_ras_block_object {
500 	struct ras_common_if  ras_comm;
501 
502 	int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
503 				enum amdgpu_ras_block block, uint32_t sub_block_index);
504 	int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
505 	void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
506 	ras_ih_cb ras_cb;
507 	const struct amdgpu_ras_block_hw_ops *hw_ops;
508 };
509 
510 struct amdgpu_ras_block_hw_ops {
511 	int  (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
512 	void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
513 	void (*query_ras_error_status)(struct amdgpu_device *adev);
514 	void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
515 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
516 	void (*reset_ras_error_status)(struct amdgpu_device *adev);
517 	bool (*query_poison_status)(struct amdgpu_device *adev);
518 	bool (*handle_poison_consumption)(struct amdgpu_device *adev);
519 };
520 
521 /* work flow
522  * vbios
523  * 1: ras feature enable (enabled by default)
524  * psp
525  * 2: ras framework init (in ip_init)
526  * IP
527  * 3: IH add
528  * 4: debugfs/sysfs create
529  * 5: query/inject
530  * 6: debugfs/sysfs remove
531  * 7: IH remove
532  * 8: feature disable
533  */
534 
535 
536 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
537 
538 void amdgpu_ras_resume(struct amdgpu_device *adev);
539 void amdgpu_ras_suspend(struct amdgpu_device *adev);
540 
541 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
542 				 unsigned long *ce_count,
543 				 unsigned long *ue_count,
544 				 struct ras_query_if *query_info);
545 
546 /* error handling functions */
547 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
548 		struct eeprom_table_record *bps, int pages);
549 
550 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
551 		unsigned long *new_cnt);
552 
553 static inline enum ta_ras_block
554 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
555 	switch (block) {
556 	case AMDGPU_RAS_BLOCK__UMC:
557 		return TA_RAS_BLOCK__UMC;
558 	case AMDGPU_RAS_BLOCK__SDMA:
559 		return TA_RAS_BLOCK__SDMA;
560 	case AMDGPU_RAS_BLOCK__GFX:
561 		return TA_RAS_BLOCK__GFX;
562 	case AMDGPU_RAS_BLOCK__MMHUB:
563 		return TA_RAS_BLOCK__MMHUB;
564 	case AMDGPU_RAS_BLOCK__ATHUB:
565 		return TA_RAS_BLOCK__ATHUB;
566 	case AMDGPU_RAS_BLOCK__PCIE_BIF:
567 		return TA_RAS_BLOCK__PCIE_BIF;
568 	case AMDGPU_RAS_BLOCK__HDP:
569 		return TA_RAS_BLOCK__HDP;
570 	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
571 		return TA_RAS_BLOCK__XGMI_WAFL;
572 	case AMDGPU_RAS_BLOCK__DF:
573 		return TA_RAS_BLOCK__DF;
574 	case AMDGPU_RAS_BLOCK__SMN:
575 		return TA_RAS_BLOCK__SMN;
576 	case AMDGPU_RAS_BLOCK__SEM:
577 		return TA_RAS_BLOCK__SEM;
578 	case AMDGPU_RAS_BLOCK__MP0:
579 		return TA_RAS_BLOCK__MP0;
580 	case AMDGPU_RAS_BLOCK__MP1:
581 		return TA_RAS_BLOCK__MP1;
582 	case AMDGPU_RAS_BLOCK__FUSE:
583 		return TA_RAS_BLOCK__FUSE;
584 	case AMDGPU_RAS_BLOCK__MCA:
585 		return TA_RAS_BLOCK__MCA;
586 	case AMDGPU_RAS_BLOCK__VCN:
587 		return TA_RAS_BLOCK__VCN;
588 	case AMDGPU_RAS_BLOCK__JPEG:
589 		return TA_RAS_BLOCK__JPEG;
590 	default:
591 		WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
592 		return TA_RAS_BLOCK__UMC;
593 	}
594 }
595 
596 static inline enum ta_ras_error_type
597 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
598 	switch (error) {
599 	case AMDGPU_RAS_ERROR__NONE:
600 		return TA_RAS_ERROR__NONE;
601 	case AMDGPU_RAS_ERROR__PARITY:
602 		return TA_RAS_ERROR__PARITY;
603 	case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
604 		return TA_RAS_ERROR__SINGLE_CORRECTABLE;
605 	case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
606 		return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
607 	case AMDGPU_RAS_ERROR__POISON:
608 		return TA_RAS_ERROR__POISON;
609 	default:
610 		WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
611 		return TA_RAS_ERROR__NONE;
612 	}
613 }
614 
615 /* called in ip_init and ip_fini */
616 int amdgpu_ras_init(struct amdgpu_device *adev);
617 int amdgpu_ras_late_init(struct amdgpu_device *adev);
618 int amdgpu_ras_fini(struct amdgpu_device *adev);
619 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
620 
621 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
622 			struct ras_common_if *ras_block);
623 
624 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
625 			  struct ras_common_if *ras_block);
626 
627 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
628 		struct ras_common_if *head, bool enable);
629 
630 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
631 		struct ras_common_if *head, bool enable);
632 
633 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
634 		struct ras_common_if *head);
635 
636 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
637 		struct ras_common_if *head);
638 
639 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
640 
641 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
642 		struct ras_query_if *info);
643 
644 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
645 		enum amdgpu_ras_block block);
646 
647 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
648 		struct ras_inject_if *info);
649 
650 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
651 		struct ras_common_if *head);
652 
653 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
654 		struct ras_common_if *head);
655 
656 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
657 		struct ras_dispatch_if *info);
658 
659 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
660 		struct ras_common_if *head);
661 
662 extern atomic_t amdgpu_ras_in_intr;
663 
664 static inline bool amdgpu_ras_intr_triggered(void)
665 {
666 	return !!atomic_read(&amdgpu_ras_in_intr);
667 }
668 
669 static inline void amdgpu_ras_intr_cleared(void)
670 {
671 	atomic_set(&amdgpu_ras_in_intr, 0);
672 }
673 
674 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
675 
676 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
677 
678 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
679 
680 void amdgpu_release_ras_context(struct amdgpu_device *adev);
681 
682 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
683 
684 const char *get_ras_block_str(struct ras_common_if *ras_block);
685 
686 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
687 
688 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
689 
690 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
691 
692 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
693 
694 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
695 
696 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
697 				struct amdgpu_ras_block_object *ras_block_obj);
698 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
699 #endif
700