1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #ifndef _AMDGPU_RAS_H
25 #define _AMDGPU_RAS_H
26 
27 #include <linux/debugfs.h>
28 #include <linux/list.h>
29 #include "ta_ras_if.h"
30 #include "amdgpu_ras_eeprom.h"
31 
32 struct amdgpu_iv_entry;
33 
34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS		(0x1 << 0)
35 
36 enum amdgpu_ras_block {
37 	AMDGPU_RAS_BLOCK__UMC = 0,
38 	AMDGPU_RAS_BLOCK__SDMA,
39 	AMDGPU_RAS_BLOCK__GFX,
40 	AMDGPU_RAS_BLOCK__MMHUB,
41 	AMDGPU_RAS_BLOCK__ATHUB,
42 	AMDGPU_RAS_BLOCK__PCIE_BIF,
43 	AMDGPU_RAS_BLOCK__HDP,
44 	AMDGPU_RAS_BLOCK__XGMI_WAFL,
45 	AMDGPU_RAS_BLOCK__DF,
46 	AMDGPU_RAS_BLOCK__SMN,
47 	AMDGPU_RAS_BLOCK__SEM,
48 	AMDGPU_RAS_BLOCK__MP0,
49 	AMDGPU_RAS_BLOCK__MP1,
50 	AMDGPU_RAS_BLOCK__FUSE,
51 	AMDGPU_RAS_BLOCK__MCA,
52 	AMDGPU_RAS_BLOCK__VCN,
53 	AMDGPU_RAS_BLOCK__JPEG,
54 
55 	AMDGPU_RAS_BLOCK__LAST
56 };
57 
58 enum amdgpu_ras_mca_block {
59 	AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
60 	AMDGPU_RAS_MCA_BLOCK__MP1,
61 	AMDGPU_RAS_MCA_BLOCK__MPIO,
62 	AMDGPU_RAS_MCA_BLOCK__IOHC,
63 
64 	AMDGPU_RAS_MCA_BLOCK__LAST
65 };
66 
67 #define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST
68 #define AMDGPU_RAS_MCA_BLOCK_COUNT	AMDGPU_RAS_MCA_BLOCK__LAST
69 #define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
70 
71 enum amdgpu_ras_gfx_subblock {
72 	/* CPC */
73 	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
74 	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
75 		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
76 	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
77 	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
78 	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
79 	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
80 	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
81 	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
82 	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
83 	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
84 		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
85 	/* CPF */
86 	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
87 	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
88 		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
89 	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
90 	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
91 	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
92 	/* CPG */
93 	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
94 	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
95 		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
96 	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
97 	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
98 	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
99 	/* GDS */
100 	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
101 	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
102 	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
103 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
104 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
105 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
106 	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
107 		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
108 	/* SPI */
109 	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
110 	/* SQ */
111 	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
112 	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
113 	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
114 	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
115 	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
116 	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
117 	/* SQC (3 ranges) */
118 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
119 	/* SQC range 0 */
120 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
121 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
122 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
123 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
124 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
125 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
126 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
127 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
128 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
129 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
130 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
131 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
132 	/* SQC range 1 */
133 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
134 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
135 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
136 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
137 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
138 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
139 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
140 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
141 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
142 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
143 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
144 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
145 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
146 	/* SQC range 2 */
147 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
148 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
149 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
150 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
151 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
152 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
153 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
154 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
155 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
156 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
157 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
158 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
159 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
160 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
161 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
162 	/* TA */
163 	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
164 	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
165 		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
166 	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
167 	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
168 	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
169 	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
170 	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
171 	/* TCA */
172 	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
173 	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
174 		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
175 	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
176 	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
177 		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
178 	/* TCC (5 sub-ranges) */
179 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
180 	/* TCC range 0 */
181 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
182 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
183 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
184 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
185 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
186 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
187 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
188 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
189 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
190 	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
191 	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
192 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
193 		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
194 	/* TCC range 1 */
195 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
196 	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
197 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
198 	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
199 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
200 		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
201 	/* TCC range 2 */
202 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
203 	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
204 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
205 	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
206 	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
207 	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
208 	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
209 	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
210 	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
211 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
212 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
213 		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
214 	/* TCC range 3 */
215 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
216 	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
217 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
218 	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
219 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
220 		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
221 	/* TCC range 4 */
222 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
223 	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
224 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
225 	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
226 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
227 		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
228 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
229 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
230 	/* TCI */
231 	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
232 	/* TCP */
233 	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
234 	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
235 		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
236 	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
237 	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
238 	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
239 	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
240 	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
241 	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
242 	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
243 		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
244 	/* TD */
245 	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
246 	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
247 		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
248 	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
249 	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
250 	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
251 	/* EA (3 sub-ranges) */
252 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
253 	/* EA range 0 */
254 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
255 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
256 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
257 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
258 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
259 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
260 	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
261 	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
262 	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
263 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
264 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
265 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
266 		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
267 	/* EA range 1 */
268 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
269 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
270 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
271 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
272 	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
273 	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
274 	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
275 	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
276 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
277 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
278 		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
279 	/* EA range 2 */
280 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
281 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
282 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
283 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
284 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
285 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
286 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
287 		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
288 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
289 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
290 	/* UTC VM L2 bank */
291 	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
292 	/* UTC VM walker */
293 	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
294 	/* UTC ATC L2 2MB cache */
295 	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
296 	/* UTC ATC L2 4KB cache */
297 	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
298 	AMDGPU_RAS_BLOCK__GFX_MAX
299 };
300 
301 enum amdgpu_ras_error_type {
302 	AMDGPU_RAS_ERROR__NONE							= 0,
303 	AMDGPU_RAS_ERROR__PARITY						= 1,
304 	AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE					= 2,
305 	AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE					= 4,
306 	AMDGPU_RAS_ERROR__POISON						= 8,
307 };
308 
309 enum amdgpu_ras_ret {
310 	AMDGPU_RAS_SUCCESS = 0,
311 	AMDGPU_RAS_FAIL,
312 	AMDGPU_RAS_UE,
313 	AMDGPU_RAS_CE,
314 	AMDGPU_RAS_PT,
315 };
316 
317 /* ras error status reisger fields */
318 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT	0x0
319 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK	0x00000001L
320 #define ERR_STATUS_LO__MEMORY_ID__SHIFT			0x18
321 #define ERR_STATUS_LO__MEMORY_ID_MASK			0xFF000000L
322 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT	0x2
323 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK		0x00000004L
324 #define ERR_STATUS__ERR_CNT__SHIFT			0x17
325 #define ERR_STATUS__ERR_CNT_MASK			0x03800000L
326 
327 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
328 	ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
329 
330 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
331 	(adev->reg_offset[hwip][ip_inst][segment] + (reg))
332 
333 #define AMDGPU_RAS_ERR_INFO_VALID	(1 << 0)
334 #define AMDGPU_RAS_ERR_STATUS_VALID	(1 << 1)
335 #define AMDGPU_RAS_ERR_ADDRESS_VALID	(1 << 2)
336 
337 struct amdgpu_ras_err_status_reg_entry {
338 	uint32_t hwip;
339 	uint32_t ip_inst;
340 	uint32_t seg_lo;
341 	uint32_t reg_lo;
342 	uint32_t seg_hi;
343 	uint32_t reg_hi;
344 	uint32_t reg_inst;
345 	uint32_t flags;
346 	const char *block_name;
347 };
348 
349 struct amdgpu_ras_memory_id_entry {
350 	uint32_t memory_id;
351 	const char *name;
352 };
353 
354 struct ras_common_if {
355 	enum amdgpu_ras_block block;
356 	enum amdgpu_ras_error_type type;
357 	uint32_t sub_block_index;
358 	char name[32];
359 };
360 
361 #define MAX_UMC_CHANNEL_NUM 32
362 
363 struct ecc_info_per_ch {
364 	uint16_t ce_count_lo_chip;
365 	uint16_t ce_count_hi_chip;
366 	uint64_t mca_umc_status;
367 	uint64_t mca_umc_addr;
368 	uint64_t mca_ceumc_addr;
369 };
370 
371 struct umc_ecc_info {
372 	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
373 
374 	/* Determine smu ecctable whether support
375 	 * record correctable error address
376 	 */
377 	int record_ce_addr_supported;
378 };
379 
380 struct amdgpu_ras {
381 	/* ras infrastructure */
382 	/* for ras itself. */
383 	uint32_t features;
384 	struct list_head head;
385 	/* sysfs */
386 	struct device_attribute features_attr;
387 	struct bin_attribute badpages_attr;
388 	struct dentry *de_ras_eeprom_table;
389 	/* block array */
390 	struct ras_manager *objs;
391 
392 	/* gpu recovery */
393 	struct work_struct recovery_work;
394 	atomic_t in_recovery;
395 	struct amdgpu_device *adev;
396 	/* error handler data */
397 	struct ras_err_handler_data *eh_data;
398 	struct mutex recovery_lock;
399 
400 	uint32_t flags;
401 	bool reboot;
402 	struct amdgpu_ras_eeprom_control eeprom_control;
403 
404 	bool error_query_ready;
405 
406 	/* bad page count threshold */
407 	uint32_t bad_page_cnt_threshold;
408 
409 	/* disable ras error count harvest in recovery */
410 	bool disable_ras_err_cnt_harvest;
411 
412 	/* is poison mode supported */
413 	bool poison_supported;
414 
415 	/* RAS count errors delayed work */
416 	struct delayed_work ras_counte_delay_work;
417 	atomic_t ras_ue_count;
418 	atomic_t ras_ce_count;
419 
420 	/* record umc error info queried from smu */
421 	struct umc_ecc_info umc_ecc;
422 
423 	/* Indicates smu whether need update bad channel info */
424 	bool update_channel_flag;
425 };
426 
427 struct ras_fs_data {
428 	char sysfs_name[32];
429 	char debugfs_name[32];
430 };
431 
432 struct ras_err_data {
433 	unsigned long ue_count;
434 	unsigned long ce_count;
435 	unsigned long err_addr_cnt;
436 	struct eeprom_table_record *err_addr;
437 };
438 
439 struct ras_err_handler_data {
440 	/* point to bad page records array */
441 	struct eeprom_table_record *bps;
442 	/* the count of entries */
443 	int count;
444 	/* the space can place new entries */
445 	int space_left;
446 };
447 
448 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
449 		void *err_data,
450 		struct amdgpu_iv_entry *entry);
451 
452 struct ras_ih_data {
453 	/* interrupt bottom half */
454 	struct work_struct ih_work;
455 	int inuse;
456 	/* IP callback */
457 	ras_ih_cb cb;
458 	/* full of entries */
459 	unsigned char *ring;
460 	unsigned int ring_size;
461 	unsigned int element_size;
462 	unsigned int aligned_element_size;
463 	unsigned int rptr;
464 	unsigned int wptr;
465 };
466 
467 struct ras_manager {
468 	struct ras_common_if head;
469 	/* reference count */
470 	int use;
471 	/* ras block link */
472 	struct list_head node;
473 	/* the device */
474 	struct amdgpu_device *adev;
475 	/* sysfs */
476 	struct device_attribute sysfs_attr;
477 	int attr_inuse;
478 
479 	/* fs node name */
480 	struct ras_fs_data fs_data;
481 
482 	/* IH data */
483 	struct ras_ih_data ih_data;
484 
485 	struct ras_err_data err_data;
486 };
487 
488 struct ras_badpage {
489 	unsigned int bp;
490 	unsigned int size;
491 	unsigned int flags;
492 };
493 
494 /* interfaces for IP */
495 struct ras_fs_if {
496 	struct ras_common_if head;
497 	const char* sysfs_name;
498 	char debugfs_name[32];
499 };
500 
501 struct ras_query_if {
502 	struct ras_common_if head;
503 	unsigned long ue_count;
504 	unsigned long ce_count;
505 };
506 
507 struct ras_inject_if {
508 	struct ras_common_if head;
509 	uint64_t address;
510 	uint64_t value;
511 };
512 
513 struct ras_cure_if {
514 	struct ras_common_if head;
515 	uint64_t address;
516 };
517 
518 struct ras_ih_if {
519 	struct ras_common_if head;
520 	ras_ih_cb cb;
521 };
522 
523 struct ras_dispatch_if {
524 	struct ras_common_if head;
525 	struct amdgpu_iv_entry *entry;
526 };
527 
528 struct ras_debug_if {
529 	union {
530 		struct ras_common_if head;
531 		struct ras_inject_if inject;
532 	};
533 	int op;
534 };
535 
536 struct amdgpu_ras_block_object {
537 	struct ras_common_if  ras_comm;
538 
539 	int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
540 				enum amdgpu_ras_block block, uint32_t sub_block_index);
541 	int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
542 	void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
543 	ras_ih_cb ras_cb;
544 	const struct amdgpu_ras_block_hw_ops *hw_ops;
545 };
546 
547 struct amdgpu_ras_block_hw_ops {
548 	int  (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
549 	void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
550 	void (*query_ras_error_status)(struct amdgpu_device *adev);
551 	void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
552 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
553 	void (*reset_ras_error_status)(struct amdgpu_device *adev);
554 	bool (*query_poison_status)(struct amdgpu_device *adev);
555 	bool (*handle_poison_consumption)(struct amdgpu_device *adev);
556 };
557 
558 /* work flow
559  * vbios
560  * 1: ras feature enable (enabled by default)
561  * psp
562  * 2: ras framework init (in ip_init)
563  * IP
564  * 3: IH add
565  * 4: debugfs/sysfs create
566  * 5: query/inject
567  * 6: debugfs/sysfs remove
568  * 7: IH remove
569  * 8: feature disable
570  */
571 
572 
573 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
574 
575 void amdgpu_ras_resume(struct amdgpu_device *adev);
576 void amdgpu_ras_suspend(struct amdgpu_device *adev);
577 
578 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
579 				 unsigned long *ce_count,
580 				 unsigned long *ue_count,
581 				 struct ras_query_if *query_info);
582 
583 /* error handling functions */
584 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
585 		struct eeprom_table_record *bps, int pages);
586 
587 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
588 		unsigned long *new_cnt);
589 
590 static inline enum ta_ras_block
591 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
592 	switch (block) {
593 	case AMDGPU_RAS_BLOCK__UMC:
594 		return TA_RAS_BLOCK__UMC;
595 	case AMDGPU_RAS_BLOCK__SDMA:
596 		return TA_RAS_BLOCK__SDMA;
597 	case AMDGPU_RAS_BLOCK__GFX:
598 		return TA_RAS_BLOCK__GFX;
599 	case AMDGPU_RAS_BLOCK__MMHUB:
600 		return TA_RAS_BLOCK__MMHUB;
601 	case AMDGPU_RAS_BLOCK__ATHUB:
602 		return TA_RAS_BLOCK__ATHUB;
603 	case AMDGPU_RAS_BLOCK__PCIE_BIF:
604 		return TA_RAS_BLOCK__PCIE_BIF;
605 	case AMDGPU_RAS_BLOCK__HDP:
606 		return TA_RAS_BLOCK__HDP;
607 	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
608 		return TA_RAS_BLOCK__XGMI_WAFL;
609 	case AMDGPU_RAS_BLOCK__DF:
610 		return TA_RAS_BLOCK__DF;
611 	case AMDGPU_RAS_BLOCK__SMN:
612 		return TA_RAS_BLOCK__SMN;
613 	case AMDGPU_RAS_BLOCK__SEM:
614 		return TA_RAS_BLOCK__SEM;
615 	case AMDGPU_RAS_BLOCK__MP0:
616 		return TA_RAS_BLOCK__MP0;
617 	case AMDGPU_RAS_BLOCK__MP1:
618 		return TA_RAS_BLOCK__MP1;
619 	case AMDGPU_RAS_BLOCK__FUSE:
620 		return TA_RAS_BLOCK__FUSE;
621 	case AMDGPU_RAS_BLOCK__MCA:
622 		return TA_RAS_BLOCK__MCA;
623 	case AMDGPU_RAS_BLOCK__VCN:
624 		return TA_RAS_BLOCK__VCN;
625 	case AMDGPU_RAS_BLOCK__JPEG:
626 		return TA_RAS_BLOCK__JPEG;
627 	default:
628 		WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
629 		return TA_RAS_BLOCK__UMC;
630 	}
631 }
632 
633 static inline enum ta_ras_error_type
634 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
635 	switch (error) {
636 	case AMDGPU_RAS_ERROR__NONE:
637 		return TA_RAS_ERROR__NONE;
638 	case AMDGPU_RAS_ERROR__PARITY:
639 		return TA_RAS_ERROR__PARITY;
640 	case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
641 		return TA_RAS_ERROR__SINGLE_CORRECTABLE;
642 	case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
643 		return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
644 	case AMDGPU_RAS_ERROR__POISON:
645 		return TA_RAS_ERROR__POISON;
646 	default:
647 		WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
648 		return TA_RAS_ERROR__NONE;
649 	}
650 }
651 
652 /* called in ip_init and ip_fini */
653 int amdgpu_ras_init(struct amdgpu_device *adev);
654 int amdgpu_ras_late_init(struct amdgpu_device *adev);
655 int amdgpu_ras_fini(struct amdgpu_device *adev);
656 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
657 
658 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
659 			struct ras_common_if *ras_block);
660 
661 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
662 			  struct ras_common_if *ras_block);
663 
664 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
665 		struct ras_common_if *head, bool enable);
666 
667 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
668 		struct ras_common_if *head, bool enable);
669 
670 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
671 		struct ras_common_if *head);
672 
673 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
674 		struct ras_common_if *head);
675 
676 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
677 
678 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
679 		struct ras_query_if *info);
680 
681 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
682 		enum amdgpu_ras_block block);
683 
684 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
685 		struct ras_inject_if *info);
686 
687 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
688 		struct ras_common_if *head);
689 
690 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
691 		struct ras_common_if *head);
692 
693 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
694 		struct ras_dispatch_if *info);
695 
696 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
697 		struct ras_common_if *head);
698 
699 extern atomic_t amdgpu_ras_in_intr;
700 
701 static inline bool amdgpu_ras_intr_triggered(void)
702 {
703 	return !!atomic_read(&amdgpu_ras_in_intr);
704 }
705 
706 static inline void amdgpu_ras_intr_cleared(void)
707 {
708 	atomic_set(&amdgpu_ras_in_intr, 0);
709 }
710 
711 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
712 
713 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
714 
715 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
716 
717 void amdgpu_release_ras_context(struct amdgpu_device *adev);
718 
719 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
720 
721 const char *get_ras_block_str(struct ras_common_if *ras_block);
722 
723 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
724 
725 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
726 
727 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
728 
729 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
730 
731 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
732 
733 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
734 				struct amdgpu_ras_block_object *ras_block_obj);
735 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
736 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
737 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
738 					 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
739 					 uint32_t instance,
740 					 uint32_t *memory_id);
741 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
742 				       const struct amdgpu_ras_err_status_reg_entry *reg_entry,
743 				       uint32_t instance,
744 				       unsigned long *err_cnt);
745 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
746 					   const struct amdgpu_ras_err_status_reg_entry *reg_list,
747 					   uint32_t reg_list_size,
748 					   const struct amdgpu_ras_memory_id_entry *mem_list,
749 					   uint32_t mem_list_size,
750 					   uint32_t instance,
751 					   uint32_t err_type,
752 					   unsigned long *err_count);
753 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
754 					   const struct amdgpu_ras_err_status_reg_entry *reg_list,
755 					   uint32_t reg_list_size,
756 					   uint32_t instance);
757 #endif
758