1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "ta_ras_if.h" 32 #include "amdgpu_ras_eeprom.h" 33 34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 35 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET (0x1 << 1) 36 37 enum amdgpu_ras_block { 38 AMDGPU_RAS_BLOCK__UMC = 0, 39 AMDGPU_RAS_BLOCK__SDMA, 40 AMDGPU_RAS_BLOCK__GFX, 41 AMDGPU_RAS_BLOCK__MMHUB, 42 AMDGPU_RAS_BLOCK__ATHUB, 43 AMDGPU_RAS_BLOCK__PCIE_BIF, 44 AMDGPU_RAS_BLOCK__HDP, 45 AMDGPU_RAS_BLOCK__XGMI_WAFL, 46 AMDGPU_RAS_BLOCK__DF, 47 AMDGPU_RAS_BLOCK__SMN, 48 AMDGPU_RAS_BLOCK__SEM, 49 AMDGPU_RAS_BLOCK__MP0, 50 AMDGPU_RAS_BLOCK__MP1, 51 AMDGPU_RAS_BLOCK__FUSE, 52 AMDGPU_RAS_BLOCK__MPIO, 53 54 AMDGPU_RAS_BLOCK__LAST 55 }; 56 57 extern const char *ras_block_string[]; 58 59 #define ras_block_str(i) (ras_block_string[i]) 60 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 61 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 62 63 enum amdgpu_ras_gfx_subblock { 64 /* CPC */ 65 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 66 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 67 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 68 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 69 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 70 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 71 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 72 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 73 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 74 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 75 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 76 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 77 /* CPF */ 78 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 79 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 80 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 81 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 82 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 83 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 84 /* CPG */ 85 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 86 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 87 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 88 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 89 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 90 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 91 /* GDS */ 92 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 93 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 94 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 95 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 96 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 97 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 98 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 99 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 100 /* SPI */ 101 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 102 /* SQ */ 103 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 104 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 105 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 106 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 107 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 108 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 109 /* SQC (3 ranges) */ 110 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 111 /* SQC range 0 */ 112 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 113 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 114 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 115 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 116 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 117 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 118 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 119 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 120 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 121 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 122 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 123 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 124 /* SQC range 1 */ 125 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 126 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 127 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 128 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 129 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 130 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 131 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 132 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 133 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 134 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 135 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 136 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 137 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 138 /* SQC range 2 */ 139 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 140 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 141 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 142 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 143 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 144 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 145 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 146 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 147 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 148 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 149 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 150 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 151 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 152 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 153 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 154 /* TA */ 155 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 156 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 157 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 158 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 159 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 160 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 161 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 162 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 163 /* TCA */ 164 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 165 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 166 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 167 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 168 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 169 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 170 /* TCC (5 sub-ranges) */ 171 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 172 /* TCC range 0 */ 173 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 174 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 175 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 176 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 177 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 178 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 179 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 180 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 181 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 182 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 183 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 184 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 185 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 186 /* TCC range 1 */ 187 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 188 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 189 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 190 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 191 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 192 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 193 /* TCC range 2 */ 194 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 195 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 196 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 197 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 198 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 199 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 200 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 201 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 202 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 203 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 204 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 205 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 206 /* TCC range 3 */ 207 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 208 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 209 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 210 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 211 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 212 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 213 /* TCC range 4 */ 214 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 215 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 216 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 217 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 218 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 219 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 220 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 221 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 222 /* TCI */ 223 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 224 /* TCP */ 225 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 226 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 227 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 228 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 229 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 230 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 231 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 232 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 233 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 234 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 235 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 236 /* TD */ 237 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 238 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 239 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 240 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 241 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 242 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 243 /* EA (3 sub-ranges) */ 244 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 245 /* EA range 0 */ 246 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 247 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 248 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 249 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 250 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 251 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 252 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 253 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 254 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 255 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 256 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 257 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 258 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 259 /* EA range 1 */ 260 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 261 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 262 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 263 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 264 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 265 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 266 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 267 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 268 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 269 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 270 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 271 /* EA range 2 */ 272 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 273 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 274 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 275 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 276 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 277 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 278 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 279 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 280 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 281 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 282 /* UTC VM L2 bank */ 283 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 284 /* UTC VM walker */ 285 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 286 /* UTC ATC L2 2MB cache */ 287 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 288 /* UTC ATC L2 4KB cache */ 289 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 290 AMDGPU_RAS_BLOCK__GFX_MAX 291 }; 292 293 enum amdgpu_ras_error_type { 294 AMDGPU_RAS_ERROR__NONE = 0, 295 AMDGPU_RAS_ERROR__PARITY = 1, 296 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 297 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 298 AMDGPU_RAS_ERROR__POISON = 8, 299 }; 300 301 enum amdgpu_ras_ret { 302 AMDGPU_RAS_SUCCESS = 0, 303 AMDGPU_RAS_FAIL, 304 AMDGPU_RAS_UE, 305 AMDGPU_RAS_CE, 306 AMDGPU_RAS_PT, 307 }; 308 309 struct ras_common_if { 310 enum amdgpu_ras_block block; 311 enum amdgpu_ras_error_type type; 312 uint32_t sub_block_index; 313 char name[32]; 314 }; 315 316 struct amdgpu_ras { 317 /* ras infrastructure */ 318 /* for ras itself. */ 319 uint32_t features; 320 struct list_head head; 321 /* sysfs */ 322 struct device_attribute features_attr; 323 struct bin_attribute badpages_attr; 324 struct dentry *de_ras_eeprom_table; 325 /* block array */ 326 struct ras_manager *objs; 327 328 /* gpu recovery */ 329 struct work_struct recovery_work; 330 atomic_t in_recovery; 331 struct amdgpu_device *adev; 332 /* error handler data */ 333 struct ras_err_handler_data *eh_data; 334 struct mutex recovery_lock; 335 336 uint32_t flags; 337 bool reboot; 338 struct amdgpu_ras_eeprom_control eeprom_control; 339 340 bool error_query_ready; 341 342 /* bad page count threshold */ 343 uint32_t bad_page_cnt_threshold; 344 345 /* disable ras error count harvest in recovery */ 346 bool disable_ras_err_cnt_harvest; 347 348 /* RAS count errors delayed work */ 349 struct delayed_work ras_counte_delay_work; 350 atomic_t ras_ue_count; 351 atomic_t ras_ce_count; 352 }; 353 354 struct ras_fs_data { 355 char sysfs_name[32]; 356 char debugfs_name[32]; 357 }; 358 359 struct ras_err_data { 360 unsigned long ue_count; 361 unsigned long ce_count; 362 unsigned long err_addr_cnt; 363 struct eeprom_table_record *err_addr; 364 }; 365 366 struct ras_err_handler_data { 367 /* point to bad page records array */ 368 struct eeprom_table_record *bps; 369 /* the count of entries */ 370 int count; 371 /* the space can place new entries */ 372 int space_left; 373 }; 374 375 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 376 void *err_data, 377 struct amdgpu_iv_entry *entry); 378 379 struct ras_ih_data { 380 /* interrupt bottom half */ 381 struct work_struct ih_work; 382 int inuse; 383 /* IP callback */ 384 ras_ih_cb cb; 385 /* full of entries */ 386 unsigned char *ring; 387 unsigned int ring_size; 388 unsigned int element_size; 389 unsigned int aligned_element_size; 390 unsigned int rptr; 391 unsigned int wptr; 392 }; 393 394 struct ras_manager { 395 struct ras_common_if head; 396 /* reference count */ 397 int use; 398 /* ras block link */ 399 struct list_head node; 400 /* the device */ 401 struct amdgpu_device *adev; 402 /* sysfs */ 403 struct device_attribute sysfs_attr; 404 int attr_inuse; 405 406 /* fs node name */ 407 struct ras_fs_data fs_data; 408 409 /* IH data */ 410 struct ras_ih_data ih_data; 411 412 struct ras_err_data err_data; 413 }; 414 415 struct ras_badpage { 416 unsigned int bp; 417 unsigned int size; 418 unsigned int flags; 419 }; 420 421 /* interfaces for IP */ 422 struct ras_fs_if { 423 struct ras_common_if head; 424 const char* sysfs_name; 425 char debugfs_name[32]; 426 }; 427 428 struct ras_query_if { 429 struct ras_common_if head; 430 unsigned long ue_count; 431 unsigned long ce_count; 432 }; 433 434 struct ras_inject_if { 435 struct ras_common_if head; 436 uint64_t address; 437 uint64_t value; 438 }; 439 440 struct ras_cure_if { 441 struct ras_common_if head; 442 uint64_t address; 443 }; 444 445 struct ras_ih_if { 446 struct ras_common_if head; 447 ras_ih_cb cb; 448 }; 449 450 struct ras_dispatch_if { 451 struct ras_common_if head; 452 struct amdgpu_iv_entry *entry; 453 }; 454 455 struct ras_debug_if { 456 union { 457 struct ras_common_if head; 458 struct ras_inject_if inject; 459 }; 460 int op; 461 }; 462 /* work flow 463 * vbios 464 * 1: ras feature enable (enabled by default) 465 * psp 466 * 2: ras framework init (in ip_init) 467 * IP 468 * 3: IH add 469 * 4: debugfs/sysfs create 470 * 5: query/inject 471 * 6: debugfs/sysfs remove 472 * 7: IH remove 473 * 8: feature disable 474 */ 475 476 #define amdgpu_ras_get_context(adev) ((adev)->psp.ras_context.ras) 477 #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras_context.ras = (ras_con)) 478 479 /* check if ras is supported on block, say, sdma, gfx */ 480 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev, 481 unsigned int block) 482 { 483 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 484 485 if (block >= AMDGPU_RAS_BLOCK_COUNT) 486 return 0; 487 return ras && (adev->ras_enabled & (1 << block)); 488 } 489 490 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 491 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, 492 unsigned int block); 493 494 void amdgpu_ras_resume(struct amdgpu_device *adev); 495 void amdgpu_ras_suspend(struct amdgpu_device *adev); 496 497 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 498 unsigned long *ce_count, 499 unsigned long *ue_count); 500 501 /* error handling functions */ 502 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 503 struct eeprom_table_record *bps, int pages); 504 505 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev); 506 507 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) 508 { 509 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 510 511 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) 512 schedule_work(&ras->recovery_work); 513 return 0; 514 } 515 516 static inline enum ta_ras_block 517 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 518 switch (block) { 519 case AMDGPU_RAS_BLOCK__UMC: 520 return TA_RAS_BLOCK__UMC; 521 case AMDGPU_RAS_BLOCK__SDMA: 522 return TA_RAS_BLOCK__SDMA; 523 case AMDGPU_RAS_BLOCK__GFX: 524 return TA_RAS_BLOCK__GFX; 525 case AMDGPU_RAS_BLOCK__MMHUB: 526 return TA_RAS_BLOCK__MMHUB; 527 case AMDGPU_RAS_BLOCK__ATHUB: 528 return TA_RAS_BLOCK__ATHUB; 529 case AMDGPU_RAS_BLOCK__PCIE_BIF: 530 return TA_RAS_BLOCK__PCIE_BIF; 531 case AMDGPU_RAS_BLOCK__HDP: 532 return TA_RAS_BLOCK__HDP; 533 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 534 return TA_RAS_BLOCK__XGMI_WAFL; 535 case AMDGPU_RAS_BLOCK__DF: 536 return TA_RAS_BLOCK__DF; 537 case AMDGPU_RAS_BLOCK__SMN: 538 return TA_RAS_BLOCK__SMN; 539 case AMDGPU_RAS_BLOCK__SEM: 540 return TA_RAS_BLOCK__SEM; 541 case AMDGPU_RAS_BLOCK__MP0: 542 return TA_RAS_BLOCK__MP0; 543 case AMDGPU_RAS_BLOCK__MP1: 544 return TA_RAS_BLOCK__MP1; 545 case AMDGPU_RAS_BLOCK__FUSE: 546 return TA_RAS_BLOCK__FUSE; 547 default: 548 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 549 return TA_RAS_BLOCK__UMC; 550 } 551 } 552 553 static inline enum ta_ras_error_type 554 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 555 switch (error) { 556 case AMDGPU_RAS_ERROR__NONE: 557 return TA_RAS_ERROR__NONE; 558 case AMDGPU_RAS_ERROR__PARITY: 559 return TA_RAS_ERROR__PARITY; 560 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 561 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 562 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 563 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 564 case AMDGPU_RAS_ERROR__POISON: 565 return TA_RAS_ERROR__POISON; 566 default: 567 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 568 return TA_RAS_ERROR__NONE; 569 } 570 } 571 572 /* called in ip_init and ip_fini */ 573 int amdgpu_ras_init(struct amdgpu_device *adev); 574 int amdgpu_ras_fini(struct amdgpu_device *adev); 575 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 576 int amdgpu_ras_late_init(struct amdgpu_device *adev, 577 struct ras_common_if *ras_block, 578 struct ras_fs_if *fs_info, 579 struct ras_ih_if *ih_info); 580 void amdgpu_ras_late_fini(struct amdgpu_device *adev, 581 struct ras_common_if *ras_block, 582 struct ras_ih_if *ih_info); 583 584 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 585 struct ras_common_if *head, bool enable); 586 587 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 588 struct ras_common_if *head, bool enable); 589 590 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 591 struct ras_fs_if *head); 592 593 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 594 struct ras_common_if *head); 595 596 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 597 598 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 599 struct ras_query_if *info); 600 601 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 602 enum amdgpu_ras_block block); 603 604 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 605 struct ras_inject_if *info); 606 607 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 608 struct ras_ih_if *info); 609 610 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 611 struct ras_ih_if *info); 612 613 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 614 struct ras_dispatch_if *info); 615 616 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 617 struct ras_common_if *head); 618 619 extern atomic_t amdgpu_ras_in_intr; 620 621 static inline bool amdgpu_ras_intr_triggered(void) 622 { 623 return !!atomic_read(&amdgpu_ras_in_intr); 624 } 625 626 static inline void amdgpu_ras_intr_cleared(void) 627 { 628 atomic_set(&amdgpu_ras_in_intr, 0); 629 } 630 631 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 632 633 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 634 635 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 636 637 void amdgpu_release_ras_context(struct amdgpu_device *adev); 638 639 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 640 641 #endif 642