1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "ta_ras_if.h" 32 33 enum amdgpu_ras_block { 34 AMDGPU_RAS_BLOCK__UMC = 0, 35 AMDGPU_RAS_BLOCK__SDMA, 36 AMDGPU_RAS_BLOCK__GFX, 37 AMDGPU_RAS_BLOCK__MMHUB, 38 AMDGPU_RAS_BLOCK__ATHUB, 39 AMDGPU_RAS_BLOCK__PCIE_BIF, 40 AMDGPU_RAS_BLOCK__HDP, 41 AMDGPU_RAS_BLOCK__XGMI_WAFL, 42 AMDGPU_RAS_BLOCK__DF, 43 AMDGPU_RAS_BLOCK__SMN, 44 AMDGPU_RAS_BLOCK__SEM, 45 AMDGPU_RAS_BLOCK__MP0, 46 AMDGPU_RAS_BLOCK__MP1, 47 AMDGPU_RAS_BLOCK__FUSE, 48 49 AMDGPU_RAS_BLOCK__LAST 50 }; 51 52 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 53 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 54 55 enum amdgpu_ras_error_type { 56 AMDGPU_RAS_ERROR__NONE = 0, 57 AMDGPU_RAS_ERROR__PARITY = 1, 58 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 59 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 60 AMDGPU_RAS_ERROR__POISON = 8, 61 }; 62 63 enum amdgpu_ras_ret { 64 AMDGPU_RAS_SUCCESS = 0, 65 AMDGPU_RAS_FAIL, 66 AMDGPU_RAS_UE, 67 AMDGPU_RAS_CE, 68 AMDGPU_RAS_PT, 69 }; 70 71 struct ras_common_if { 72 enum amdgpu_ras_block block; 73 enum amdgpu_ras_error_type type; 74 uint32_t sub_block_index; 75 /* block name */ 76 char name[32]; 77 }; 78 79 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 80 struct amdgpu_iv_entry *entry); 81 82 struct amdgpu_ras { 83 /* ras infrastructure */ 84 /* for ras itself. */ 85 uint32_t hw_supported; 86 /* for IP to check its ras ability. */ 87 uint32_t supported; 88 uint32_t features; 89 struct list_head head; 90 /* debugfs */ 91 struct dentry *dir; 92 /* debugfs ctrl */ 93 struct dentry *ent; 94 /* sysfs */ 95 struct device_attribute features_attr; 96 /* block array */ 97 struct ras_manager *objs; 98 99 /* gpu recovery */ 100 struct work_struct recovery_work; 101 atomic_t in_recovery; 102 struct amdgpu_device *adev; 103 /* error handler data */ 104 struct ras_err_handler_data *eh_data; 105 struct mutex recovery_lock; 106 107 uint32_t flags; 108 }; 109 110 /* interfaces for IP */ 111 112 struct ras_fs_if { 113 struct ras_common_if head; 114 char sysfs_name[32]; 115 char debugfs_name[32]; 116 }; 117 118 struct ras_query_if { 119 struct ras_common_if head; 120 unsigned long ue_count; 121 unsigned long ce_count; 122 }; 123 124 struct ras_inject_if { 125 struct ras_common_if head; 126 uint64_t address; 127 uint64_t value; 128 }; 129 130 struct ras_cure_if { 131 struct ras_common_if head; 132 uint64_t address; 133 }; 134 135 struct ras_ih_if { 136 struct ras_common_if head; 137 ras_ih_cb cb; 138 }; 139 140 struct ras_dispatch_if { 141 struct ras_common_if head; 142 struct amdgpu_iv_entry *entry; 143 }; 144 145 struct ras_debug_if { 146 union { 147 struct ras_common_if head; 148 struct ras_inject_if inject; 149 }; 150 int op; 151 }; 152 /* work flow 153 * vbios 154 * 1: ras feature enable (enabled by default) 155 * psp 156 * 2: ras framework init (in ip_init) 157 * IP 158 * 3: IH add 159 * 4: debugfs/sysfs create 160 * 5: query/inject 161 * 6: debugfs/sysfs remove 162 * 7: IH remove 163 * 8: feature disable 164 */ 165 166 #define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras) 167 #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras.ras = (ras_con)) 168 169 /* check if ras is supported on block, say, sdma, gfx */ 170 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev, 171 unsigned int block) 172 { 173 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 174 175 return ras && (ras->supported & (1 << block)); 176 } 177 178 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 179 bool is_ce); 180 181 /* error handling functions */ 182 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 183 unsigned long *bps, int pages); 184 185 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev); 186 187 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev, 188 bool is_baco) 189 { 190 /* remove me when gpu reset works on vega20 A1. */ 191 #if 0 192 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 193 194 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) 195 schedule_work(&ras->recovery_work); 196 #endif 197 return 0; 198 } 199 200 static inline enum ta_ras_block 201 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 202 switch (block) { 203 case AMDGPU_RAS_BLOCK__UMC: 204 return TA_RAS_BLOCK__UMC; 205 case AMDGPU_RAS_BLOCK__SDMA: 206 return TA_RAS_BLOCK__SDMA; 207 case AMDGPU_RAS_BLOCK__GFX: 208 return TA_RAS_BLOCK__GFX; 209 case AMDGPU_RAS_BLOCK__MMHUB: 210 return TA_RAS_BLOCK__MMHUB; 211 case AMDGPU_RAS_BLOCK__ATHUB: 212 return TA_RAS_BLOCK__ATHUB; 213 case AMDGPU_RAS_BLOCK__PCIE_BIF: 214 return TA_RAS_BLOCK__PCIE_BIF; 215 case AMDGPU_RAS_BLOCK__HDP: 216 return TA_RAS_BLOCK__HDP; 217 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 218 return TA_RAS_BLOCK__XGMI_WAFL; 219 case AMDGPU_RAS_BLOCK__DF: 220 return TA_RAS_BLOCK__DF; 221 case AMDGPU_RAS_BLOCK__SMN: 222 return TA_RAS_BLOCK__SMN; 223 case AMDGPU_RAS_BLOCK__SEM: 224 return TA_RAS_BLOCK__SEM; 225 case AMDGPU_RAS_BLOCK__MP0: 226 return TA_RAS_BLOCK__MP0; 227 case AMDGPU_RAS_BLOCK__MP1: 228 return TA_RAS_BLOCK__MP1; 229 case AMDGPU_RAS_BLOCK__FUSE: 230 return TA_RAS_BLOCK__FUSE; 231 default: 232 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 233 return TA_RAS_BLOCK__UMC; 234 } 235 } 236 237 static inline enum ta_ras_error_type 238 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 239 switch (error) { 240 case AMDGPU_RAS_ERROR__NONE: 241 return TA_RAS_ERROR__NONE; 242 case AMDGPU_RAS_ERROR__PARITY: 243 return TA_RAS_ERROR__PARITY; 244 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 245 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 246 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 247 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 248 case AMDGPU_RAS_ERROR__POISON: 249 return TA_RAS_ERROR__POISON; 250 default: 251 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 252 return TA_RAS_ERROR__NONE; 253 } 254 } 255 256 /* called in ip_init and ip_fini */ 257 int amdgpu_ras_init(struct amdgpu_device *adev); 258 void amdgpu_ras_post_init(struct amdgpu_device *adev); 259 int amdgpu_ras_fini(struct amdgpu_device *adev); 260 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 261 262 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 263 struct ras_common_if *head, bool enable); 264 265 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 266 struct ras_common_if *head, bool enable); 267 268 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 269 struct ras_fs_if *head); 270 271 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 272 struct ras_common_if *head); 273 274 int amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 275 struct ras_fs_if *head); 276 277 int amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 278 struct ras_common_if *head); 279 280 int amdgpu_ras_error_query(struct amdgpu_device *adev, 281 struct ras_query_if *info); 282 283 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 284 struct ras_inject_if *info); 285 286 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 287 struct ras_ih_if *info); 288 289 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 290 struct ras_ih_if *info); 291 292 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 293 struct ras_dispatch_if *info); 294 #endif 295