1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "ta_ras_if.h" 32 #include "amdgpu_ras_eeprom.h" 33 34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 35 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET (0x1 << 1) 36 37 enum amdgpu_ras_block { 38 AMDGPU_RAS_BLOCK__UMC = 0, 39 AMDGPU_RAS_BLOCK__SDMA, 40 AMDGPU_RAS_BLOCK__GFX, 41 AMDGPU_RAS_BLOCK__MMHUB, 42 AMDGPU_RAS_BLOCK__ATHUB, 43 AMDGPU_RAS_BLOCK__PCIE_BIF, 44 AMDGPU_RAS_BLOCK__HDP, 45 AMDGPU_RAS_BLOCK__XGMI_WAFL, 46 AMDGPU_RAS_BLOCK__DF, 47 AMDGPU_RAS_BLOCK__SMN, 48 AMDGPU_RAS_BLOCK__SEM, 49 AMDGPU_RAS_BLOCK__MP0, 50 AMDGPU_RAS_BLOCK__MP1, 51 AMDGPU_RAS_BLOCK__FUSE, 52 53 AMDGPU_RAS_BLOCK__LAST 54 }; 55 56 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 57 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 58 59 enum amdgpu_ras_gfx_subblock { 60 /* CPC */ 61 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 62 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 63 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 64 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 65 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 66 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 67 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 68 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 69 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 70 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 71 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 72 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 73 /* CPF */ 74 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 75 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 76 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 77 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 78 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 79 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 80 /* CPG */ 81 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 82 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 83 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 84 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 85 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 86 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 87 /* GDS */ 88 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 89 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 90 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 91 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 92 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 93 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 94 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 95 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 96 /* SPI */ 97 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 98 /* SQ */ 99 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 100 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 101 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 102 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 103 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 104 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 105 /* SQC (3 ranges) */ 106 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 107 /* SQC range 0 */ 108 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 109 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 110 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 111 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 112 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 113 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 114 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 115 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 116 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 117 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 118 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 119 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 120 /* SQC range 1 */ 121 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 122 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 123 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 124 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 125 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 126 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 127 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 128 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 129 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 130 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 131 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 132 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 133 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 134 /* SQC range 2 */ 135 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 136 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 137 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 138 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 139 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 140 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 141 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 142 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 143 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 144 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 145 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 146 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 147 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 148 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 149 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 150 /* TA */ 151 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 152 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 153 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 154 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 155 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 156 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 157 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 158 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 159 /* TCA */ 160 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 161 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 162 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 163 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 164 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 165 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 166 /* TCC (5 sub-ranges) */ 167 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 168 /* TCC range 0 */ 169 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 170 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 171 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 172 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 173 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 174 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 175 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 176 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 177 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 178 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 179 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 180 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 181 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 182 /* TCC range 1 */ 183 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 184 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 185 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 186 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 187 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 188 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 189 /* TCC range 2 */ 190 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 191 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 192 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 193 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 194 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 195 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 196 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 197 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 198 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 199 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 200 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 201 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 202 /* TCC range 3 */ 203 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 204 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 205 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 206 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 207 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 208 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 209 /* TCC range 4 */ 210 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 211 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 212 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 213 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 214 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 215 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 216 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 217 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 218 /* TCI */ 219 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 220 /* TCP */ 221 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 222 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 223 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 224 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 225 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 226 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 227 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 228 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 229 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 230 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 231 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 232 /* TD */ 233 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 234 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 235 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 236 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 237 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 238 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 239 /* EA (3 sub-ranges) */ 240 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 241 /* EA range 0 */ 242 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 243 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 244 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 245 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 246 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 247 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 248 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 249 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 250 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 251 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 252 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 253 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 254 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 255 /* EA range 1 */ 256 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 257 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 258 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 259 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 260 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 261 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 262 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 263 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 264 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 265 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 266 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 267 /* EA range 2 */ 268 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 269 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 270 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 271 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 272 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 273 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 274 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 275 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 276 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 277 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 278 /* UTC VM L2 bank */ 279 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 280 /* UTC VM walker */ 281 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 282 /* UTC ATC L2 2MB cache */ 283 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 284 /* UTC ATC L2 4KB cache */ 285 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 286 AMDGPU_RAS_BLOCK__GFX_MAX 287 }; 288 289 enum amdgpu_ras_error_type { 290 AMDGPU_RAS_ERROR__NONE = 0, 291 AMDGPU_RAS_ERROR__PARITY = 1, 292 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 293 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 294 AMDGPU_RAS_ERROR__POISON = 8, 295 }; 296 297 enum amdgpu_ras_ret { 298 AMDGPU_RAS_SUCCESS = 0, 299 AMDGPU_RAS_FAIL, 300 AMDGPU_RAS_UE, 301 AMDGPU_RAS_CE, 302 AMDGPU_RAS_PT, 303 }; 304 305 struct ras_common_if { 306 enum amdgpu_ras_block block; 307 enum amdgpu_ras_error_type type; 308 uint32_t sub_block_index; 309 /* block name */ 310 char name[32]; 311 }; 312 313 struct amdgpu_ras { 314 /* ras infrastructure */ 315 /* for ras itself. */ 316 uint32_t hw_supported; 317 /* for IP to check its ras ability. */ 318 uint32_t supported; 319 uint32_t features; 320 struct list_head head; 321 /* debugfs */ 322 struct dentry *dir; 323 /* sysfs */ 324 struct device_attribute features_attr; 325 struct bin_attribute badpages_attr; 326 /* block array */ 327 struct ras_manager *objs; 328 329 /* gpu recovery */ 330 struct work_struct recovery_work; 331 atomic_t in_recovery; 332 struct amdgpu_device *adev; 333 /* error handler data */ 334 struct ras_err_handler_data *eh_data; 335 struct mutex recovery_lock; 336 337 uint32_t flags; 338 bool reboot; 339 struct amdgpu_ras_eeprom_control eeprom_control; 340 341 bool error_query_ready; 342 343 /* bad page count threshold */ 344 uint32_t bad_page_cnt_threshold; 345 346 /* disable ras error count harvest in recovery */ 347 bool disable_ras_err_cnt_harvest; 348 }; 349 350 struct ras_fs_data { 351 char sysfs_name[32]; 352 char debugfs_name[32]; 353 }; 354 355 struct ras_err_data { 356 unsigned long ue_count; 357 unsigned long ce_count; 358 unsigned long err_addr_cnt; 359 struct eeprom_table_record *err_addr; 360 }; 361 362 struct ras_err_handler_data { 363 /* point to bad page records array */ 364 struct eeprom_table_record *bps; 365 /* the count of entries */ 366 int count; 367 /* the space can place new entries */ 368 int space_left; 369 }; 370 371 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 372 void *err_data, 373 struct amdgpu_iv_entry *entry); 374 375 struct ras_ih_data { 376 /* interrupt bottom half */ 377 struct work_struct ih_work; 378 int inuse; 379 /* IP callback */ 380 ras_ih_cb cb; 381 /* full of entries */ 382 unsigned char *ring; 383 unsigned int ring_size; 384 unsigned int element_size; 385 unsigned int aligned_element_size; 386 unsigned int rptr; 387 unsigned int wptr; 388 }; 389 390 struct ras_manager { 391 struct ras_common_if head; 392 /* reference count */ 393 int use; 394 /* ras block link */ 395 struct list_head node; 396 /* the device */ 397 struct amdgpu_device *adev; 398 /* debugfs */ 399 struct dentry *ent; 400 /* sysfs */ 401 struct device_attribute sysfs_attr; 402 int attr_inuse; 403 404 /* fs node name */ 405 struct ras_fs_data fs_data; 406 407 /* IH data */ 408 struct ras_ih_data ih_data; 409 410 struct ras_err_data err_data; 411 }; 412 413 struct ras_badpage { 414 unsigned int bp; 415 unsigned int size; 416 unsigned int flags; 417 }; 418 419 /* interfaces for IP */ 420 struct ras_fs_if { 421 struct ras_common_if head; 422 char sysfs_name[32]; 423 char debugfs_name[32]; 424 }; 425 426 struct ras_query_if { 427 struct ras_common_if head; 428 unsigned long ue_count; 429 unsigned long ce_count; 430 }; 431 432 struct ras_inject_if { 433 struct ras_common_if head; 434 uint64_t address; 435 uint64_t value; 436 }; 437 438 struct ras_cure_if { 439 struct ras_common_if head; 440 uint64_t address; 441 }; 442 443 struct ras_ih_if { 444 struct ras_common_if head; 445 ras_ih_cb cb; 446 }; 447 448 struct ras_dispatch_if { 449 struct ras_common_if head; 450 struct amdgpu_iv_entry *entry; 451 }; 452 453 struct ras_debug_if { 454 union { 455 struct ras_common_if head; 456 struct ras_inject_if inject; 457 }; 458 int op; 459 }; 460 /* work flow 461 * vbios 462 * 1: ras feature enable (enabled by default) 463 * psp 464 * 2: ras framework init (in ip_init) 465 * IP 466 * 3: IH add 467 * 4: debugfs/sysfs create 468 * 5: query/inject 469 * 6: debugfs/sysfs remove 470 * 7: IH remove 471 * 8: feature disable 472 */ 473 474 #define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras) 475 #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras.ras = (ras_con)) 476 477 /* check if ras is supported on block, say, sdma, gfx */ 478 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev, 479 unsigned int block) 480 { 481 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 482 483 if (block >= AMDGPU_RAS_BLOCK_COUNT) 484 return 0; 485 return ras && (ras->supported & (1 << block)); 486 } 487 488 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 489 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, 490 unsigned int block); 491 492 void amdgpu_ras_resume(struct amdgpu_device *adev); 493 void amdgpu_ras_suspend(struct amdgpu_device *adev); 494 495 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, 496 bool is_ce); 497 498 bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev); 499 500 /* error handling functions */ 501 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 502 struct eeprom_table_record *bps, int pages); 503 504 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev); 505 506 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) 507 { 508 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 509 510 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) 511 schedule_work(&ras->recovery_work); 512 return 0; 513 } 514 515 static inline enum ta_ras_block 516 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 517 switch (block) { 518 case AMDGPU_RAS_BLOCK__UMC: 519 return TA_RAS_BLOCK__UMC; 520 case AMDGPU_RAS_BLOCK__SDMA: 521 return TA_RAS_BLOCK__SDMA; 522 case AMDGPU_RAS_BLOCK__GFX: 523 return TA_RAS_BLOCK__GFX; 524 case AMDGPU_RAS_BLOCK__MMHUB: 525 return TA_RAS_BLOCK__MMHUB; 526 case AMDGPU_RAS_BLOCK__ATHUB: 527 return TA_RAS_BLOCK__ATHUB; 528 case AMDGPU_RAS_BLOCK__PCIE_BIF: 529 return TA_RAS_BLOCK__PCIE_BIF; 530 case AMDGPU_RAS_BLOCK__HDP: 531 return TA_RAS_BLOCK__HDP; 532 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 533 return TA_RAS_BLOCK__XGMI_WAFL; 534 case AMDGPU_RAS_BLOCK__DF: 535 return TA_RAS_BLOCK__DF; 536 case AMDGPU_RAS_BLOCK__SMN: 537 return TA_RAS_BLOCK__SMN; 538 case AMDGPU_RAS_BLOCK__SEM: 539 return TA_RAS_BLOCK__SEM; 540 case AMDGPU_RAS_BLOCK__MP0: 541 return TA_RAS_BLOCK__MP0; 542 case AMDGPU_RAS_BLOCK__MP1: 543 return TA_RAS_BLOCK__MP1; 544 case AMDGPU_RAS_BLOCK__FUSE: 545 return TA_RAS_BLOCK__FUSE; 546 default: 547 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 548 return TA_RAS_BLOCK__UMC; 549 } 550 } 551 552 static inline enum ta_ras_error_type 553 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 554 switch (error) { 555 case AMDGPU_RAS_ERROR__NONE: 556 return TA_RAS_ERROR__NONE; 557 case AMDGPU_RAS_ERROR__PARITY: 558 return TA_RAS_ERROR__PARITY; 559 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 560 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 561 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 562 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 563 case AMDGPU_RAS_ERROR__POISON: 564 return TA_RAS_ERROR__POISON; 565 default: 566 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 567 return TA_RAS_ERROR__NONE; 568 } 569 } 570 571 /* called in ip_init and ip_fini */ 572 int amdgpu_ras_init(struct amdgpu_device *adev); 573 int amdgpu_ras_fini(struct amdgpu_device *adev); 574 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 575 int amdgpu_ras_late_init(struct amdgpu_device *adev, 576 struct ras_common_if *ras_block, 577 struct ras_fs_if *fs_info, 578 struct ras_ih_if *ih_info); 579 void amdgpu_ras_late_fini(struct amdgpu_device *adev, 580 struct ras_common_if *ras_block, 581 struct ras_ih_if *ih_info); 582 583 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 584 struct ras_common_if *head, bool enable); 585 586 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 587 struct ras_common_if *head, bool enable); 588 589 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 590 struct ras_fs_if *head); 591 592 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 593 struct ras_common_if *head); 594 595 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 596 597 int amdgpu_ras_error_query(struct amdgpu_device *adev, 598 struct ras_query_if *info); 599 600 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 601 struct ras_inject_if *info); 602 603 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 604 struct ras_ih_if *info); 605 606 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 607 struct ras_ih_if *info); 608 609 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 610 struct ras_dispatch_if *info); 611 612 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 613 struct ras_common_if *head); 614 615 extern atomic_t amdgpu_ras_in_intr; 616 617 static inline bool amdgpu_ras_intr_triggered(void) 618 { 619 return !!atomic_read(&amdgpu_ras_in_intr); 620 } 621 622 static inline void amdgpu_ras_intr_cleared(void) 623 { 624 atomic_set(&amdgpu_ras_in_intr, 0); 625 } 626 627 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 628 629 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 630 631 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 632 #endif 633