1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "ta_ras_if.h" 32 33 enum amdgpu_ras_block { 34 AMDGPU_RAS_BLOCK__UMC = 0, 35 AMDGPU_RAS_BLOCK__SDMA, 36 AMDGPU_RAS_BLOCK__GFX, 37 AMDGPU_RAS_BLOCK__MMHUB, 38 AMDGPU_RAS_BLOCK__ATHUB, 39 AMDGPU_RAS_BLOCK__PCIE_BIF, 40 AMDGPU_RAS_BLOCK__HDP, 41 AMDGPU_RAS_BLOCK__XGMI_WAFL, 42 AMDGPU_RAS_BLOCK__DF, 43 AMDGPU_RAS_BLOCK__SMN, 44 AMDGPU_RAS_BLOCK__SEM, 45 AMDGPU_RAS_BLOCK__MP0, 46 AMDGPU_RAS_BLOCK__MP1, 47 AMDGPU_RAS_BLOCK__FUSE, 48 49 AMDGPU_RAS_BLOCK__LAST 50 }; 51 52 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 53 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 54 55 enum amdgpu_ras_error_type { 56 AMDGPU_RAS_ERROR__NONE = 0, 57 AMDGPU_RAS_ERROR__PARITY = 1, 58 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 59 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 60 AMDGPU_RAS_ERROR__POISON = 8, 61 }; 62 63 enum amdgpu_ras_ret { 64 AMDGPU_RAS_SUCCESS = 0, 65 AMDGPU_RAS_FAIL, 66 AMDGPU_RAS_UE, 67 AMDGPU_RAS_CE, 68 AMDGPU_RAS_PT, 69 }; 70 71 struct ras_common_if { 72 enum amdgpu_ras_block block; 73 enum amdgpu_ras_error_type type; 74 uint32_t sub_block_index; 75 /* block name */ 76 char name[32]; 77 }; 78 79 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 80 struct amdgpu_iv_entry *entry); 81 82 struct amdgpu_ras { 83 /* ras infrastructure */ 84 /* for ras itself. */ 85 uint32_t hw_supported; 86 /* for IP to check its ras ability. */ 87 uint32_t supported; 88 uint32_t features; 89 struct list_head head; 90 /* debugfs */ 91 struct dentry *dir; 92 /* debugfs ctrl */ 93 struct dentry *ent; 94 /* sysfs */ 95 struct device_attribute features_attr; 96 struct bin_attribute badpages_attr; 97 /* block array */ 98 struct ras_manager *objs; 99 100 /* gpu recovery */ 101 struct work_struct recovery_work; 102 atomic_t in_recovery; 103 struct amdgpu_device *adev; 104 /* error handler data */ 105 struct ras_err_handler_data *eh_data; 106 struct mutex recovery_lock; 107 108 uint32_t flags; 109 }; 110 111 struct ras_ih_data { 112 /* interrupt bottom half */ 113 struct work_struct ih_work; 114 int inuse; 115 /* IP callback */ 116 ras_ih_cb cb; 117 /* full of entries */ 118 unsigned char *ring; 119 unsigned int ring_size; 120 unsigned int element_size; 121 unsigned int aligned_element_size; 122 unsigned int rptr; 123 unsigned int wptr; 124 }; 125 126 struct ras_fs_data { 127 char sysfs_name[32]; 128 char debugfs_name[32]; 129 }; 130 131 struct ras_err_data { 132 unsigned long ue_count; 133 unsigned long ce_count; 134 }; 135 136 struct ras_err_handler_data { 137 /* point to bad pages array */ 138 struct { 139 unsigned long bp; 140 struct amdgpu_bo *bo; 141 } *bps; 142 /* the count of entries */ 143 int count; 144 /* the space can place new entries */ 145 int space_left; 146 /* last reserved entry's index + 1 */ 147 int last_reserved; 148 }; 149 150 struct ras_manager { 151 struct ras_common_if head; 152 /* reference count */ 153 int use; 154 /* ras block link */ 155 struct list_head node; 156 /* the device */ 157 struct amdgpu_device *adev; 158 /* debugfs */ 159 struct dentry *ent; 160 /* sysfs */ 161 struct device_attribute sysfs_attr; 162 int attr_inuse; 163 164 /* fs node name */ 165 struct ras_fs_data fs_data; 166 167 /* IH data */ 168 struct ras_ih_data ih_data; 169 170 struct ras_err_data err_data; 171 }; 172 173 struct ras_badpage { 174 unsigned int bp; 175 unsigned int size; 176 unsigned int flags; 177 }; 178 179 /* interfaces for IP */ 180 struct ras_fs_if { 181 struct ras_common_if head; 182 char sysfs_name[32]; 183 char debugfs_name[32]; 184 }; 185 186 struct ras_query_if { 187 struct ras_common_if head; 188 unsigned long ue_count; 189 unsigned long ce_count; 190 }; 191 192 struct ras_inject_if { 193 struct ras_common_if head; 194 uint64_t address; 195 uint64_t value; 196 }; 197 198 struct ras_cure_if { 199 struct ras_common_if head; 200 uint64_t address; 201 }; 202 203 struct ras_ih_if { 204 struct ras_common_if head; 205 ras_ih_cb cb; 206 }; 207 208 struct ras_dispatch_if { 209 struct ras_common_if head; 210 struct amdgpu_iv_entry *entry; 211 }; 212 213 struct ras_debug_if { 214 union { 215 struct ras_common_if head; 216 struct ras_inject_if inject; 217 }; 218 int op; 219 }; 220 /* work flow 221 * vbios 222 * 1: ras feature enable (enabled by default) 223 * psp 224 * 2: ras framework init (in ip_init) 225 * IP 226 * 3: IH add 227 * 4: debugfs/sysfs create 228 * 5: query/inject 229 * 6: debugfs/sysfs remove 230 * 7: IH remove 231 * 8: feature disable 232 */ 233 234 #define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras) 235 #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras.ras = (ras_con)) 236 237 /* check if ras is supported on block, say, sdma, gfx */ 238 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev, 239 unsigned int block) 240 { 241 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 242 243 if (block >= AMDGPU_RAS_BLOCK_COUNT) 244 return 0; 245 return ras && (ras->supported & (1 << block)); 246 } 247 248 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, 249 unsigned int block); 250 251 void amdgpu_ras_resume(struct amdgpu_device *adev); 252 void amdgpu_ras_suspend(struct amdgpu_device *adev); 253 254 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 255 bool is_ce); 256 257 /* error handling functions */ 258 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 259 unsigned long *bps, int pages); 260 261 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev); 262 263 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev, 264 bool is_baco) 265 { 266 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 267 268 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) 269 schedule_work(&ras->recovery_work); 270 return 0; 271 } 272 273 static inline enum ta_ras_block 274 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 275 switch (block) { 276 case AMDGPU_RAS_BLOCK__UMC: 277 return TA_RAS_BLOCK__UMC; 278 case AMDGPU_RAS_BLOCK__SDMA: 279 return TA_RAS_BLOCK__SDMA; 280 case AMDGPU_RAS_BLOCK__GFX: 281 return TA_RAS_BLOCK__GFX; 282 case AMDGPU_RAS_BLOCK__MMHUB: 283 return TA_RAS_BLOCK__MMHUB; 284 case AMDGPU_RAS_BLOCK__ATHUB: 285 return TA_RAS_BLOCK__ATHUB; 286 case AMDGPU_RAS_BLOCK__PCIE_BIF: 287 return TA_RAS_BLOCK__PCIE_BIF; 288 case AMDGPU_RAS_BLOCK__HDP: 289 return TA_RAS_BLOCK__HDP; 290 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 291 return TA_RAS_BLOCK__XGMI_WAFL; 292 case AMDGPU_RAS_BLOCK__DF: 293 return TA_RAS_BLOCK__DF; 294 case AMDGPU_RAS_BLOCK__SMN: 295 return TA_RAS_BLOCK__SMN; 296 case AMDGPU_RAS_BLOCK__SEM: 297 return TA_RAS_BLOCK__SEM; 298 case AMDGPU_RAS_BLOCK__MP0: 299 return TA_RAS_BLOCK__MP0; 300 case AMDGPU_RAS_BLOCK__MP1: 301 return TA_RAS_BLOCK__MP1; 302 case AMDGPU_RAS_BLOCK__FUSE: 303 return TA_RAS_BLOCK__FUSE; 304 default: 305 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 306 return TA_RAS_BLOCK__UMC; 307 } 308 } 309 310 static inline enum ta_ras_error_type 311 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 312 switch (error) { 313 case AMDGPU_RAS_ERROR__NONE: 314 return TA_RAS_ERROR__NONE; 315 case AMDGPU_RAS_ERROR__PARITY: 316 return TA_RAS_ERROR__PARITY; 317 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 318 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 319 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 320 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 321 case AMDGPU_RAS_ERROR__POISON: 322 return TA_RAS_ERROR__POISON; 323 default: 324 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 325 return TA_RAS_ERROR__NONE; 326 } 327 } 328 329 /* called in ip_init and ip_fini */ 330 int amdgpu_ras_init(struct amdgpu_device *adev); 331 int amdgpu_ras_fini(struct amdgpu_device *adev); 332 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 333 334 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 335 struct ras_common_if *head, bool enable); 336 337 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 338 struct ras_common_if *head, bool enable); 339 340 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 341 struct ras_fs_if *head); 342 343 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 344 struct ras_common_if *head); 345 346 void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 347 struct ras_fs_if *head); 348 349 void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 350 struct ras_common_if *head); 351 352 int amdgpu_ras_error_query(struct amdgpu_device *adev, 353 struct ras_query_if *info); 354 355 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 356 struct ras_inject_if *info); 357 358 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 359 struct ras_ih_if *info); 360 361 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 362 struct ras_ih_if *info); 363 364 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 365 struct ras_dispatch_if *info); 366 #endif 367